This document discusses space vector pulse width modulation (SVPWM) techniques for multilevel inverters. It begins by introducing SVPWM and explaining that it provides advantages over sinusoidal PWM, including better fundamental output voltage and improved harmonic performance. It then defines two-dimensional and three-dimensional space vectors and discusses how SVPWM can be implemented in both 2D and 3D. The document focuses on SVPWM for three-leg voltage source inverters, describing the voltage space vectors and how SVPWM can be used to synthesize the required output voltage vector through PWM of the switching state vectors.
The document discusses pulse width modulation (PWM) variable speed drives that are increasingly used in industrial applications. It describes how PWM is used to generate variable voltage and frequency for AC drives from a three-phase voltage source inverter. Space vector PWM (SVPWM) is highlighted as it provides superior harmonic quality and larger modulation range compared to sinusoidal PWM. SVPWM represents the inverter states as voltage space vectors to calculate duty cycles for adjacent vectors and zero vectors to synthesize the desired output voltage vector. The document outlines the theory of SVPWM and compares different sequencing methods. It also discusses simulations and advantages of PWM including proportional average value, fast switching, noise resistance and less heat.
This document describes a simulation project of a space vector PWM inverter. It provides details of the system configuration including IGBT switches, DC link voltage, frequencies, and load components. It then provides an in-depth explanation of space vector PWM technique, including the principle of PWM, representation of voltage vectors in the dq reference frame, and algorithm for determining switching times. State-space equations for the L-C output filter are also derived. The overall purpose is to simulate and analyze a three-phase PWM inverter using space vector modulation in MATLAB/Simulink.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
Application of SVM Technique for Three Phase Three Leg Ac/Ac Converter TopologyIOSR Journals
This paper presents a simulation of a three-phase three-leg AC/AC converter topology using nine IGBTs and space vector pulse width modulation (SVM) technique. The proposed topology reduces the number of switches compared to conventional back-to-back and matrix converters. Simulation results show the converter provides sinusoidal input and output voltages with unity power factor under constant frequency and variable frequency operation. Experimental results from a 5kVA prototype verify the validity of the proposed scheme.
This document presents a simplified model predictive control methodology for a three-phase four-leg voltage source inverter (VSI). Compared to traditional three-leg VSIs, four-leg VSIs increase possible switch states from 8 to 16. The proposed method uses a three-dimensional space vector pulse width modulation technique to preselect 5 out of the 16 possible voltage vectors. A discrete-time model of the future reference voltage vector is used to predict future load current movements. The position of this vector is then used to select the 5 preselected vectors at each sampling period. This reduces computational load compared to evaluating all 16 vectors, while maintaining performance. Simulation results demonstrate the effectiveness of the proposed predictive control methodology.
Space Vector Modulation in Voltage Sourced Three Level Neutral Point Clamped ...emredurna
The document discusses a 3-level neutral point clamped (NPC) inverter. It has three voltage levels for each phase (+E, 0, -E) and uses space vector modulation (SVM) to generate reference voltages. SVM divides the voltage space into sectors and regions, then uses different combinations of the inverter's switching states to synthesize the reference voltage over small time intervals. Dwell times are calculated to determine how long each switching state is applied. Several SVM switching sequences are presented, including a seven-segment sequence. Simulation waveforms show the output voltage and current are close to sinusoidal.
Modelling and Simulation of a Sensorless Control of a True Asymmetric Cascade...IJPEDS-IAES
This paper introduces a new method to track the saliency of an AC motor fed
by a multilevel converter through measuring the dynamic current response of
the motor line currents due the IGBT switching actions. The method uses
only the fundamental PWM waveform (i.e there is no modification to the
operation of the multilevel converter) similar to the fundamental PWM
method proposed for a 2-level converter. Simulation results are provided to
demonstrate the performance of the complete sensorless speed control of a
PM motor driven by such a converter over a wide speed range. Finally the
paper introduces a comparison between the 2-level converter and the
multilevel converter in terms of the reduction of the total harmonic distortion
(THD) using the fundamental PWM method in both cases.
This document summarizes a research paper on implementing hysteresis control for space vector pulse width modulation (SVPWM) inverters. It begins by introducing SVPWM and total harmonic distortion (THD). It then describes the principles of SVPWM, including determining switching times and patterns. Next, it defines the hysteresis band control method using a relay function. The document proceeds to model the inverter and describe the switching interval generator and control signal generator blocks. Finally, it provides an overview of the simulation model, which combines hysteresis control with SVPWM.
The document discusses pulse width modulation (PWM) variable speed drives that are increasingly used in industrial applications. It describes how PWM is used to generate variable voltage and frequency for AC drives from a three-phase voltage source inverter. Space vector PWM (SVPWM) is highlighted as it provides superior harmonic quality and larger modulation range compared to sinusoidal PWM. SVPWM represents the inverter states as voltage space vectors to calculate duty cycles for adjacent vectors and zero vectors to synthesize the desired output voltage vector. The document outlines the theory of SVPWM and compares different sequencing methods. It also discusses simulations and advantages of PWM including proportional average value, fast switching, noise resistance and less heat.
This document describes a simulation project of a space vector PWM inverter. It provides details of the system configuration including IGBT switches, DC link voltage, frequencies, and load components. It then provides an in-depth explanation of space vector PWM technique, including the principle of PWM, representation of voltage vectors in the dq reference frame, and algorithm for determining switching times. State-space equations for the L-C output filter are also derived. The overall purpose is to simulate and analyze a three-phase PWM inverter using space vector modulation in MATLAB/Simulink.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
Application of SVM Technique for Three Phase Three Leg Ac/Ac Converter TopologyIOSR Journals
This paper presents a simulation of a three-phase three-leg AC/AC converter topology using nine IGBTs and space vector pulse width modulation (SVM) technique. The proposed topology reduces the number of switches compared to conventional back-to-back and matrix converters. Simulation results show the converter provides sinusoidal input and output voltages with unity power factor under constant frequency and variable frequency operation. Experimental results from a 5kVA prototype verify the validity of the proposed scheme.
This document presents a simplified model predictive control methodology for a three-phase four-leg voltage source inverter (VSI). Compared to traditional three-leg VSIs, four-leg VSIs increase possible switch states from 8 to 16. The proposed method uses a three-dimensional space vector pulse width modulation technique to preselect 5 out of the 16 possible voltage vectors. A discrete-time model of the future reference voltage vector is used to predict future load current movements. The position of this vector is then used to select the 5 preselected vectors at each sampling period. This reduces computational load compared to evaluating all 16 vectors, while maintaining performance. Simulation results demonstrate the effectiveness of the proposed predictive control methodology.
Space Vector Modulation in Voltage Sourced Three Level Neutral Point Clamped ...emredurna
The document discusses a 3-level neutral point clamped (NPC) inverter. It has three voltage levels for each phase (+E, 0, -E) and uses space vector modulation (SVM) to generate reference voltages. SVM divides the voltage space into sectors and regions, then uses different combinations of the inverter's switching states to synthesize the reference voltage over small time intervals. Dwell times are calculated to determine how long each switching state is applied. Several SVM switching sequences are presented, including a seven-segment sequence. Simulation waveforms show the output voltage and current are close to sinusoidal.
Modelling and Simulation of a Sensorless Control of a True Asymmetric Cascade...IJPEDS-IAES
This paper introduces a new method to track the saliency of an AC motor fed
by a multilevel converter through measuring the dynamic current response of
the motor line currents due the IGBT switching actions. The method uses
only the fundamental PWM waveform (i.e there is no modification to the
operation of the multilevel converter) similar to the fundamental PWM
method proposed for a 2-level converter. Simulation results are provided to
demonstrate the performance of the complete sensorless speed control of a
PM motor driven by such a converter over a wide speed range. Finally the
paper introduces a comparison between the 2-level converter and the
multilevel converter in terms of the reduction of the total harmonic distortion
(THD) using the fundamental PWM method in both cases.
This document summarizes a research paper on implementing hysteresis control for space vector pulse width modulation (SVPWM) inverters. It begins by introducing SVPWM and total harmonic distortion (THD). It then describes the principles of SVPWM, including determining switching times and patterns. Next, it defines the hysteresis band control method using a relay function. The document proceeds to model the inverter and describe the switching interval generator and control signal generator blocks. Finally, it provides an overview of the simulation model, which combines hysteresis control with SVPWM.
Harmonic comparisons of various pwm techniques... A reportSaquib Maqsood
Abstract: Cascaded inverters are ideal for connecting renewable energy sources with an AC grid, because of the need for separate dc sources, which is the case in applications such as photovoltaic or fuel cells. The inverter could be controlled to either regulate the power factor of the current drawn from the source or the bus voltage of the electrical system where the inverter was connected. The modulation techniques are crucial in operating any inverter at desired conditions. In this work different PWM techniques are implemented for five level cascaded multilevel inverter and THD variation is analyzed.
Multiphase Transformer Modelling using Finite Element MethodIAES-IJPEDS
In the year of 1970 saw the starting invention of the five-phase motor as the milestone in advanced electric motor. Through the years, there are many researchers, which passionately worked towards developing for multiphase drive system. They developed a static transformation system to obtain a multiphase supply from the available three-phase supply. This idea gives an influence for further development in electric machines as an example; an efficient solution for bulk power transfer. This paper highlighted the detail descriptions that lead to five-phase supply with fixed voltage and frequency by using Finite-Element Method (FEM). Identifying of specification on a real transformer had been done before applied into software modeling. Therefore, Finite-Element Method provides clearly understandable in terms of visualize the geometry modeling, connection scheme and output waveform.
Space Vector Pulse Width Modulation Technique Applied to Two Level Voltage So...Qusai Abdelrahman
Space vector pulse width modulation SVPWM provides a better technique compared to the other pulse width modulation techniques. This paper presents simulation and implementation of SVPWM signal generation for driving three phase two level voltage source inverter VSI, also proposes and analyzes a new switching sequence for generating an SVPWM. Simulation results are obtained using the simulation package PSIM. and the inverter performance is evaluated in terms of total harmonic distortion (THD). The model is experimentally implemented and verified on Arduino Mega Atmega2560 microcontroller.
Modeling and Simulation of SVPWM Based ApplicationIJAPEJOURNAL
Recent developments in power electronics and semiconductor technology have lead to widespread use of power electronic converters in the power electronic systems. A number of Pulse width modulation (PWM) schemes are used to obtain variable voltage and frequency supply from a three-phase voltage source inverter. Among the different PWM techniques proposed for voltage fed inverters, the sinusoidal PWM technique has been popularly accepted. But there is an increasing trend of using space vector PWM (SVPWM) because of their easier digital realization, reduced harmonics, reduced switching losses and better dc bus utilization. This project focuses on step by step development of SVPWM technique. Simulation results are obtained using MATLAB/Simulink software for effectiveness of the study.
Implementation of Space Vector Modulator for Cascaded H-Bridge Multilevel Inv...IJPEDS-IAES
The Space Vector Modulation (SVM) technique has gained wide acceptance
for many AC drive applications, due to a higher DC bus voltage utilization
(higher output voltage when compared with the SPWM), lower harmonic
distortions and easy digital realization. In recent years, the SVM technique
was extensively adopted in multilevel inverters since it offers greater
numbers of switching vectors for obtaining further improvements of AC
drive performances. However, the use of multilevel inverters associated with
SVM increases the complexity of control algorithm (or computational
burden), in obtaining proper switching sequences and vectors. The
complexity of SVM computation causes a microcontroller or digital signal
processor (DSP) to execute the computation at a larger sampling time. This
consequently may produce errors in computation and hence degrades the
control performances of AC motor drives. This paper presents a
developement of SVM modulator for three-level Cascaded H-Bridge
Multilevel Inverter (CHMI) using a hybrid controller approach, i.e. with
combination between the DS1104 Controller Board and FPGA. In such way,
the computational burden can be minimized as the SVM tasks are distributed
into two parts, in which every part is executed by a single controller. This
allows the generation of switching gates performed by FPGA at the
minimum sampling time ܦܶଶ ൌ 540 ݊ݏ to obtain precise desired output
voltages, as can be verified via simulation and experimental results.
PWM control techniques for three phase three level inverter drivesTELKOMNIKA JOURNAL
In this paper two very efficient pulse width modulation techniques were discussed named Sin pulse width modulation and space vector pulse width modulation. The basic structure of the three-level inverter neutral-point clamped is introduced and the basic idea about space vector pulse width modulation for three-level voltage source inverter has been discussed in detail. Nearest three vectors space vector pulse width modulation control algorithm is adopted as the control strategy for the three phase three level NPC inverter in order to compensate the neutral-point shifting. Mathematical formulation for calculating switching sequence has determined. Comparative analysis proving superiority of the space vector pulse width modulation technique over the conventional pulse width modulation, and the results of the simulations of inverter confirm the feasibility and advantage of the space vector pulse width modulation strategy over sin pulse width modulation in terms of good utilization of dc-bus voltage, low current ripple and reduced switching frequency. Space vector pulse width modulation provides advantages better fundamental output voltage and useful in improving harmonic performance and reducing total harmonic distortion.
Two leg three-phase inverters (FSTPIs) have been proposed to be used in low-power; low-cost applications because of the reduced number of semiconductor devices, and space vector pulse width modulation (SVPWM) techniques have also been introduced to control FSTPIs. However, high-performance controllers are needed to implement complicated SVPWM algorithms, which limit their low-cost applications. To simplify algorithms and reduce the cost of implementation, an equivalent scalar method for SVPWM of FSTPIs is proposed. SVPWM for FSTPIs is actually a sine PWM by modulating two sine waves of 600 phase difference with a triangle wave, but in this method third harmonics doesn’t eliminated. So as to eliminate the third harmonics we have to compose a high frequency sine wave to on existing sine waves. So such a special sine PWM can be used to control FSTPIs. The Mathematical and simulation results demonstrate the validity of the proposed method.
http://www.mathworks.com/matlabcentral/fileexchange/authors/126814
Performance of a voltage source inverter depends on pulse width modulation algorithms. Various algorithms exist for conventional space vector as well as space vector based bus clamped pulse width modulation for multilevel inverter in the literature. In this paper appropriate region selection algorithm for conventional space vector pulse width modulation (CSVPWM) and bus clamped pulse width modulation (BCPWM) techniques are proposed for diode clamped three level voltage source inverter. The proposed techniques are implemented on a three level voltage source inverter fed induction motor drive for open loop operation. The schemes are simulated in MATLAB/SIMULINK environments. The merit of proposed region selection algorithm is tested and verified through simulation result. Further performance comparisons between SVPWM and BCPWM for different modulation index are discussed.
One of the preferred choices of electronic power conversion for high power applications are multilevel inverters topologies finding increased attention in industry. Cascaded H-Bridge multilevel inverter is one of these topologies reaching the higher output voltage, power level and higher reliability due to its modular topology. Level Shifted Carrier Pulse Width Modulation (LSCPWM) and Phase Shifted Carrier Pulse Width Modulation are used generally for switching cascaded H-bridge (CHB) multilevel inverters. This paper compares LSCPWM and PSCPWM in terms of total harmonics distortion (THD) and output voltage among inverter cells. Simulation for 21-level CHB inverter is carried out in MATLAB/SIMULINK and simulation results are presented.
This document presents a comparative study of five-level and seven-level diode-clamped inverters controlled by space vector pulse width modulation (SVPWM). MATLAB/SIMULINK models of the two inverter topologies were developed. SVPWM control algorithms based on symmetrical sequence were used for each inverter. Both inverters were simulated driving an induction motor. The results showed that the seven-level inverter produced less harmonic distortion and torque fluctuations in the motor, while the five-level inverter had lower commutation losses. The seven-level inverter provided better motor dynamic response.
This document describes a simulation of a space vector PWM controller for a five-level voltage-fed inverter motor drive. It begins by introducing multilevel inverters and some of the challenges in controlling them, specifically the increased complexity with more levels. It then presents a new approach to implementing space vector PWM for a five-level inverter by treating it as a conventional two-level system, making the calculations simpler. The methodology and implementation are described, including estimating switching times. Simulation results are presented showing the current, voltage and THD waveforms both with and without an LC filter. It is concluded that the proposed 2D system approach allows for simple implementation of SVPWM for a five-level inverter using common D
Total Harmonic Distortion of Dodecagonal Space Vector ModulationIJPEDS-IAES
Space vector modulation technique is one of the best PWM techniques which have been implemented to the Multilevel inverter circuit to get the purely sinusoidal cuurent. This is a important algorithm which is implemented in open wind induction motor. This type of I.M has great impact on Electric Drive system. SVM is nothing but the technique of switching algorithm. The Hexagonal space vector modulation has been implemented before, but elimination of higher order harmonics is not possible. Torque pulsation arises. Speed control of Induction motor was not smooth. So Dodecagonal (12) structure developed. A 12 side polygonal space vector structure is meant for eliminating (6n±1) harmonics in the phase current waveform throughout the modulating range. A high resolution of PWM technique is proposed involving multiple 12 sided polygonal (Dodecagonal) structure that can generate highly sinusoidal voltage at a reduced switching frequency. In this paper different values of frequencies have been taken for harmonic analysis. SVM method features a higher level of dc-bus voltage utilization compared to the conventional PWM.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document presents an implementation of space vector modulation (SVM) for a two-level three-phase inverter using a dSPACE DS1104 controller. It describes the principles of SVM, including voltage vector modeling, sector detection, and pulse generation. Hardware experiments were conducted to validate a SVM control algorithm developed in Simulink. Results showed line voltages from the real hardware matched simulation. THD comparisons confirmed SVM provides lower distortion and higher fundamental output than sinusoidal PWM. The dSPACE system allows real-time testing of control algorithms on actual hardware.
A Refined Space Vector PWM Signal Generation for Multilevel InvertersIDES Editor
A refined space vector modulation scheme for
multilevel inverters, using only the instantaneous sampled
reference signals is presented in this paper. The proposed
space vector pulse width modulation technique does not require
the sector information and look-up tables to select the
appropriate switching vectors. The inverter leg switching times
are directly obtained from the instantaneous sampled
reference signal amplitudes and centers the switching times
for the middle space vectors in a sampling time interval, as in
the case of conventional space vector pulse width modulation.
The simulation results are presented to a five-level inverter
system for dual-fed induction motor drive. The dual-fed
structure is realized by opening the neutral-point of the
conventional squirrel cage induction motor. The five-level
inversion is obtained by feeding the dual-fed induction motor
with four-level inverter from one end and two-level inverter
from the other end.
An Implementation Mechanisms of SVM Control Strategies Applied to Five Levels...IJPEDS-IAES
In the area of the energy control with high voltage and power, the multilevel inverters constitute a relatively recent research orientation. The current applications of this technology are in the domains of the high voltage (over hundred kV), variable speed drives, transport and distribution of a good quality of electrical energy (HVDC, FACTS system, ....). To improve the output voltage for such inverters, many different modulation strategies have been developed. Among these strategies, the SVM (Space Vector Modulation). The technique provide the nearest switching vectors sequence to the reference vector without involving trigonometric functions and provide the additional advantages of superior harmonic quality. In this paper, we analyze different mechanisms of the output voltage synthesis and the problem of even order harmonic production. With the proposed a new trajectory SVM, which can eliminate all the even order harmonics for five levels inverter. Show clearly how to deduce the trajectories from the sequences allowing to have better performances among several possible trajectories. It is dedicated to the application of two particular trajectories.
Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascad...IJAAS Team
This paper presents unipolar pulse width modulation technique with sinusoidal sampling pulse width modulation are analyzed for three-phase five-level, seven-level, nine-level and eleven-level cascaded multi-level inverter. The unipolar PWM method offers a good opportunity for the realization of the Three-phase inverter control, it is better to use the unipolar PWM method with single carrier wave compared to two reference waves. In such case the motor harmonic losses will be considerably lower.The necessary calculations for generation of unipolar pulse width modulation strategies have presented in detail. The unipolar SPWM voltage switching scheme is selected in this paper because this method offers the advantages of effectively doubling the switching frequency of the inverter voltage. The cascaded multi level inverter fed induction motor is simulated and compared the total harmonic distroction for all level (five-level, seven-level, nine-level and elevel-level)of the inverter. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Multilevel inverters are emerging as the new breed of power converter options for high power applications. They typically synthesis the staircase voltage waveform (from several dc sources) which reduced harmonic content. This paper presents a simple selective harmonic elimination (SHE) modulation for single-phase cascaded H-bridge (CHB) multilevel inverter. The optimum switching angle of the transcendental equations describing the fundamental and harmonic components is solved by means of the Newton-Raphson (NR) method. The proposed SHE scheme is performed through simulation using MATLAB/Simulink. This simulation results are then verified through experiment using Altera DE0-Nano field-programmable gate array (FPGA). The proposed SHE is efficient in eliminating the lowest-order harmonics and producing a higher quality output waveform with a better harmonic profile.
This document discusses issues related to integrating distributed energy resources (DER) into electric power grids. It provides background on DER definitions and classifications. It addresses grid integration and interconnection standards, including requirements for steady state and transient operations, protection, and islanding detection. The document outlines considerations for DER protection and control requirements to safely interconnect DER while maintaining grid reliability. It also presents examples of DER installations and research on advanced relay techniques for islanding detection.
This document discusses unintentional islanding of power systems with distributed resources like solar PV. It defines intentional and unintentional islands, and issues with unintentional islands like safety hazards, overvoltages, and loss of protection. Methods to detect unintentional islands are described, like reverse power relays and active techniques. Simulation results show one technique detecting an island within 0.5 cycles. Guidelines for assessing islanding risk are provided, and the future of anti-islanding techniques discussed, like the potential need for multiple active methods with reduced grid stiffness.
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Harmonic comparisons of various pwm techniques... A reportSaquib Maqsood
Abstract: Cascaded inverters are ideal for connecting renewable energy sources with an AC grid, because of the need for separate dc sources, which is the case in applications such as photovoltaic or fuel cells. The inverter could be controlled to either regulate the power factor of the current drawn from the source or the bus voltage of the electrical system where the inverter was connected. The modulation techniques are crucial in operating any inverter at desired conditions. In this work different PWM techniques are implemented for five level cascaded multilevel inverter and THD variation is analyzed.
Multiphase Transformer Modelling using Finite Element MethodIAES-IJPEDS
In the year of 1970 saw the starting invention of the five-phase motor as the milestone in advanced electric motor. Through the years, there are many researchers, which passionately worked towards developing for multiphase drive system. They developed a static transformation system to obtain a multiphase supply from the available three-phase supply. This idea gives an influence for further development in electric machines as an example; an efficient solution for bulk power transfer. This paper highlighted the detail descriptions that lead to five-phase supply with fixed voltage and frequency by using Finite-Element Method (FEM). Identifying of specification on a real transformer had been done before applied into software modeling. Therefore, Finite-Element Method provides clearly understandable in terms of visualize the geometry modeling, connection scheme and output waveform.
Space Vector Pulse Width Modulation Technique Applied to Two Level Voltage So...Qusai Abdelrahman
Space vector pulse width modulation SVPWM provides a better technique compared to the other pulse width modulation techniques. This paper presents simulation and implementation of SVPWM signal generation for driving three phase two level voltage source inverter VSI, also proposes and analyzes a new switching sequence for generating an SVPWM. Simulation results are obtained using the simulation package PSIM. and the inverter performance is evaluated in terms of total harmonic distortion (THD). The model is experimentally implemented and verified on Arduino Mega Atmega2560 microcontroller.
Modeling and Simulation of SVPWM Based ApplicationIJAPEJOURNAL
Recent developments in power electronics and semiconductor technology have lead to widespread use of power electronic converters in the power electronic systems. A number of Pulse width modulation (PWM) schemes are used to obtain variable voltage and frequency supply from a three-phase voltage source inverter. Among the different PWM techniques proposed for voltage fed inverters, the sinusoidal PWM technique has been popularly accepted. But there is an increasing trend of using space vector PWM (SVPWM) because of their easier digital realization, reduced harmonics, reduced switching losses and better dc bus utilization. This project focuses on step by step development of SVPWM technique. Simulation results are obtained using MATLAB/Simulink software for effectiveness of the study.
Implementation of Space Vector Modulator for Cascaded H-Bridge Multilevel Inv...IJPEDS-IAES
The Space Vector Modulation (SVM) technique has gained wide acceptance
for many AC drive applications, due to a higher DC bus voltage utilization
(higher output voltage when compared with the SPWM), lower harmonic
distortions and easy digital realization. In recent years, the SVM technique
was extensively adopted in multilevel inverters since it offers greater
numbers of switching vectors for obtaining further improvements of AC
drive performances. However, the use of multilevel inverters associated with
SVM increases the complexity of control algorithm (or computational
burden), in obtaining proper switching sequences and vectors. The
complexity of SVM computation causes a microcontroller or digital signal
processor (DSP) to execute the computation at a larger sampling time. This
consequently may produce errors in computation and hence degrades the
control performances of AC motor drives. This paper presents a
developement of SVM modulator for three-level Cascaded H-Bridge
Multilevel Inverter (CHMI) using a hybrid controller approach, i.e. with
combination between the DS1104 Controller Board and FPGA. In such way,
the computational burden can be minimized as the SVM tasks are distributed
into two parts, in which every part is executed by a single controller. This
allows the generation of switching gates performed by FPGA at the
minimum sampling time ܦܶଶ ൌ 540 ݊ݏ to obtain precise desired output
voltages, as can be verified via simulation and experimental results.
PWM control techniques for three phase three level inverter drivesTELKOMNIKA JOURNAL
In this paper two very efficient pulse width modulation techniques were discussed named Sin pulse width modulation and space vector pulse width modulation. The basic structure of the three-level inverter neutral-point clamped is introduced and the basic idea about space vector pulse width modulation for three-level voltage source inverter has been discussed in detail. Nearest three vectors space vector pulse width modulation control algorithm is adopted as the control strategy for the three phase three level NPC inverter in order to compensate the neutral-point shifting. Mathematical formulation for calculating switching sequence has determined. Comparative analysis proving superiority of the space vector pulse width modulation technique over the conventional pulse width modulation, and the results of the simulations of inverter confirm the feasibility and advantage of the space vector pulse width modulation strategy over sin pulse width modulation in terms of good utilization of dc-bus voltage, low current ripple and reduced switching frequency. Space vector pulse width modulation provides advantages better fundamental output voltage and useful in improving harmonic performance and reducing total harmonic distortion.
Two leg three-phase inverters (FSTPIs) have been proposed to be used in low-power; low-cost applications because of the reduced number of semiconductor devices, and space vector pulse width modulation (SVPWM) techniques have also been introduced to control FSTPIs. However, high-performance controllers are needed to implement complicated SVPWM algorithms, which limit their low-cost applications. To simplify algorithms and reduce the cost of implementation, an equivalent scalar method for SVPWM of FSTPIs is proposed. SVPWM for FSTPIs is actually a sine PWM by modulating two sine waves of 600 phase difference with a triangle wave, but in this method third harmonics doesn’t eliminated. So as to eliminate the third harmonics we have to compose a high frequency sine wave to on existing sine waves. So such a special sine PWM can be used to control FSTPIs. The Mathematical and simulation results demonstrate the validity of the proposed method.
http://www.mathworks.com/matlabcentral/fileexchange/authors/126814
Performance of a voltage source inverter depends on pulse width modulation algorithms. Various algorithms exist for conventional space vector as well as space vector based bus clamped pulse width modulation for multilevel inverter in the literature. In this paper appropriate region selection algorithm for conventional space vector pulse width modulation (CSVPWM) and bus clamped pulse width modulation (BCPWM) techniques are proposed for diode clamped three level voltage source inverter. The proposed techniques are implemented on a three level voltage source inverter fed induction motor drive for open loop operation. The schemes are simulated in MATLAB/SIMULINK environments. The merit of proposed region selection algorithm is tested and verified through simulation result. Further performance comparisons between SVPWM and BCPWM for different modulation index are discussed.
One of the preferred choices of electronic power conversion for high power applications are multilevel inverters topologies finding increased attention in industry. Cascaded H-Bridge multilevel inverter is one of these topologies reaching the higher output voltage, power level and higher reliability due to its modular topology. Level Shifted Carrier Pulse Width Modulation (LSCPWM) and Phase Shifted Carrier Pulse Width Modulation are used generally for switching cascaded H-bridge (CHB) multilevel inverters. This paper compares LSCPWM and PSCPWM in terms of total harmonics distortion (THD) and output voltage among inverter cells. Simulation for 21-level CHB inverter is carried out in MATLAB/SIMULINK and simulation results are presented.
This document presents a comparative study of five-level and seven-level diode-clamped inverters controlled by space vector pulse width modulation (SVPWM). MATLAB/SIMULINK models of the two inverter topologies were developed. SVPWM control algorithms based on symmetrical sequence were used for each inverter. Both inverters were simulated driving an induction motor. The results showed that the seven-level inverter produced less harmonic distortion and torque fluctuations in the motor, while the five-level inverter had lower commutation losses. The seven-level inverter provided better motor dynamic response.
This document describes a simulation of a space vector PWM controller for a five-level voltage-fed inverter motor drive. It begins by introducing multilevel inverters and some of the challenges in controlling them, specifically the increased complexity with more levels. It then presents a new approach to implementing space vector PWM for a five-level inverter by treating it as a conventional two-level system, making the calculations simpler. The methodology and implementation are described, including estimating switching times. Simulation results are presented showing the current, voltage and THD waveforms both with and without an LC filter. It is concluded that the proposed 2D system approach allows for simple implementation of SVPWM for a five-level inverter using common D
Total Harmonic Distortion of Dodecagonal Space Vector ModulationIJPEDS-IAES
Space vector modulation technique is one of the best PWM techniques which have been implemented to the Multilevel inverter circuit to get the purely sinusoidal cuurent. This is a important algorithm which is implemented in open wind induction motor. This type of I.M has great impact on Electric Drive system. SVM is nothing but the technique of switching algorithm. The Hexagonal space vector modulation has been implemented before, but elimination of higher order harmonics is not possible. Torque pulsation arises. Speed control of Induction motor was not smooth. So Dodecagonal (12) structure developed. A 12 side polygonal space vector structure is meant for eliminating (6n±1) harmonics in the phase current waveform throughout the modulating range. A high resolution of PWM technique is proposed involving multiple 12 sided polygonal (Dodecagonal) structure that can generate highly sinusoidal voltage at a reduced switching frequency. In this paper different values of frequencies have been taken for harmonic analysis. SVM method features a higher level of dc-bus voltage utilization compared to the conventional PWM.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document presents an implementation of space vector modulation (SVM) for a two-level three-phase inverter using a dSPACE DS1104 controller. It describes the principles of SVM, including voltage vector modeling, sector detection, and pulse generation. Hardware experiments were conducted to validate a SVM control algorithm developed in Simulink. Results showed line voltages from the real hardware matched simulation. THD comparisons confirmed SVM provides lower distortion and higher fundamental output than sinusoidal PWM. The dSPACE system allows real-time testing of control algorithms on actual hardware.
A Refined Space Vector PWM Signal Generation for Multilevel InvertersIDES Editor
A refined space vector modulation scheme for
multilevel inverters, using only the instantaneous sampled
reference signals is presented in this paper. The proposed
space vector pulse width modulation technique does not require
the sector information and look-up tables to select the
appropriate switching vectors. The inverter leg switching times
are directly obtained from the instantaneous sampled
reference signal amplitudes and centers the switching times
for the middle space vectors in a sampling time interval, as in
the case of conventional space vector pulse width modulation.
The simulation results are presented to a five-level inverter
system for dual-fed induction motor drive. The dual-fed
structure is realized by opening the neutral-point of the
conventional squirrel cage induction motor. The five-level
inversion is obtained by feeding the dual-fed induction motor
with four-level inverter from one end and two-level inverter
from the other end.
An Implementation Mechanisms of SVM Control Strategies Applied to Five Levels...IJPEDS-IAES
In the area of the energy control with high voltage and power, the multilevel inverters constitute a relatively recent research orientation. The current applications of this technology are in the domains of the high voltage (over hundred kV), variable speed drives, transport and distribution of a good quality of electrical energy (HVDC, FACTS system, ....). To improve the output voltage for such inverters, many different modulation strategies have been developed. Among these strategies, the SVM (Space Vector Modulation). The technique provide the nearest switching vectors sequence to the reference vector without involving trigonometric functions and provide the additional advantages of superior harmonic quality. In this paper, we analyze different mechanisms of the output voltage synthesis and the problem of even order harmonic production. With the proposed a new trajectory SVM, which can eliminate all the even order harmonics for five levels inverter. Show clearly how to deduce the trajectories from the sequences allowing to have better performances among several possible trajectories. It is dedicated to the application of two particular trajectories.
Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascad...IJAAS Team
This paper presents unipolar pulse width modulation technique with sinusoidal sampling pulse width modulation are analyzed for three-phase five-level, seven-level, nine-level and eleven-level cascaded multi-level inverter. The unipolar PWM method offers a good opportunity for the realization of the Three-phase inverter control, it is better to use the unipolar PWM method with single carrier wave compared to two reference waves. In such case the motor harmonic losses will be considerably lower.The necessary calculations for generation of unipolar pulse width modulation strategies have presented in detail. The unipolar SPWM voltage switching scheme is selected in this paper because this method offers the advantages of effectively doubling the switching frequency of the inverter voltage. The cascaded multi level inverter fed induction motor is simulated and compared the total harmonic distroction for all level (five-level, seven-level, nine-level and elevel-level)of the inverter. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Multilevel inverters are emerging as the new breed of power converter options for high power applications. They typically synthesis the staircase voltage waveform (from several dc sources) which reduced harmonic content. This paper presents a simple selective harmonic elimination (SHE) modulation for single-phase cascaded H-bridge (CHB) multilevel inverter. The optimum switching angle of the transcendental equations describing the fundamental and harmonic components is solved by means of the Newton-Raphson (NR) method. The proposed SHE scheme is performed through simulation using MATLAB/Simulink. This simulation results are then verified through experiment using Altera DE0-Nano field-programmable gate array (FPGA). The proposed SHE is efficient in eliminating the lowest-order harmonics and producing a higher quality output waveform with a better harmonic profile.
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09_chapter4SPACEVECTORPULSEWIDTHMODULATION.pdf
1. 61
CHAPTER 4
SPACE VECTOR PULSE WIDTH MODULATION
4.1 INTRODUCTION
Multilevel inverters generate sinusoidal voltages from discrete
voltage levels, and pulse width modulation (PWM) strategies accomplish this
task of generating sinusoids of variable voltage and frequency. Modulation
methods for Hybrid Multilevel Inverter can be classified according to the
switching frequency methods. Many different PWM methods have been
developed to achieve the following: Wide linear modulation range, less
switching loss, reduced Total Harmonic Distortion (THD) in the spectrum of
switching waveform: and easy implementation and less computation time.
The most widely used techniques for implementing the pulse with modulation
(PWM) strategy for multilevel inverters are Sinusoidal PWM (SPWM) and
space vector PWM (SPWM). The SVPWM is considered as a better technique
of PWM implementation as it has advantages over SPWM in terms of good
utilization of dc bus voltage, reduced switching frequency and low current
ripple is presented in Beig et al (2007), Gupta and Khambadkone (2007), and
Franquelo et al (2006).
SVPWM is considered a better technique of PWM implementation,
as it provides the following advantages,
(i) Better fundamental output voltage.
(ii) Useful in improving harmonic performance and reducing
THD.
2. 62
(iii) Extreme simplicity and its easy and direct hardware
implementation in a Digital Signal Processor (DSP).
(iv) SVPWM can be efficiently executed in a few microseconds,
achieving similar results compared with other PWM methods.
In this chapter, a space vector is defined in a two-dimensional (2-D)
plane and a SVM is performed in the 2-D plane. Furthermore, a three-
dimensional (3-D) space vector has been defined in this chapter for cascaded
H-bridge multilevel inverter. All the existing space vector modulation
schemes are implemented in a two-dimensional, and are therefore unable to
deal with the zero-sequence component caused by unbalanced load.
Complexity and computational cost of traditional SVPWM technique increase
with the number of levels of the inverter as most of the space vector
modulation algorithms proposed in the literature involve trigonometric
function calculations or look-up tables. Previous works on three-dimensional
space vector modulation algorithms have been presented in Prats et al (2003)
and Oscar Lopez et al (2008) for diode-clamped inverter. However, unequal
dc sources cannot be applied to diode-clamped inverter. Meanwhile, the first
3-D space vector modulation for cascaded H-bridge inverter is presented in
Karthikeyan and Chenthur Pandian (2011), which is capable of dealing with
zero-sequence component caused by unbalanced load.
The three-dimensional space vector modulation schemes are
supersets of, and thus are compatible with, conventional two-dimensional
space vector modulation schemes. A new optimized 3-D SVPWM (3-D
OSVPWM) technique was proposed by Karthikeyan and Chenthur Pandian
(2011), which is similar to already existing 3-D SVPWM presented in,
following a similar notation. The proposed SVPWM technique calculate the
nearest switching vectors sequence to the reference vector and the on-state
durations of the respective switching state vectors by means of simple
3. 63
addition and comparison operation, without using trigonometric function
calculations, look-up tables or coordinate system transformations. Such very
low complexity and computational cost make them very suitable for
implementation in low cost devices. It is important to notice that these 3-D
OSVPWM techniques can be applied with balanced and unbalanced systems.
Implementation of the 2-D SVPWM and 3-D OSVPWM techniques is carried
out. Both SVPWM algorithms are implemented into a Field Programmable
Gate Arrays (FPGA) from Xilinx Foundation. Matlab Simulink is used to
develop all simulation works. Finally, both algorithmic implementations have
been tested with a cascaded H-bridge multilevel inverter.
4.2 SVPWM FOR THREE-LEG VOLTAGE SOURCE
INVERTER
The topology of a three-leg voltage source inverter is shown in
Figure 4.1. Eight possible switching combinations are generated by the
switching network shown in Figure 4.1 Six out of these eight topologies
producing a nonzero output voltage are known as the non-zero switching
states and the remaining two topologies producing zero output voltage are
known as zero switching states.
Figure 4.1 Three-Phase Voltage Source Inverter
4. 64
4.2.1 Voltage Space Vectors
Space Vector Modulation (SVM) for three-leg VSI is based on the
representation of the three phase quantities as vectors in a two-dimensional
( , ) plane. Considering topology 1 of Figure 4.2, which is repeated in
Figure 4.3 a. The line voltages ab
V , bc
V and ca
V are given by
0
-
ab dc
bc
ca dc
V V
V
V V
(4.1)
This can be represented in the ( , ) plane as shown in Figure
4.3(b), where voltages ab
V , bc
V and ca
V are three line voltage vectors
displaced 1200
in space. The effective voltage vector generated by this
topology is represented as 1
V (pnn) in Figure 4.3.b. The switching network
shown in Figure 4.1 has a total of eight possible switching combinations.
Each switching combination is shown in Figure 4.2, and is
represented according to the phase leg connection, where ‘p’ denotes that
phase leg is connected to the positive rail of the DC link, and ‘n’ denotes that
phase leg is connected to the negative rail of the DC link. For example,
switching combination ‘pnn’ represents the condition where the phase A
output terminal a
V is connected to the positive DC rail, and phase B and C
output terminals b
V and c
V are connected to the negative DC rail.
5. 65
Figure 4.2 Eight Switching State Topologies of Three-Phase Inverter
Each switching combination results in a set of three phase voltages
at the AC terminal of the switching network. A reference vector 1
V can be
obtained by transforming the reference three-phase voltage into the
plane, as shown in Figure 4.3.b. A balanced three-phase sinusoidal waveform
is obtained when the reference vector is rotating in the plane.
6. 66
Proceeding on similar lines the six non-zero voltage vectors
1 6
V V can be shown to assume the positions shown in Figure 4.4. The tips
of these vectors form a regular hexagon (dotted line shown in Figure 4.4). The
area enclosed by two adjacent vectors, within the hexagon, is chosen as a
sector. Thus there are six sectors numbered 1 to 6 in Figure 4.4.
Figure 4.3.a. Topology V1 (100) Voltage Source Inverter
Figure 4.3.b. Topology Representation of , plane
7. 67
The output line voltages generated by this topology in Figure 4.5.a
are given by
0
0
0
ab
cb
ca
V
V
V
(4.2)
Figure 4.4 Non-Zero Voltage Vectors in the , Plane.
The output voltages are represented as vectors which have zero
magnitude and hence are referred to as zero-switching state vectors or zero
voltage vectors. The position at origin in the ( , )plane is as shown in Figure
4.5.b. A total of eight vectors are obtained by transforming the three-phase
voltages into the a b coordinate and the same are called switching state
vectors.
4.2.2 Space Vector Modulation
The desired three phase voltages at the output of the inverter could
be represented by an equivalent vector V rotating in the counter clock wise
direction as shown in Figure 4.6.a. The magnitude of this vector is related to
8. 68
the magnitude of the output voltage as shown in Figure 4.6.b and the time this
vector takes to complete one revolution is the same as the fundamental time
period of the output voltage.
Figure 4.5.a. Zero Output Voltage Topologies
Figure 4.5.b Representation of the zero voltage vectors in the , plane
When the desired line-to-line output voltage vector V is in sector 1
as shown in Figure 4.7., vector V could be synthesized by the pulse-width
modulation (PWM) of the two adjacent switching state vectors 1
V (pnn) and
2
V (ppn), the duty cycle of each being d1 and d2, respectively, and the zero
vector (V7 (nnn) / V8 (ppp) ) of duty cycle d0:
9. 69
Figure 4.6.a Output voltage vector in the , plane
Figure 4.6.b Output Line Voltage
1 2
1 2
je
g
d V d V V mV e (4.3)
1 2 0 1
d d d (4.4)
where, 0 m 0.850 is the modulation index. This would correspond to a
maximum line-to-line voltage of 1.0Vg, which is 15% more than conventional
sinusoidal PWM is presented in Van Der Broeck et al (1988).
10. 70
All SVPWM schemes and most of the other PWM algorithms, use
the Equations 4.3 and 4.4 for the output voltage synthesis. The modulation
algorithms that use non-adjacent switching state vectors have been shown to
produce higher THD and/or switching losses. But some of them, for e.g.
hysteresis modulation, can be very simple to implement and can provide
faster transient response. The duty cycles 1 2
,
d d and 0
d , are uniquely
determined from Figure 4.7, and the equations of 4.3 and 4.4, the only
difference between PWM schemes that use adjacent vectors is the choice of
the zero vector(s) and the sequence in which the vectors are applied within the
switching cycle.
Figure 4.7 Synthesis of the Required Output Voltage Vector in Sector 1
4.3 SPACE VECTOR MODULATION ALGORITHMS
4.3.1 Two-Dimensional Space Vector
For any balanced three-phase variable, a b c
V V V , where V be the
voltage vector, there is a relationship
0
a b c
V V V (4.5)
11. 71
The above equation suggests that the three variables could be
mapped into a vector V on the orthogonal plane, where
V V jV (4.6)
The transformation for this orthogonal co-ordinate mapping,
sometime called 3/2 transformation, is expressed as
2
,
T T
a b c
V V T V V V (4.7)
where T is the transformation matrix and is expressed as
1 1
1
2 2 2
0
3 3 3
2 2
T (4.8)
4.3.2 Three-Dimensional Space Vector
For any balanced three-phase inverter, an assumption is always
made that, 0
a b c
V V V , where V be the voltage vector. The three
variables in a-b-c coordinate abc
V can be mapped into a vector V on the
orthogonal plane. Since each variable maintains the equal phase
difference for each phase, zero–sequence current is automatically nullified as
the reference vectors will be on a plane. When the system becomes
unbalanced, there is no zero–sequence component or triple harmonics because
the reference vectors are on a plane. So the three-dimensional space vector
representation and mapping will be similar to that of 2-D one.
12. 72
4.3.3 Two-Dimensional SVPWM for Calculating Switching Angles
A two-dimensional scheme for an n-level 3
n cascaded
multilevel inverter is proposed. In the proposed method, a simple algorithm of
forming switching sequence is applied that leads to minimum change in
voltage. An effective hybrid multilevel inverter must ensure that the Total
Harmonic Distortion (THD) in the voltage output waveform is small enough.
An algorithm is proposed for the cascaded multilevel inverter with equal
voltage steps under the space vector modulation. The algorithm results in the
minimal THD of output voltage of the cascaded multilevel inverter with equal
voltage steps.
A new expression of THD is presented to simplify the derivation.
The output voltage of the hybrid multilevel inverter is 2 1
S with the
SVPWM modulation. 1 2 3
, , ...
p P p pn
E E E E indicates the voltage steps in positive
side and 1 2 3
, , ...
n n n nn
E E E E indicates the voltage steps in negative steps.
1 2 3
, , ... n are the switching angles that indicates the on and off instance of
switches inside the inverter are presented in Liang and Nwankpa (1999),
Sirisukprasert et al (2002) and Zhou and Wang (2002).
4.3.3.1 Mathematical formulation
The algorithm can be expressed from the basis waveform by
applying Fourier series analysis, the amplitude of any odd nth
harmonic can be
expressed as,
1
4
cos
n
n k k
k
V E n
n (4.9)
13. 73
where n is an odd harmonic and k is the kth
switching angle. The amplitude of
all even harmonics is zero. The modulation index m is defined as,
1
1
4 n
i
i
V
m
E
(4.10)
Vn is the total harmonic component and V1 is the fundamental
harmonic component.
The voltage THD is defined as
2
2
3,5,7,... 1
n
n
V
THD
V
(4.11)
Now, to find the problem and to implement an algorithm for the
following variable inputs of the inverter 1 2 3
, , ... n
V V V V Modulation index term
m. Output of the algorithm 1 2 3
, , ... n such that THD is minimum. The input
voltages 1 2 3
, , ... n
V V V V are from dc sources.
The input m is determined by a controller in multilevel inverter.
The pulse angles 1 2 3
, , ... n are used by the inverter to control the switches.
It is important to note that minimizing voltage THD is desirable in some
applications. In some high power applications one desires to limit each order
harmonic to certain maximum allowed values. For the three phase system, the
triple order harmonic can be cancelled without help of modulation techniques,
yet it is desired to minimize THD for certain applications is presented in Beig
et al (2004), Naik and Udaya (2005) and Khajehoddin et al (2007).
From modulation index m, determine the value of by evaluating
2
1
1
n
k k
k
m e (4.12)
14. 74
where,
1
k
k n
l
i
E
e
E
(4.13)
1
1
/2
/ 2
nk
i k
i
k n
i n
i
E E
E E
(4.14)
The switching angles are determined by,
sin
k k (4.15)
The output voltages of the inverter is,
2
1 k k k k k
k
V E V V V V
(4.16)
where V is unit function. By Fourier series expansion,
1,3,5,...
sin
n
n
V V n
where,
1 1
1,3,5,..
4
cos
n n
V E n
n (4.17)
Modulation index m for the basic output voltage
1 1 1
1
cos
4 4 n
m V E n (4.18)
The THD is expressed as
2
2
3,5,7,... 1
THD n
n
V
V
(4.19)
15. 75
4.3.3.2 General structure of the algorithm
The control processing unit calculates the basic parameters to apply
a switching state. The input data to the control processing unit is the reference
space vector. During various iterations, the unit determines the sector number,
triangle number of the subhexagon. The sector number and triangle number
identify the correct switching sequence. The flowchart is given for an n-level
inverter and can be used for any n-levels without change.
The input supply is the amplitude of the voltage steps and
modulation index m, the initial value of o . The flow diagram of the proposed
algorithm to find minimum THD is shown in Figure 4.8. The modulation
index mc is calculated for various iterations. The difference between two
modulation index terms is calculated.
Figure 4.8 Flowchart of the Algorithm
16. 76
c
m m (4.20)
where,
– Reference value increases (or) decreases the pulse generation in
the pulse generator.
If the difference between the two modulation index terms is less
than reference value , the proposed algorithm outputs the optimal switching
angles. The iteration method is used to solve and find minimization of the
voltage THD.
4.3.3.3 Principles of the 2-D SVPWM technique
The SVPWM technique can be easily extended to all multilevel
inverters by Rodriguez et al (2002). This section explains the 2-D technique
for the generation of SVPWM for a five-level inverter. By using the space-
vector diagram, the basic principles of the SVPWM method can be easily
explained. Figure 4.9 shows the space vector diagram of a five level inverter.
The SVPWM implementation involves two phases: i) Selecting the switching
vector, and ii) Determining the center of the subhexagon.
A. Selection of the Switching Vector
In the 2-D method, the small triangles formed by the adjacent
voltage space vectors are called sectors. Such six sectors around a space
vector forms a hexagon called subhexagon. The space vector modulation
diagram of a multilevel inverter can be viewed composed of a number of
subhexagons. Sector identification is done by determining the triangle that
encloses the tip of the reference space vector.
17. 77
Figure 4.9 Space Vector Diagram for a Five Level Inverter
Numerous publications on two-dimensional space vector
modulation strategies are developed and applied to multilevel inverters with
equal dc sources. Previous works from authors on 2-D SVPWM algorithms
presented in Aneesh Mohamed et al (2009) and McGrath et al (2003) shows
that the reference voltage vector is identified from a single sub hexagon. In
the proposed 2-D SVPWM technique, the 2-D algorithm chooses two
subhexagons randomly. From the two chosen subhexagons, the 2-D
algorithm compares and selects the subhexagon that contains the nearest
reference vector.
The selected subhexagon that contains the tip of the reference space
vector is mapped to the inner subhexagon by subtracting the vector located at
the center of the subhexagon, from which switching sequence generations are
carried out. This comparison process helps in determining the appropriate
subhexagon having the nearest reference vector as well as the sector to which
the reference vector is pointing to is determined for calculating the switching
states and the switching times.
18. 78
After identification of the sector in which the tip of the reference
vector is located, four adjacent triangles having four nearest state vectors (two
redundant vectors) to the reference vector are identified. The adjacent
switching vectors and its corresponding switching sequence for the multilevel
inverter are determined. Then the algorithm determines the time duration of
each switching sequence. Once the duration of the switching sequence is
calculated, then its corresponding switching angles are determined. The 2-D
algorithm proposed reduces the total harmonic distortion of output voltage of
the inverter as the exact voltage vector is chosen for switching sequence
generation. The proposed modulation is computational very efficient and cost
effective which can be applied to multilevel inverters with any number of
levels.
The shaded region in Figure 4.10 shows two subhexagons. They are
represented as “subhexagon I” having vector 000 as the centre and
“subhexagon II” having the vector 032 as the centre. Another “subhexagon
III” is also considered, having a vector 330 as the centre. The inner
subhexagon can be viewed as a space vector diagram of a two-level inverter
whose inverter voltage vectors switch between the lower most levels.
Subhexagon II can be also viewed as a space vector diagram of a two level
inverter whose voltage vectors involve higher levels.
The shifting of subhexagon in the space vector diagram of a
multilevel inverter to the zero vector 000 simplifies the switching time
calculations associated with multilevel inverters. The shifting of subhexagon
II in the space vector diagram of a multilevel inverter toward the zero vector
000 involves the mapping of the sectors of subhexagon II to the sectors of the
inner subhexagon. This is done by subtracting the vector at the centre of the
subhexagon II from its other vector.
19. 79
Figure 4.10 Mapping of Reference Space Vector for Switching Vector
Generation
In a reverse approach of mapping, the inner subhexagon can be
mapped to subhexagon II by adding the voltage space vector at the centre of
subhexagon II to the vector of the inner subhexagon. Consider the voltage
vectors 000, 001, 101 and 111 associated with sector 5 of the inner
subhexagon and the voltage space vector 032 which is the vector at the centre
of subhexagon II. Adding the voltage space vector 032 to the voltage space
vector associated with sector 5 of the inner subhexagon gives the vectors 032
(001+033), 022(101+022) and 421(100+021), which are the vectors
associated with sector 5 of subhexagon.
Also, the voltage space vector associated with any subhexagon can
be generated by adding the vector at the centre of the particular subhexagon to
the voltage space vector of the corresponding sectors in the inner subhexagon.
The mapping of the inner subhexagon to any other outer subhexagon called as
reverse mapping is used to generate the vectors associated with any sector in
the space vector diagram of the multilevel inverter is presented in Aneesh
Mohamed et al (2009).
20. 80
B. Determining the Centre of the subhexagon
The space vector diagram of a five-level inverter, shown in Figure
4.11 can be viewed as the form of five levels with four layers. These levels
are represented as Level 1 to 5. The instantaneous reference space vector
lying in layer4 (P=4) and within the S1 region forms a triangular shape.
Depending upon the layer of operation of the instantaneous
reference space vector, all vectors for the center of the subhexagon are
generated, and the vector which is closest to the reference space vector is
taken as the center of the subhexagon. Figure 4.11 also shows the six 60o
regions 1 2 3 4 5
, , , ,
S S S S S and 6
S .
Figure 4.11 Levels in the Space Vector Diagram of a Five-Level Inverter
The subhexagon associated with the instantaneous reference space
vector can be considered as centered on the inner side of layer 4. The
instantaneous reference space vector can be resolved in to the axes ,
x y
V V and
z
V using the following where ,
a b
V V and c
V are the instantaneous amplitude of
the three reference phase voltages
21. 81
3
2
3
2
3
2
x a c
y b a
z c b
V V V
V V V
V V V
(4.21)
The axis lying in the 60 region which contains the instantaneous
reference space vector will have maximum magnitude among the values.
4.3.4 3-D Space Vector Pulse Width Modulation
A simple three-dimensional (3-D) space vector algorithm of
multilevel inverters for mitigating harmonic content in three phase systems
was proposed by Prats et al (2003), and Franquelo et al (2006). The three-
dimensional SVPWM (3-D SVPWM) scheme computes the switching state
vectors and the nearest switching sequence. The 3-D modulation technique
allows directly compensating harmonics in three phase systems and
optimizing the switching sequence minimizing the number of switchings.
Most of the SVM algorithms found in the literature for multilevel
inverters use a representation of voltage vectors in coordinates, instead
of using abc coordinates The representation offers an interesting
information about the zero-sequence component of both currents and voltages
(proportional to the gamma coordinate), however the change of reference
frame have to be carried out, implies complex calculations. In addition, the
three-dimensional (3-D) representation of the switching vectors, in is
difficult to understand. Most methods based on representation need to
determine the “sextant” in which the desired voltage vector is included, which
leads to many complicated operations, including rotations, complex
comparisons etc.
22. 82
Using coordinates, the possible tetrahedrons that compose the
state vectors space have different shapes and volumes. It is not easy to
develop computationally efficient modulation algorithms to find out the
tetrahedron where the reference vector is pointing to. However, Zhang et al
(2002) has developed 3-D SVPWM algorithms using coordinates for
three-leg four-wire (3L4W) topologies. But these algorithms are complex and
their computational cost is very high.
This is the fundamental drawback of this type of 3-D SVPWM
algorithms. Therefore, it is necessary to change the way of representation for
the multilevel state vectors space. This is the reason because abc coordinates
are used by other authors doing modulation algorithms very simple and more
easily implemented. In order to reduce the 3-D SVPWM computational cost,
multilevel inverters state vectors space can be represented using
abc coordinates instead of coordinates.
The 3-D SVPWM techniques carry out a search of the four nearest
state vectors to determine the switching sequence. Using abc coordinates, the
3-D SVPWM algorithm control complexity and the computational load is
lower than using coordinates. Using abc coordinates, the control region
is a cube or a prism for three-legged inverter. The 3-D SVPWM technique
presented in need to synthesis 3-D vector space and identifies the subcube
where the reference vector is located. Once this subcube is determined, it is
divided into six tetrahedrons, and the 3-D SVPWM has to calculate the
tetrahedron where the reference vector is pointing to.
Finally, the switching sequence and the corresponding duty cycles
are determined. This technique can be used as the modulation algorithm in all
applications needing a 3-D vector control such as an active filter, where the
conventional 2-D SVM cannot be used. The 3-D space vector modulation
23. 83
schemes are supersets of, and as a result 3-D SVPWM is compatible with
conventional two dimensional space vector modulation schemes.
4.3.4.1 Synthesis of Reference Vector
The 3-D space vector modulation is to synthesize the reference
vector ref
V using the switching vectors in the abc coordinate. It is similar to
that of 2-D space vector modulation (describe in section 4.2). Synthesis of the
reference vector in abc coordinates needs to take the following steps: (1)
selection of switching vectors and (2) sequencing the switching vectors.
4.3.4.1.1. Selection of Switching Vectors
For the 2-D space vector modulation it is easy to identify the
adjacent switching vectors. For 3-D space vector, it takes the following steps
to identify the adjacent vectors.
1. The 3-D SVPWM techniques carry out a search of the four
nearest state vectors to determine the switching sequence.
Using abc coordinates, the control region is a cube or a prism
for a three-legged inverter. Then the control region is divided
into several sub-cubes. The four vectors nearest to the
reference vector must be identified. The 3-D SVPWM
algorithm easily calculates the four state vectors which
generate the reference vector. The multilevel control region is
a cube, which is divided into several sub-cubes and the first
step of the modulation algorithm is to find the sub-cube where
the reference vector is pointing to. The cubes in three-
dimensional space are formed by a certain number of sub-
cubes depending on the number of the levels of the inverter.
Only one subcube for two-level inverters, eight sub-cubes for
24. 84
three-level inverters, twenty-seven sub-cubes for four-level
inverters. In general, 3
( 1)
n sub-cubes into each cube,
where n is the number of levels of the multilevel inverter.
2. Once this subcube is determined, it is divided into six
tetrahedrons. Thus, the reference vector will be pointing to a
volume which is a tetrahedron. Within each sub-cube, six
tetrahedrons can be identified. The adjacent switching vectors
are defined by the tetrahedrons. Therefore, it is necessary to
define the tetrahedron where the reference vector is pointing
to. This tetrahedron is easily found using comparisons with
three 450
planes into the 3-D space, which define the six
tetrahedrons inside the subcube. The three planes define the
six tetrahedrons. Notice that only a maximum of three
comparisons are needed regardless the inverter number of levels.
3. Once abc coordinates are known, the algorithm calculates the
four state vectors corresponding to the four vertices of the
tetrahedron into the selected sub-cube, which form the
switching sequence. These vectors will generate the reference
vector. Configurations of the 3-D space with different
numbers of tetrahedrons in the cube have been studied.
However, the minimum number of comparisons is obtained
using the six tetrahedrons.
4.3.4.1.2. Sequencing of the Switching Vectors
The SVPWM algorithm calculates the four state vectors into the 3-
D space and the corresponding duty-cycles and a maximum of three
comparisons for calculating the suitable tetrahedron. The computational load
is always the same and it is independent of the number of levels. In addition,
25. 85
the algorithm provides the switching sequence that minimizes the total
harmonic distortion.
4.3.4.2 Calculation of the duty cycles
Once the state vectors which generate each reference vector are
known, the corresponding duty-cycles are calculated. The numeric evaluation
of the duty cycles or on-state durations of the switching states are reduced to a
simple addition. The algorithm generates a matrix S with four state vectors
and the corresponding switching times i
t . Where , ,
i i i
a b c
S S S with 1,..,4
i are
the coordinates of each state vector and i
d is the corresponding duty cycle
1 1 1
1
2 2 2
2
3 3 3
3
4 4 4 4
1,..,4
a b c
a b c
i i m
a b c
a b c
S S S d
S S S d
S t d T i
d
S S S
d
S S S
(4.22)
Where, m
T is the sample time.
The coordinates abc represent the different voltage levels between
each phase and the neutral. They take values between zero and2( 1)
n , where
n is the number of levels of the multilevel inverter. The duty cycles are only
functions of the reference vector components and the integer part of reference
vector coordinates. In addition, the optimized switching sequence is selected
in order to minimize the number of switching.
4.3.5 Optimized Three-Dimensional SVPWM for Balanced and
Unbalanced Systems
A simple and generalized 3-D OSVPWM (optimized 3-D space
vector modulation) is presented for multilevel inverters, which can be used for
26. 86
any number of levels of multilevel inverter. The 3-D OSVPWM scheme
proposed is similar to the existing 3-D SVPWM presented in Prats et al
(2003), and Leon et al (2009), following the similar notation. Since the
proposed scheme is similar to the already existing 3-D SVPWM scheme, once
the duty cycle, which is the function of reference vector components is
calculated. Then it translates the generating vectors into switching pulses. In
general, the SVPWM techniques are used to generate an average voltage
vector equal to the reference voltage vector.
In two-dimensional SVPWM (2-D SVPWM), the space vectors are
contained in a plane when the system is balanced without triple harmonics. A
perfect balance of the dc voltages of a multilevel inverter cannot be achieved
in all loading conditions. Load imbalances or transient loads have a
significant impact on the multilevel inverter dc voltage ripple. In this case, 2-
D SVPWM modulation techniques are not prepared for this unbalance
because they do not take it into account to carry out the modulation process.
As a result, errors appear in the output modulated voltages because they do
not match to the desired output voltages when they are brought to average
over a period of switching.
This fact leads to an increase of the harmonic distortion of the
output voltages and currents of the multilevel inverters. This problem has
been previously addressed by Blaabjerg et al (1999) and Enjeti and Shireen
(1992), avoiding the influence of the dc-link voltage ripple on the output
signals for two-level inverters. Previous works from Parts et al (2003) and
Leon et al (2009) focused on 3-D SVPWM algorithm shows the reference
vectors are not on a plane, if the system is unbalanced for multilevel inverter.
A new three-dimensional space vector modulation scheme named as 3-D
OSVPWM is presented. The simple and generalized 3-D OSVPWM scheme
proposed for multilevel inverter is an improved version of the previous 3-D
27. 87
SVPWM technique because the proposed technique can be used for any
number of levels of the multilevel inverter. The 3-D OSVPWM technique
presented, takes into account the actual unbalance of the multilevel inverter to
carry out the necessary calculations, avoiding errors in the modulation
process. The proposed 3-D OSVPWM algorithm maintains 1200
phase for
each phase to compute switching state vectors and the nearest switching
sequence. The reference vectors are on a plane with 1200
phase shift for each
phase.
Each switching state of the inverter is represented by a switching
voltage vector. The method is to choose the vectors that, applied during a
certain time over the switching period, produce a voltage vector equal to the
reference or desired voltage vector. The proposed 3-D OSVPWM algorithm
permits the on-line selection of the nearest space vectors sequence for
generating the reference voltage vector. The 3-D OSVPWM algorithm readily
computes the nearest switching vectors sequence to the reference vector and
calculates the on-state durations of the respective switching state vectors.
Since each vector maintains an equal phase difference for each phase, the
flow of zero–sequence current is automatically nullified as there will be no
component in the voltage vector and the reference vectors will be contained
on a plane.
When the system becomes unbalanced, there is no zero–sequence
component of both current and voltage (proportional to the coordinate) or
triple harmonics because the reference vectors are on an equal 1200
phase shift
plane. So the 3-D space vector representation and mapping will be similar to
that of 2-D one. This technique can be used as modulation algorithm in all
applications needing a 3-D control vector such as active filters, where the
conventional two dimensional space vector modulations cannot be used. The
unequal dc voltage does not affect the THD of the output waveform, leading
28. 88
to an economical cost and reduction of the harmonic content. The 3-D
OSVPWM can be applied to multilevel inverters with any number of levels.
Using the proposed 3-D OSVPWM, balanced and unbalanced systems can be
modulated with balanced or unbalanced dc voltages.
4.3.5.1 Determination of 3-D Control Region
In the 3-D SVPWM technique explained in Section 4.3.4., the dc
voltages of a multilevel inverter are not balanced. Therefore, the existing 3-D
SVPWM technique cannot be used because the 3-D control region changes
and it is not formed by regular cubes. The 3-D control region of a multilevel
inverter changes because the distinct locations of the switching state vectors
move due unbalance in the voltage. Three different dc voltages 1 2
,
dc dc
V V and
3
dc
V have to be considered for a three-bridge fourteen-level cascaded
multilevel inverter. The various possible Vphase-0 voltages of the multilevel
inverter are 1 1 2
0, ,
dc dc dc
V V V and 1 2 3
dc dc dc
V V V . The phase states can be
represented using generalized dc voltages 1 2
,
dc dc
V V and 3
dc
V .
In general, the 3-D control region formed will be cube with
size 1 2 3
dc dc dc
V V V , which forms several rectangular sub cubes with different
sizes, depending on the voltages of different dc sources. The 3-D control
region of a fourteen-level power inverter having 1 2 3
dc dc dc
V V V is
represented in Figure 4.12. The i values are the size of the sub cubes that
form the 3-D control region, are as follows:
dctotal dc1 dc2 dcn
V =V +V +.....+V
(4.23)
di
i
dctotal
V
=
V (4.24)
29. 89
The actual output voltages of the multilevel inverter are determined
from the vector Vo. The elements of the vector Vo are in increasing order from
zero to the positive value. In the N-level inverter, the vector is represented as
o dc1 dc1 dc2 dc1 dcn-1
V= 0,V ,V +V ,....,V +...+V
(4.25)
Figure 4.12 Three-Dimensional Control Region of a Five –Level Inverter
with Voltage Unbalance in the DC Link Vdc1<Vdc2<Vdc3
Normalizing the vector Vo with respect to the total dc voltage
generating vector Von
30. 90
o
o n
d cto tal
V
V =
V (4.26)
dc1 dc1 dc2 dc1 dcn-1
on
dctotal dctotal dctotal
V V +V V +...+V
V = 0, , ,....,
V V V
(4.27)
1 1 2 1 N -1
= 0, ,....., +...+
(4.28)
1 1 2
= 0 , , . .. . ., 1
(4.29)
4.3.5.2 Reference vector normalization
The reference vector calculated is defined as , ,
refn a b c
V V V V where
j
V is the voltage of phase j with respect to point zero. The reference vector Vref
is normalized using the total dc voltage of the multilevel inverter. The
normalized reference voltages ,
a b
V V and c
V take values between zero and one.
The reference vector in the nth
component is represented as
a c
b
a c
refn b
dctotal dctotal dctotal
V
V V
V ={v , v , v }= , ,
V V V (4.30)
4.3.5.3 Algorithm for generating switching angles
1) Read the instantaneous magnitudes of phase voltages.
2) Determine the coordinates of the instantaneous space vector.
3) The coordinates of the reference space vector is normalized
through division by the normalization constant VDC / n – 1.
4) Determine the tetrahedron region enclosing the normalized
cube for an n-level inverter.
31. 91
5) Calculate the modulation index m, which is determined by a
number of iterations repeatedly applied to various
tetrahedrons.
6) Identify the tetrahedron region having m, calculated in step (5)
7) Determine the centroid of each of the four triangles. Also
determine the tetrahedron with centroid closest to the 16
triangles.
8) Each triangle gives three vectors and switching states.
9) Determine the nearest switching angle and the resultant m
from step (5), go to next step, else go to step (7).
10) The tetrahedron finally determined represents the tetrahedron
enclosing the space vector.
11) Continue the process of identifying the voltage space vector in
different tetrahedron of the cube.
12) Select the zero vector from the vectors located at the vertices
of the identified subcube.
4.3.5.4 Determination of the tetrahedron
Several iterations are carried out over each component to find out
the nearest centroid of the tetrahedral region enclosing the normalized
subcube. Several iterations are carried out in phase a, to find where a
v is
located inside Von vector, comparing with each element. Finally, the lower
and upper closer elements in vector Von of the range where va is located can
be determined. For example, for the four level stages, it is as follows
dc1 dc1 dc2 dc1 dc2 dc3
on
dc1 dc2 dc3 dc1 dc2 dc3 dc1 dc2 dc3
V V +V V +V +V
V = 0, , ,
V +V +V V +V +V V +V +V (4.31)
32. 92
1 1 2 1 2 3
= 0, , ,
(4.32)
1 2
= 0, , , 1
3 3 (4.33)
If 1 < a
v < 1, the factor a
v is 1 and the factor a
Vs is one. For each
phase of the reference vector this process is repeated to calculate the vector
, ,
abc a b c
V V V V which is the nearest centroid of the triangular region where
the reference vector , ,
a b c
V V V is located. Also, the
vector , ,
abc a b c
Vs Vs Vs Vs is determined. Vectors , ,
a b c and
, ,
a b c
V can be calculated.
a b c a a b b c c
={ , , }={Vs -V ,Vs -V ,Vs -V} (4.34)
a b c a a b b c c
V={ , , }={v -V , v -V , v -V} (4.35)
The switching sequences and the duty cycles calculations are
summarized in Table 4.1 and the parameters ,
a b and c in the table are
defined as
a b c
a b a
a b c
= , = , = (4.36)
33. 93
Figure 4.13 Division of Each Rectangular Subcube of the 3-D SVPWM
Control Region of a Multilevel Inverter with Unbalanced
DC Voltages
The proposed modulation technique finds out the four nearest state
vectors to form the switching sequences to generate the reference voltage. The
switching sequence consisting of four nearest state vectors have four
tetrahedron in each sub cube and six different cases is shown in Figure 4.13.
Determine the centroid of each of the four triangles; each triangle gives three
vectors and a switching state.
34. 94
Table 4.1 Switching sequence and Duty Cycles Determined by the 3-D
SVPWM Technique
S. No Cube Cases
State Vector
Sequences
Duty Cycles
1 Case 1
210, 310, 321
210, 310, 320
210, 321, 320
321, 310, 320
D = 1-µa
D = µa - µc
D = µc - µb
D = µb
2 Case 2
210, 212, 220
210, 212, 321
210, 220, 321
212, 321, 220
D = 1-µc
D = µc - µa
D = µa - µb
D = µb
3 Case 3
210, 311, 310
210, 311, 321
210, 310, 321
310, 311, 321
D = 1-µc
D = µc - µb
D = µb - µa
D = µa
4 Case 4
210, 321, 220
210, 320, 220
210, 321, 320
220, 320, 321
D = 1-µb
D = µb - µa
D = µc - µa
D = µa
5 Case 5
210, 211, 212
210, 321, 212
210, 321, 211
212, 321, 211
D = 1-µb
D = µb - µa
D = µa - µc
D = µc
6 Case 6
210, 311, 321
210, 311, 211
210, 211, 321
211, 311, 321
D = 1-µa
D = µa - µc
D = µb - µc
D = µc
35. 95
4.4 2-D SVPWM ALGORITHM COMPONENTS
Figure 4.14 shows the block diagram designed for the 2-D
algorithm, which included the following components: frequency, 2 ,
dq 2-
DSVM, 2 ,
abc PWM3 and dead time.
4.4.1 Component Frequency-
The user can select one of four modulator switching frequencies
available by means of the input signal s
f . The selected frequency defines the
needed values for the switching period T and the dead time Td. A dead time of
5% of the switching period was used.
4.4.2 Component dq to
This element carries out the following to
dq transformation of
the reference vector ,
d q
r r
v v from the rotational frame to the stationary
frame.
-1 cos -sin
3
2 sin cos
0
d
r r
q
r r
v v
v v
(4.37)
4.4.2.1 Component 2-DSVM
This component is the core of the system. It determines the nearest
three vector 1 1 2 2
, , ,
T T
s s s s
v v v v and 3 3
,
T
s s
v v to the reference vector
in the ,
T
r r
v v in the frame and calculates their corresponding
switching times which is presented in Celanovic and Boroyevic (2001).
36. 96
4.4.2.2 Component to abc
This component transforms back three nearest vectors from to
the abcframe. This is achieved by evaluating the Equation 4.37. This
expression has multiple solutions. Therefore, the following algorithm was
developed to obtain a vector sequence that minimizes the number of
switchings. The twenty four triangular regions have been joined in the six
highlighted groups shown in Figure 4.15. The vector sequence starts with the
boxed vector of the group, and it is tailored with adjacent vectors.
The 1 1 1
, ,
T
a b c
s s s
v v v is the boxed vector and vector 2 2 2
, ,
T
a b c
s s s
v v v and
3 3 3
, ,
T
a b c
s s s
v v v are taken accordance with the arrow inside the region.
Figure 4.14 2-DSVPWM Algorithm
37. 97
Figure 4.15 Switching Vector Sequence Selection
The following components PWM3 generates a symmetrical
sequence that starts and ends with the same vector, therefore, there are no
additional switchings when the reference vector changes between triangular
regions that belong to the same group, but it only adds two extra switchings
when the reference changes to the next group. Hence, this vector selection
method minimize the number of switchings when the reference vector stays
inside a region as well as when it changes region.
4.4.2.3 Components PWM3
It arranges the three vectors of the sequence in the symmetrical way
into the switching period. The sequence generated is the following.
38. 98
1
1 1 1
2
2 2 2
3
3 3 3
1 1 1 1
1 1 1
3 3 3
, , - - - - - -
4
, , - - - - - -
2
, , - - - - - -
2
, , - - - - - -
2
, ,
T
a b c
s s s
T
a b c
s s s
T
a b c
s s s
T
a b c
s s s
T
a b c
s s s
T
v v v
T
v v v
T
V V V
T
v v v
V V V 3
2
2 2 2
1
1 1 1
- - - - - -
2
, , - - - - - -
2
, , - - - - - -
4
T
a b c
s s s
T
a b c
s s s
T
T
v v v
T
v v v
(4.38)
After that, it generates the six PWM signals corresponding to each
complementary pair of switches.
4.4.2.4 Components dead-time
Finally, this circuit generates the trigger signal for each power
switch, introducing the proper dead time to give each Metal Oxide
Semiconductor Field Effect Transistor (MOSFET) enough time to switch off,
before its complementary one is switched on. This is done, as shown in Figure
4.17 by delaying the rising edges of the trigger signals by the time Td.
4.4.3 3D SVPWM Components
Figure 4.16 shows the block diagram designed for the 3-D
algorithm, which includes the following components: frequency, 2
dq abc, 3D
SVPWM, PWM4 and dead time.
39. 99
4.4.4 Component Frequency
This block is similar to the one used in the 2D SVPWM algorithm
for calculating the switching period T and the dead time Td.
4.4.5 Component dq to abc
This component implements the following 2
dq abcco-ordinate
transformation
1 0 0
cos -sin
1 3
- 0
sin cos
2 2
1 3
- - 0
2 2
a
r d
r
b
r q
r
c
r
v
v
v
v
V
(4.39)
4.4.5.1 Component 3DPWM
This component finds the four nearest switching vectors
1 1 1 2 2 2 3 3 3 4 4 4
, , , , , , , , , and , ,
T T T T
a b c a b c a b c a b c
s s s s s s s s s s s s
v v v v v v v v v v v v to
the reference vector and calculates their corresponding switching times, and
the resulting sequences minimizes of switches.
40. 100
Figure 4.16 3D SVPWM Algorithm
4.4.5.2 Components of PWM
This block is very similar to the PWM3 but working with four input
vectors instead of three. It arranges the vectors in a symmetrical way into the
switching time and generates the Six PWM signals corresponding to each
complementary pair of MOSFETs. The sequence generated is the following.
1
1 1 1
2
2 2 2
3
3 3 3
4 4 4 4
3
3 3 3
2 2 2
, , - - - - - -
2
, , - - - - - -
2
, , - - - - - -
2
, , - - - - - - -
, , - - - - - -
2
, , - - -
T
a b c
s s s
T
a b c
s s s
T
a b c
s s s
T
a b c
s s s
T
a b c
s s s
T
a b c
s s s
T
v v v
T
v v v
T
v v v
v v v T
T
v v v
v v v 2
1
1 1 1
- - -
2
, , - - - - - -
2
T
a b c
s s s
T
T
v v v
(4.40)
41. 101
4.4.5.3 Component dead time
This circuit generates the trigger signal for each power switch,
introducing the proper dead time to give each MOSFET enough time to
switch off, before its complementary one is switched on.
Figure 4.17 Dead Time Implementation
This is done, as shown in Figure 4.17 and to generate the twelve
trigger signals inserting the corresponding dead times.
4.5 COMPONENT IMPLEMENTATION
The hardware description of the components of the algorithms
shown in Figure 4.9 and 4.11 has been hand-coded in VHDL. An exception
was made with the components dq to anddqtoabc. These components
have been developed in the Simulink with the System Generator libraries
provided by Xilinx. The VHDL code that describes these components has
been automatically generated using the System Generator tool, in order to
produce a correct system implementation in a short design time.
4.5.1 Component Frequency
One of the four frequencies and dead time pairs can be selected by
means of the two-bit signal fs. Signals T and Td are integer numbers that
express the switching period and dead time in microseconds. Signal T is
twelve bits wide, which allows periods of upto 1023µs i.e., 977.5Hz. Td is a
42. 102
six bit signal, which allows defining a dead time upto 63µs. The modulator
switching period T and the corresponding dead time Td are selected by means
of a four-channel multiplexer, as shown in the Figure 4.18.
Figure 4.18 Component Frequency
4.5.2 Components dq to
The implementation of transformation from the rotating to the
stationary frames is given in Equation 4.37. Figure 4.19 shows the Simulink
models used to describe the components and to generate the corresponding
VHDL description files. Internal arithmetic operations are done with adequate
precision using fixed-point number representation and two’s complement
format. The fractional part of the final result was rounded to 8-bits in order to
calculate the switching times with adequate accuracy in the component 2-D
SVPWM. For an n-level inverter in the 2-D SVPWM algorithm, the integer
part of the result takes values from ( 1) ( 1)
n to n . Therefore 3 bit are
43. 103
necessary to represent the integer part. The output signals in the 2-D case are
11-bit wide.
Figure 4.19 Component of dq to
4.5.3 Components dqto abc
The component implements transformation Equation 4.39 from the
rotating to the stationary frames. Figure 4.20 shows the Simulink models used
to describe the components and to generate the corresponding VHDL
description files. Internal arithmetic operations are done with adequate
precision using fixed-point number representation and two’s complement
format. The fractional part of the final result was rounded to 8-bits in order to
calculate the switching times with adequate accuracy in the component 3-D
SVPWM. For an n-level inverter, in the 3-D SVPWM algorithm the integer
parts of the results take values in the range0 ( 1)
to n . Therefore, 2 bits are
necessary to represent the integer part. Consequently, the output signals in the
3-D case are 10 bit wide. The 3-D SVPWM can be used without any
modification for a CHB inverter of upto 5 levels. If the number of level
increases then more bits would be needed to represent these signals properly.
The sine and cosine operations have been implemented by means of a table
44. 104
stored in a memory. 256 points of the sinusoidal waveform have been stored
with 8-bits of resolution. In order to store the data a 256*8 memory is needed.
Therefore an external RAM was used to take advantage of the FPGA
hardware resources.
Figure 4.20 Component dqto abc
4.5.4 Component 2-D SVM
The 2-D SVPWM has been implemented strictly following the
algorithm descriptions given in Celanovic and Boroyevic (2001) by means of
simple arithmetic and comparison operations.
Figure 4.21 Flow Diagram of VHDL Description of the 2-D SVPWM
Component
45. 105
The nearest vector and switching times are calculated from the
integer and fractional part of the reference. The signals corresponding to the
vector component has been 3-bit in the 2-D algorithm and the unit switching
times are 8-bit wide.
The integer and fractional part of the references can be done by the
proper bit extraction from the fixed point number. Corrections have been done
in the case of negative numbers in the 2-D algorithm. Figure 4.21 show the
flow diagram of the VHDL description and the bit extraction operation.
4.5.5 Component 3D SVPWM
The 3-D SVPWM has been implemented strictly following the
algorithm descriptions given in Prats et al (2003) by means of simple
arithmetic and comparison operations.
Figure 4.22 Flow Diagram of VHDL Description of the 3D SVPWM
Component
46. 106
The nearest vector and switching times are calculated from the
integer and fractional part of the reference. The signals corresponding to the
vector component has 2-bit in the 3-D algorithm and the unit switching times
are 8-bit wide. Figure 4.22 shows the flow diagram of the VHDL description
and the bit extraction operation.
4.5.6 Component toabc
Figure 4.23 Flow Diagram of VHDL Description of the to
abccomponent
Figure 4.23 shows the flow diagram utilized for the VHDL
description of this block in accordance with Figure 4.15. As shown
previously, the output signals of the component have 2-bits which are enough
to represent the three levels of inverter.
4.5.7 Components PWM3 and PWM4
Figure 4.19 shows the PWM4 implementation. The implementation
of component PWM3 is very similar. But, in this case unit time T4 is not
needed and the four vector is internally generated as
47. 107
4 4 4 1 1 1
, , 1, 1, 1
T T
a b c a b c
s s s s s s
v v v v v v (4.41)
The block sequence compares the switching time corresponding to
each vector with the value of a counter to generate the vector index
corresponding to each time interval. The 50 MHz master clock of the S3 was
divided using the digital clock manager of the FPGA in order to obtain a 10
KHz clock. That clock allows generating the PWM signals with a time
precision of 0.1 µs. Due to the fact that vector times are 8-bit wide, then the
maximum switching frequency available in the system is 100MHz without the
frequency division of the master clock, the maximum. Switching frequency
could be increased 5 times, upto 125 KHz. The output of the multiplexer is the
space vector that must be generated by the inverter at a particular time.
Figure 4.24 Component Diagram of the PWM4
The level of each phase in the corresponding trigger signals is
translated by the component Level to trigger signal. This translation depends
on the inverter topology, therefore this block must be redesigned if an inverter
48. 108
different from the CHB is used. It is not necessary to modify the rest of
components because both modulation algorithms do not depend on the
topology.
4.5.8 Component Dead-Time
Figure 4.25 Component of Dead Time Description
This block generates the inverse of trigger signals adding the
corresponding dead time. It was implemented using an edge detector together
with a counter working as a timer in order to delay rising edges of the trigger
signal as show in Figure 4.25.
4.6 RESOURCES
All circuits were combined in a top file according to Figure 4.14.
and 4.16. Finally, the whole system is synthesized and implemented in the
XS200E FPGA through the use of the Xilinx foundation ISE tools, which are
specific for these tasks. Both algorithm implementations use only one ERAM,
to generate the sine and cosine functions, but the 2-D algorithm uses half flip-
flops and two hardware multipliers less than 3-D algorithm. This is because
the first algorithm works with only three 2-D vectors, instead of four 3-D
vectors of the second algorithm. Although the 2-D algorithm works with
fewer vectors represented with fewer bits, both implementations use similar
number of logic blocks and look-up tables (LUTs). This is due to the need for
49. 109
an extra task to select the generating vectors in the 2-D algorithm.
Consequently, the 3-D algorithm is easier to implement but uses more logical
resources of the FPGA.
In order to extend the proposed implementation to a higher level
inverter, many considerations have to be taken into account. The
implementation of the component frequency is independent of the inverter
topology; therefore it can be used without any modification. Components
dq to , dq to abc , 2-D SVPWM and 3-D SVPWM only need slight
modifications in order to adapt the bit number of signals to the number of
level of the inverter. Resources used by those components increases with the
increase in the number of levels. In fact, they could be directly used for a five
level topology. Components PWM3, PWM4 and dead-time have to be
extended in order to generate additional PWM signals for extra MOSFET’s of
the inverter. Therefore, resources used by the additional components increases
almost linearly with number of levels of the CHB inverter. The component
to abcwas designed for a five-level inverter.
4.7 COMPARISON OF SVPWM AND PWM
The SVPWM is considered a better technique of PWM implementation
as it has some advantages over SPWM in terms of good utilization of dc-bus
voltage, reduced switching frequency and low current ripple. SVPWM
provides the following advantages: i) better fundamental output voltage; ii)
useful in improving harmonic performance and reducing THD; and iii) easier
hardware implementation in digital signal processor. SVPWM can be
efficiently executed in a few micro seconds, achieving similar results
compared with other PWM methods.
50. 110
The carrier-based PWM methods were developed first and were
widely used in most applications. One of the earliest modulation signals for
carrier-based PWM is sinusoidal PWM (SPWM). The SPWM technique is
based on the comparison of a carrier signal and a pure sinusoidal modulation
signal. The SVPWM technique calculates and computes the duty cycles but
SPWM technique derives through comparison. The utilization rate of the DC
voltage for traditional sinusoidal PWM is only 78.5% of the DC bus voltage,
which is far less than that of the six-step wave (100%). This technique can be
used in single-phase and three-phase inverters. The SVPWM technique can
increase the fundamental component by up to 27.39% that of SPWM. The
fundamental voltage can be increased up to a square wave mode where a
modulation index of unity is reached. The SVPWM is significantly better than
SPWM by approximately 15.5%.
4.8 SUMMARY
In this chapter, two very efficient SVPWM techniques were
discussed. The basic idea about SVPWM for three-legged voltage source
inverter was discussed in detail. It is illustrated how the voltage space vectors
are defined in a two-dimensional (2-D) plane and three-dimensional (3-D)
plane for a cascaded H-bridge multilevel inverter. Furthermore, two-
dimensional (2-D) and three-dimensional (3-D) space vector modulation
algorithms are explained. Mathematical formulation for calculating switching
angles and switching sequence was determined and the Fourier series theory
was used to derive the harmonic equations corresponding to the multilevel
switching scheme.
The basic idea about the existing three-dimensional space vector
modulation schemes was discussed. Furthermore, the optimized three-
dimensional (3-D) space vector modulation for balanced and unbalanced
system was explained. A new 3-D OSVPWM technique is proposed to carry
51. 111
out the necessary calculations taking the actual values of the dc voltages in
the modulation process and therefore undesirable harmonic distortions in
output waveform is avoided in unbalanced condition. The optimized 3-D
space vector modulation algorithm for cascaded H-bridge inverter was
proposed to handle the zero-sequence component caused by unbalanced load.
Using the proposed 3-D OSVPWM, balanced and unbalanced systems can be
modulated with balanced or unbalanced dc voltages. The computational cost
of the proposed modulation technique is very low and the technique can be
applied to multilevel inverter with any number of levels.