This paper presents the design of a bandgap voltage reference circuit in a 0.18um CMOS process. Simulation results show the circuit outputs 1.203V over an operating temperature range of -40 to 125 degrees Celsius. The output voltage varies by 0.026mV/C with temperature and 3.89mV/V with power supply variations from 1.62V to 1.98V. The layout area is 0.245mm by 0.133mm. Key aspects of the design include the use of a PTAT circuit, dummy transistors, and a cascode configuration.

1. A Bandgap Voltage Reference Circuit Design In
0.18um CMOS Process
Yanyan Cai Liqin Yue
Information Engineering College Information Engineering College
Huanghe Science and Technology College Huanghe Science and Technology College
Zhengzhou, China Zhengzhou, China
51861557@qq.com yueliqin316@163.com
Abstract—This paper presents a design and analysis
method of a bandgap reference circuit. The Bandgap design is
realized through the 0.18um CMOS process. Simulation results B.
show that the bandgap circuit outputs 1.203V in the typical
operation condition. The variance rate of output voltage is 1
0.026mV/ with the operating temperature varying from -40 PTAT: proportional
to 125 . And it is 3.89mV/V with the power supply changes to absolute temperature IPTAT
from 1.62V to 1.98V. The layout area is 0.245mm*0.133mm. M4~M9 PMOS op1
Keywords- CMOS; Bandgap Voltage Reference; Spectre;
PTAT
op1 inp inn
I. VEB1 = VEB 2 + I × R1 (2)
/
(ADC) / (DAC) IC I
VBE1 − VBE 2 = VT ln − VT ln C = VT ln n
1. CMOS 2.
IS nI S (3)
3.
4. PSRR
VBE1 − VBE 2 VT ln n
I PTAT = =
R1 R1 (4)
0.18um CMOS Q1 Q2 n Q1 Q2
-40 125 4 VT
0.026mV/ 1.62V 1.98V PTAT PTAT M6 M9
3.89mV/V R2 Q3
245um*133 um
II. CMOS R2
Vo = Vbg 1.2 v = I PTAT × R2 + VBE 3 = VT ln n + VBE 3 (5)
R1
A.
VBE - 5
1.5mV/K VT VT=KT/q ∂Vo R2 ∂V ∂V
= ln n T + BE 3 (6)
0.087mV/K VT K VBE ∂T R1 ∂T ∂T
VREF , (6)
[3]
Vref = VBE + KVT (1) Q2 Q1 n
R2 R1 6
K VBE Vo
978-1-4244-8039-5/11/$26.00 ©2011 IEEE

2. 3 Bandgap
1 CMOS
B.
III. Bandgap
Q 1 Q2 Q3 Q1
A. dummy
1 M4~M6 M7~M9
dummy R1 R2
Bandgap
M1~M12 245um*133 um 3
op1 2
cascode
IV.
C2 TSMC0.18 CMOS Cadence
1 Spectre 4-6
[6]
1
“en” “vs1”0, “vs2” “vs3” 1 M15 M17
M3~M6
“en” 0 1 C1 “vs1”
0 “vs2” 1 “vs3” 0 M15 M17 “inp”
“inn” 0 1 0 M3~M6
M13 M14 C1 “vs1” I2
“vs2” 0 “vs3” 1 M15 M17
“vs1”
4 Bandgap
5 Bandgap 64 corners
4 Bandgap
2

3. 1.203V -40 125
0.026mV/ 1.62V 1.98V
3.89mV/V
6 Bandgap
5 Bandgap corners
(1.98V), (1.62V)
125 -40 MOS FF SS
FF SS FF SS FF
SS 1.217V, 1.197V
6 Bandgap
765.1ns
V.
TSMC0.18um CMOS
-40 125
1.62V 1.98V
REFERENCES
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327
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Voltage Reference in CMOS
[7] process”,IEEE J.Solid State Circuits,Vol.30,1995