This document provides a device modeling report for an operational amplifier (opamp) with part number HA17558 manufactured by Renesas. It includes simulation results and comparison tables summarizing the opamp's output voltage swing, input offset voltage, slew rate, input bias current, open loop voltage gain, and common-mode rejection ratio.

1. Device Modeling Report
COMPONENTS: OPERATIONAL AMPLIFIER
PART NUMBER: HA17558
MANUFACTURER: RENESAS
REMARK TYPE: (OPAMP)
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

2. Spice Model
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

3. Output Voltage Swing
Simulation result
20V
0V
-20V
-500mV -250mV 0V 250mV 500mV
V(Vout)
V_V1
Evaluation circuit
Rl oa d 10 k Vo ut U1
OU T1 VCC
-IN1 - OU T2
+
+ IN 1 -IN2
+ -
VEE + IN 2
HA 175 58
V+
V1 V-
0V dc 15 Vd c
-15 Vdc
0
Comparison table
Output Voltage Swing Measurement Simulation %Error
+Vout(V) 14.000 13.999 -0.007
-Vout(V) -14.000 -13.999 -0.007
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

4. Input Offset Voltage
Simulation result
20V
14V
0V
-14V
-20V
-1.0mV 0V 1.0mV 2.0mV
V(Vout)
V_Vin
Evaluation circuit
Rl oa d
2k
U1
OU T1 VCC
Vo ut
-IN1 - OU T2
+
+ IN 1 -IN2
+
-
Vi n VEE + IN 2
Vi
VO FF = 0 VO FF = 0
HA 175 58
VA MPL = 0 VA MPL = 0 V+
FREQ = 0 FREQ = 0 V-
AC = 0 AC = 0
DC = 0 DC = 0 15 Vd c
-15 Vdc
0
Comparison table
Measurement Simulation %Error
Vos(mV)
0.500 0.492 -1.600
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

5. Slew Rate
Simulation result
20V
0V
-20V
0s 50us 100us 150us 200us
V(Vout)
Time
Evaluation circuit
Vo ut U1
OU T1 VCC
-IN1 - OU T2
+
+ IN 1 -IN2
+
-
VEE + IN 2 V+
Vi V1 = -1 4 Vi n
V2 = 14
HA 175 58
VO FF = 0 TD = 0 .1m 15 Vd c
VA MPL = 0 TR = 1 0n
FREQ = 0 TF = 10n
AC = 0 PW = 1 m V-
DC = 0 PE R = 2m
-15 Vdc
0
Comparison table
Slew Measurement Simulation %Error
Rate(v/us) 1.000 1.018 1.800
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

6. Input current Ib, Ibos
Simulation result
60nA
55nA
50nA
45nA
40nA
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms
I(Vi) I(Vin)
Time
Evaluation circuit
Vo ut U1
OU T1 VCC
-IN1 - OU T2
+
+ IN 1 -IN2
+ -
VEE + IN 2
Vi n V+
VO FF = 0
HA 175 58
Vi VA MPL = 0
VO FF = 0 FREQ = 0 15 Vd c
VA MPL = 0 AC = 0 V-
FREQ = 0 DC = 0
AC = 0 V1 -15 Vdc
DC = 0
0.4 92m
0
Comparison table
Measurement Simulation %Error
Ib(nA) 50.000 50.020 0.040
Ibos(nA) 5.000 5.016 0.318
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

7. Open Loop Voltage Gain vs. Frequency , Av-dc, f-0dB
Simulation result
120
80
40
0
1.0Hz 100Hz 10KHz 1.0MHz 100MHz
DB(V(Vout)/V(Vin:+))
Frequency
Evaluation circuit
RL 2k Vo ut U1
OU T1 VCC
-IN1 - OU T2
+
+ IN 1 -IN2
+ -
VEE + IN 2
V+
Vi n
HA 175 58
Vi
VO FF = 0 VO FF = 0 V- 15 Vd c
VA MPL = 0 VA MPL = 0
FREQ = 0 FREQ = 0
AC = 0 AC = 1 m -15 Vdc
DC = 0 DC = 0 .492 m
0
Comparison table
Measurement Simulation %Error
f-0dB(MHz) 1.000 1.000 0.000
Av-dc(dB) 104.000 104.069 0.066
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

8. Common-Mode Rejection Voltage gain
Simulation result
20V
10V
0V
-10V
-20V
0s 1.0s 2.0s 3.0s 4.0s
V(Vout)
Time
Evaluation circuit
Vo ut U1
OU T1 VCC
-IN1 - OU T2
+
+ IN 1 -IN2
+ -
V1
-0.49 2m VEE + IN 2
V+
HA 175 58
V-
15 Vd c
V
VO FF = 0 -15 Vdc
VA MPL = 5
FREQ = 1
AC = 0
DC = 0
0
Common Mode Reject Ratio=20*LOG(159753.3596/(15.835/10))
= 100.0766 dB
CMRR Measurement Simulation %Error
(dB) 100.000 100.077 0.077
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008