04 ota053001 clock synchronization theory issue1.0

HUAWEITECHNOLOGIES CO., LTD. All rights reserved
www.huawei.com
Internal
OTA053001 Clock
Synchronization Theory
ISSUE1.0

HUAWEITECHNOLOGIES CO., LTD.
Page 2All rights reserved
Upon completion of this course, you will be able to:
 Understand the optical transmission
synchronization and network synchronization
concepts
 Explain SDH network synchronization basic
fundamentals

Chapter 1 Principle of clock synchronizationChapter 1 Principle of clock synchronization
Chapter 2 SDH network synchronizationChapter 2 SDH network synchronization
architecture and methodsarchitecture and methods
Chapter 3 Clock synchronization requirementsChapter 3 Clock synchronization requirements

Chapter 1 Principle of Clock SynchronizationChapter 1 Principle of Clock Synchronization
1.1 Synchronization methods1.1 Synchronization methods
1.2 Clock types1.2 Clock types
1.3 Working modes1.3 Working modes

Principle of Clock Synchronization
 Mater-slave Method
 PRC (Primary Reference Clock)
G.811
 Transit SSU (Synchronization Supply
Unit) G.812
 SASE (Stand-Alone Synchronization
Equipment) SSU G.812
 SDH Equipment Clock (SEC) G.813
Master
Slave
SlaveSlaveSlaveSlave
Slave
Synchronization methodsSynchronization methods

 Mutual Synchronization
 In mutual synchronization,
each clock sends and
receives a timing reference
to (from) all other clocks in
the network. Network timing
is determined by each clock
by averaging the
synchronization signals it
receives from all other
clocks in the network.
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Synchronization methodsSynchronization methods

 Atomic cesium clock
 Quartz crystalloid oscillator
 Atomic rubidium clock
 GPS (Global Positioning System)
Clock typesClock types

 Normal mode (locked)
 Holdover mode
 Free run mode
Working modesWorking modes

Questions
 How many clock working modes, and which is the optimum one?

Chapter 2 SDH Network SynchronizationChapter 2 SDH Network Synchronization
Architecture and ModesArchitecture and Modes
2.1 Effect of SDH system in network2.1 Effect of SDH system in network
synchronizationsynchronization
2.2 SDH network synchronization architecture2.2 SDH network synchronization architecture
2.3 SDH network synchronization modes2.3 SDH network synchronization modes
2.4 SDH synchronization references chain2.4 SDH synchronization references chain

Effect of SDH system in network synchronizationEffect of SDH system in network synchronization
SDH Network Synchronization Architecture and Modes
 Effect of pointer adjustment in the network boundaries
 Mixed transmission add difficulties to the synchronization
planning
 SDH self healing add some difficulties to synchronization
source choice

2.1 Effect of SDH system in network2.1 Effect of SDH system in network

 Intra-Node (Star
topology) distribution
architecture
SSU
G.813
G.813
G.813
G.813
Intra-Node
Node boundary
To other nodes
Secondary PRC SD trail
SDH network synchronization architectureSDH network synchronization architecture

 Inter-Node distribution architecture G.811
PRC
G.812 G.812
G.812 G.812 G.812 G.812
SDH network synchronization architectureSDH network synchronization architecture

2.1 Effect of introducing SDH system in network2.1 Effect of introducing SDH system in network

 Synchronous
 All the clocks in the network locked to only one source clock
(Master-Slave)
 Pseudo-synchronous
 The network clocks locked to two or more source clocks.
SDH network synchronization modesSDH network synchronization modes

 Plesiochronous
 The network node clock/s can’t use the source reference
clock, so the node clock/s enter free-run or holdover mode.
 Asynchronous
 The network node clock presents big amount of frequency
difference.
SDH network synchronization modesSDH network synchronization modes

2.1 Effect of introducing SDH system in network2.1 Effect of introducing SDH system in network

SDH network synchronization references chainSDH network synchronization references chain
S
 Not more than 60 SECs in a chain
 Not more than 20 SECs between
two SSUs
 Not more than 10 SSUs in the chain

Clock Synchronization Requirements
 Primary Reference Clock (PRC) performance
requirements
 Node clock Synchronization Supply Unit (SSU)
performance requirements
 SDH Equipment Clock (SEC) performance requirements
 SDH clock implementation

 Master clock used to synchronize the entire network with
a frequency accuracy of < 1 x 10-11
 Outputted interface signals are 2048kHz or 2048 bits/s
Primary Reference Clock (PRC) performance requirementsPrimary Reference Clock (PRC) performance requirements

 Transit node with a frequency accuracy of < 1.6 x 10-8
 Local node with a frequency accuracy of < 4.6 x 10-6
 Outputted interface signals are 2048kHz , 2048 bits/s
and STM-N service signal
Node Clock Or SSU Performance RequirementsNode Clock Or SSU Performance Requirements

SDH Equipment Clock (SEC) Performance RequirementsSDH Equipment Clock (SEC) Performance Requirements
 SEC with a frequency accuracy of < 4.6 x 10-6
 Outputted interface signals are 2048kHz , 2048 bits/s
and STM-N service signal

SDH Clock Implementation
 External synchronization timing source: In this case the timing
for synchronization of NEs is provided by an external timing
source.
 Timing extracted from the received signals: This is a widely
used synchronization timing mode. It includes three types:
through timing, loop timing and line timing.
 Internal timing source: Every NE possesses an internal timing
source, so that it can use the internal timing source when
losing external synchronization source.

Summary
 What are SDH common synchronization
methods and clock source types, also the
working modes
 The effect of introducing SDH network in the
network synchronization, what is the
optimum architecture for SDH network
synchronization
 General implementation of SDH clock

04 ota053001 clock synchronization theory issue1.0

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Viewers also liked

Viewers also liked (19)

Similar to 04 ota053001 clock synchronization theory issue1.0

Similar to 04 ota053001 clock synchronization theory issue1.0 (20)

04 ota053001 clock synchronization theory issue1.0

Editor's Notes