A powerpoint presentation slide for High Speed Input Output ,a topic of Operating Systems.

1. Welcome !
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2. High Speed
Input/Output

3. Presented By….
Rafiul Ahmed – 2015-1-60-028
Farhana Haque – 2015-1-60-073
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4. Overview
 Introduction
 Input and Output(I/O)
 Computer Architecture
 System bus
 I/O module
 I/O Techniques
 I/O Procedure
 High Speed I/O
 Proper Use Of Advanced I/O Tools
 More Friendly OS Architecture
 Conclusion

5. Introduction
 Input : Signals or data received by
the system.
 Need input devices. E.g: Mouse
Keyboard etc.
Output : Signals or data generated
by the system.
 Need output devices.
E.g: Monitor, Printer etc.
Peripheral Devices

6. Computer Architecture
 System Bus :
I/O Module : I/O module is an intermediate between I/O devices
and CPU. It is used to exchange information between I/O devices and
CPU through Interfaces like Cmd prompt, GUI etc.
Determine location
Determine operation
Carry Information

7. Computer Architecture(Cont.)
 I/O Technique :
Programmed I/O Interrupt Driven I/O Direct Memory Access
 CPU waits for I/O
module to
complete
operation.
 CPU time wastes.
 CPU issues read
command and does
its works
 I/O module finishes
and Interrupts
 CPU gets back
 CPU gives permission IO
module to directly read
and write to/from the
main memory

8. Computer Architecture(Cont.)
 I/O Technique :
I/O problems :
 Slower than CPU & RAM.
 Need I/O modules.
 For variety of peripherals it may show different amount of data, speeds &
formats.
 Whole system must have to be efficient to receive input & show output.
Programmed I/O Interrupt Driven I/O Direct Memory Access

9. Recommendation-High Speed I/O
Proper Use Of
Advanced I/O Tools
Compatible Operating
System Architecture
High
Speed
I/O
More dependent on hardware than software

10. Proper Use of Advanced I/O Tools
 FPGAs
 IEEE 1394
 Gigabit Serial I/O
 Cryptographic Accelerator

11. FPGAs
 Field-Programmable Gate Array

12. Use Of FPGAs
DCM
(Digital Clock Manager)

13. Use Of FPGAs
Virtex 4
Provides 4GHz CPU
Horsepower!!!

14. Use Of FPGAs
Virtex 5
Provides 6.5GHz CPU
Horsepower!!!!

15. FPGAs Are

16. IEEE 1394-An interface standard
 A very high-speed rate of data transfer (speeds up to 400 Mbps )
 Ability to chain devices together in a number of different ways.
 Reduces the need for buffering and helps ensure a continuous
presentation of multimedia for the viewer.
FireWire
(Apple)

17. Immerged Technology
Lightning
(Apple Inc.)
Thunderbolt
(Intel)
USB Type C

18. Gigabit Serial I/O :
MGT: Multi-Gigabit Transceiver- Receives parallel data and
allows transportation of high bandwidth data over a serial
link.
 For getting data on and off of chips, boards, or boxes, nothing beats
a high-speed serial link.
 Wire speeds from 1 to 12 Gb/s.
 Payloads from 0.8 to 10Gb.

19. Cryptographic Accelerator
Provides high-performance compression
And cryptography on devices deployed
in wireless, telecom, cloud, data centers,
and enterprise systems

20. Examples
The BSD family of systems has - OpenBSD Cryptographic
Framework (OCF)
 Linux systems have the Crypto API
 Solaris OS has the Solaris Cryptographic Framework (SCF) and
 Microsoft Windows has the Microsoft CryptoAPI.

21. Operating System Architecture
Typical Operating
System
Occasionally Takes
Advantage of
Cryptographic Tools I/O Module

22. Operating System Architecture
Proposed OS
Architecture by a
research team of
Columbia University

23. Operating System Architecture
New I/O-centric operating system
architecture that removes the memory
and CPU from the data path.
In this scheme, the operating system
becomes a manager of data flows
among the various peripheral devices.
Act as a resource scheduler. The actual
data transfer occurs directly between
cards.

24. More Requirements
 We envision a simple language and associated runtime
environment(FML)
 Device status and capability sensing, programming the direct
memory access (DMA) controllers on the various peripherals.
 Ability of using Dynamic code generation(DCG) techniques on
FPGAs.
 Ability to handle exceptions:
 data-processing errors (e.g. device failure or data corruption)
 external exceptions (e.g. a TCP Reset or a Path MTU Discovery ICMP
response from a router)

25. Conclusions
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 High-speed I/O systems offer challenges in both circuit and
communication system design.
 Development of programmable logic with integrated high-
speed transceivers has helped to accept the challenges.
 USB, Firewire, FPGA, Cryptographic Accelerators etc. have
brought about a revolution in I/O.
 Focus should be on designing more HSIO friendly Operating
System Architecture.

26. Resources
http://www.intel.ru/content/dam/www/public/us/en/documents/sol
ution-briefs/integrated-cryptographic-compression-accelerators-
brief.pdf
https://www.youtube.com/watch?v=p1UTuy8r-9s
http://www.cs.columbia.edu/~angelos/Papers/flowOS-
sigcomm03.pdf
http://www.ece.tamu.edu/~spalermo/ecen474/lecture26_ee474_hig
h_speed_io_overview.pdf
http://www.slideshare.net/ergurpreet123/input-output-interfaces
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27. Questions Or Suggestions
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Rafiul Ahmed-rafiul.ahmed@yahoo.com
Farhana Haque-farhanatisha23@gmail.com

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