I/O System

2,274 views

Published on

Nagarajan.R

Published in: Education
0 Comments
5 Likes
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total views
2,274
On SlideShare
0
From Embeds
0
Number of Embeds
3
Actions
Shares
0
Downloads
0
Comments
0
Likes
5
Embeds 0
No embeds

No notes for slide

I/O System

  1. 2. INPUT / OUTPUT PROCESSING MAIN JOB OF COMPUTER?
  2. 3. <ul><li>ROLE OF OPERATING SYSTEM? </li></ul><ul><ul><li>To manage and control I/O operations and I/O devices. </li></ul></ul><ul><ul><li>TOPICS COVERED </li></ul></ul><ul><ul><li>I/O Hardware </li></ul></ul><ul><ul><li>I/O Application Interface </li></ul></ul>
  3. 5. I/O HARDWARE <ul><li>PORT </li></ul><ul><li>A Connection Point through which a device communicates with a computer system by sending signals </li></ul>
  4. 6. I/O HARDWARE <ul><li>BUS </li></ul><ul><ul><li>A common set of wires used by devices for communication(daisy chain or shared direct access) </li></ul></ul><ul><ul><ul><li>Example </li></ul></ul></ul><ul><ul><ul><li>PCI , ISA, SCSI </li></ul></ul></ul>
  5. 7. I/O HARDWARE <ul><li>CONTROLLER </li></ul><ul><ul><li>A collection of electronics that can </li></ul></ul><ul><ul><li>operate a port,a bus,or a device </li></ul></ul><ul><ul><ul><li>Serial port controller, SCSI </li></ul></ul></ul><ul><ul><ul><li>controller, IDE controller </li></ul></ul></ul><ul><li>The processor give commands and data to a controller to accomplish an I/O transfer </li></ul><ul><ul><li>Direct I/O instructions </li></ul></ul><ul><ul><li>Memory-mapped I/O </li></ul></ul><ul><ul><li>Direct I/O + memory mapped I/O </li></ul></ul>
  6. 8. Controller… <ul><li>I/O controller has 4 types of registers </li></ul><ul><ul><li>Status registers - also known as flag register or condition code register (CCR) ) is a collection of flag bits for a processor. </li></ul></ul><ul><ul><li>Control registers- - is a processor register which changes or controls the general behavior of a CPU or other digital device. </li></ul></ul><ul><ul><li>Data-in registers -Used by Host to get Input </li></ul></ul><ul><ul><li>Data-out registers -Used by Host to send output </li></ul></ul>
  7. 9. PCI BUS STRUCTURE
  8. 10. <ul><li>A PCI Bus consists of Serial Port Controller, SCSI Bus controller etc., </li></ul><ul><li>A serial port controller is a simple device controller and it is a chip or portion of a chip in the computer. </li></ul><ul><li>It controls the signal s on the wires of a serial port. </li></ul><ul><li>SCSI bus controller is contrast to serial port controller as SCSI protocol is complex . </li></ul><ul><li>SCSI bus controller is frequently implemented as a separate circuit board or a host adapter that plugs into the computer. </li></ul><ul><li>It consists of a processor,Microcode and Private memory to enable it to process SCSI protocol messages </li></ul>PCI BUS STRUCTURE
  9. 11. <ul><li>Three interaction models between I/O controllers and CPUs </li></ul><ul><ul><li>Polling </li></ul></ul><ul><ul><li>Interrupt </li></ul></ul><ul><ul><li>Direct Memory Access(DMA) </li></ul></ul>I/O HARDWARE
  10. 12. POLLING <ul><li>Polling refers to the situation where a device is repeatedly checked for readiness. </li></ul><ul><ul><li>Is reasonable only if the device and controller are fast. </li></ul></ul><ul><ul><li>EXAMPLE </li></ul></ul><ul><ul><li>-> 2 bits are used </li></ul></ul><ul><ul><li>-> The controller indicates its state through the busy bit in the </li></ul></ul><ul><ul><li>status register. </li></ul></ul><ul><ul><li>-> The controller sets the busy bit when it is busy working and </li></ul></ul><ul><ul><li>clears the busy bit when it is ready to accept the next </li></ul></ul><ul><ul><li> command </li></ul></ul>
  11. 13. Example continued… <ul><li>The host signals its wishes via the command-ready bit in the command register. </li></ul><ul><li>The host sets the command ready bit when a command is available for the controller to execute. </li></ul><ul><li>Process </li></ul><ul><li>1.The host repeatedly reads the busy bit until that bit becomes clear. </li></ul><ul><li>2.The host sets the write bit in the command register and writes a byte into the data out register </li></ul><ul><li>3.The host sets the command ready bit </li></ul>
  12. 14. PROCESS contd… <ul><li>4.When the controller notices the command ready bit is </li></ul><ul><li>set it sets the busy bit. </li></ul><ul><li>5.The controller reads the command register and sees the write command. </li></ul><ul><li>6.It reads the data out register to get the byte and does the I/O to device. </li></ul><ul><li>7.The controller clears the command ready bit, clears the error bit in the status register to indicate that the device. </li></ul><ul><li>8.I/O succeeded, and clears the busy bit to indicate that it is finished. </li></ul>
  13. 15. INTERRUPTS <ul><li>A Temporary stopping of a task for a while and Resuming it later </li></ul><ul><li>CPU Interrupt request line triggered by I/O device </li></ul><ul><li>Interrupt handler receives interrupts </li></ul><ul><li>Maskable to ignore or delay some interrupts </li></ul><ul><li>Interrupt vector to dispatch interrupt to correct handler </li></ul><ul><ul><li>Based on priority </li></ul></ul><ul><ul><li>Some unmaskable, some maskable </li></ul></ul>
  14. 16. INTERRUPTS IN SIGNAL HAS PRIORITY… INTERRUPT HANDLER ACTS LIKE CPU OTHER PROCESS
  15. 17. INTERRUPT <ul><li>Interrupt mechanism also used for </li></ul><ul><ul><li>exceptions and </li></ul></ul><ul><ul><li>system calls </li></ul></ul><ul><li>Interrupt handlers can be divided into two </li></ul><ul><ul><li>Top half </li></ul></ul><ul><ul><li>Bottom half </li></ul></ul>
  16. 18. INTERRUPT-DRIVEN CYCLE
  17. 19. DIRECT MEMORY ACCESS(DMA) <ul><ul><li>Used to avoid programmed I/O for large data movement </li></ul></ul><ul><ul><li>Requires DMA controller for offloading of work in case of large transfers </li></ul></ul><ul><ul><li>Handshaking between DMA controller and the Device Controller is performed via a pair of wires called DMA-request and DMA-acknowledge </li></ul></ul><ul><ul><li>Bypasses CPU to transfer data directly between I/O device and memory </li></ul></ul>
  18. 20. STEPS IN DMA TRANSFER
  19. 21. APPLICATION I/O INTERFACE <ul><li>The OS could be designed such that new devices can be attached to the computer without the OS being rewritten with the help of Application I/O interface. </li></ul><ul><li>I/O system calls encapsulate device behaviors in generic classes </li></ul><ul><li>Device-driver layer hides differences among I/O controllers from kernel </li></ul><ul><li>Devices vary in many dimensions </li></ul><ul><ul><ul><li>Character-stream or block </li></ul></ul></ul><ul><ul><ul><li>Sequential or random-access </li></ul></ul></ul><ul><ul><ul><li>Sharable or dedicated </li></ul></ul></ul><ul><ul><ul><li>Speed of operation </li></ul></ul></ul><ul><ul><ul><li>read-write, read only, or write only </li></ul></ul></ul>
  20. 22. BLOCK AND CHARACTER DEVICES <ul><li>Block devices include disk drives </li></ul><ul><li>Commands include read, write, seek </li></ul><ul><li>Raw I/O or file-system access </li></ul><ul><li>Character devices include keyboards, mice, serial ports </li></ul><ul><ul><ul><li>Commands include get, put </li></ul></ul></ul><ul><ul><ul><li>Libraries layered on top allow line editing </li></ul></ul></ul>
  21. 23. NETWORK DEVICES <ul><li>Different from block and character devices to have own interface </li></ul><ul><li>Unix and Windows NT/2000 include socket interface </li></ul><ul><ul><li>Separates network protocol from network operation </li></ul></ul><ul><ul><li>Includes select functionality (returns information about which socket has room for data or has data available to be read) </li></ul></ul>
  22. 24. CLOCKS AND TIMERS <ul><li>Programmable interval timer used for timings, periodic interrupts </li></ul><ul><li>ioctl (on UNIX) covers odd aspects of I/O such as clocks and timers </li></ul><ul><li>Provides three basic functions </li></ul><ul><ul><li>Give the Current Time </li></ul></ul><ul><ul><li>Give the Elapsed Time </li></ul></ul><ul><ul><li>Set a Timer to Trigger Operation </li></ul></ul>
  23. 25. BLOCKING AND NON-BLOCKING I/O <ul><li>Blocking - process suspended until I/O completed </li></ul><ul><ul><li>Easy to use and understand </li></ul></ul><ul><ul><li>Insufficient for some needs </li></ul></ul><ul><li>Nonblocking - I/O call returns as much as available </li></ul><ul><ul><li>User interface, data copy (buffered I/O) </li></ul></ul><ul><ul><li>Implemented via multi-threading </li></ul></ul><ul><ul><li>Returns quickly with count of bytes read or written </li></ul></ul><ul><li>Asynchronous - process runs while I/O executes </li></ul><ul><ul><li>I/O subsystem signals process when I/O completed </li></ul></ul>

×