Series compensation is installed in power system networks to increase power transfer capacity, improve the system stability, reduce system losses, improve voltage regulation and for achieving flexible power flow control. Distance relays are widely used as main or backup protection of transmission lines including series-compensated transmission lines. The performance of conventional distance relays is affected by series capacitors and cause certain protection issues. This paper briefly discusses the problems like voltage inversion, current inversion, overreach and under reach during the fault conditions specific to series compensated lines. The behavior of capacitor protection techniques is discussed with simulations performed using Real Time Digital Simulator (RTDS) simulator for a typical 400 kV system having series compensation. The analysis is based on Transmission Line fault simulations, internal and external to the 400-transmission line where the Fixed Series Compensation (FSC)is installed.
2. Kumar and Meera 093
The capacitor, MOV or bypass switch coming in the fault
loop depends on the ratings of capacitor and energy limits
of MOV. Some of the problems that distance relay
encounters in the presence of series capacitors are current
inversion, voltage inversion, overreach and under reach.
Thus, it is required to evaluate the performance of the relay
for these conditions. The power system is modeled with the
series capacitor at one end of the transmission line on
RTDSTM and by simulating various fault conditions, tests
are carried out. The faulted voltage and current signals at
the relay location is fed to the relay (also modeled on
RTDS) and the performance analyzed.
Voltage and current Inversion
The first challenge that a distance relay located on a series
compensated line faces is the dynamic changes that occur
in the total impedance presented by the series capacitor
and its protection devices. The state of the series capacitor,
whether it is in service/by-passed, or partly in service and
partly by-passed, complicates the reach settings of zone 1
elements.
Series capacitors located at line ends are more likely to
create voltage and current inversions because of the
absence of line impedance between the relay location and
series capacitor (R.J. Marttila, 1992).
Voltage inversion: This phenomenon is experienced on
series compensated lines, if the impedance between the
fault point and the relaying point is capacitive but the overall
impedance between the power system source and fault
point is still inductive i.e. the reactance of the capacitor is
greater than the reactance of the line section up to fault
point. During voltage inversion the voltage at the relaying
point will be of the opposite sign with the source voltage,
causing the voltage inversion. A voltage inversion on the
power system results in a distance element (polarized by
voltage) to incorrectly identify the fault direction.
Current inversion: For a fault on series compensated line
the impedance between the source and fault point can be
capacitive. Under this circumstance, the fault current will be
capacitive instead of inductive. This phenomenon is known
as a current inversion and leads to false directional decision
in distance relays.
The presence of series compensation also generates sub
harmonics that can cause distance elements to overreach.
System Model
The real time digital simulator used in the tests reported in
this paper is supplied by RTDS Technologies, Inc. Canada.
The simulator performs fully digital electromagnetic
transient power system simulation in real time, utilizing the
Dommel Algorithm (Hermann W. Dommel, 1968) similar to
non-real time EMTP-type programs. The RTDS has an
Electromagnetic Transient type representation and so can
provide a very detailed and realistic model of the system,
including all nonlinearities. The simulator with parallel
processing architecture is specifically designed for power
system simulations and ensures continuous real-time
operation. This type of simulator is an ideal tool for
designing, studying, and testing protection schemes (Real
Time Digital Simulator (RTDS TM) user’s Hardware and
Software manual set, RTDS Technologies, Canada).
A. Power System Network model
The power system network chosen for simulation is based
on recommendations of CIGRE Working Group 04 of Study
Committee 34 (Evaluation of characteristics and
performance of power system protection relays and
protective systems, CIGRE Working Group 04 of Study
Committee 34 (Protection), 1986). Fig 1 shows the 400 kV
power system network simulated on RTDS, with source at
either ends of the line. The parallel line is kept open by the
circuit breakers at either end of the line. The data used for
the system simulation are given in Appendix I. The
transmission line is modeled using the distributed
parameter Bergeron line model. The network behind the
buses at either end are represented by voltage sources
behind the impedance calculated based on the short circuit
contribution from the network. The series capacitor on
RTDS is modeled as shown in Fig 2. A compensation level
of 40 % has been chosen. The Lightning arrester across
the series capacitor has been modeled with its nonlinear
characteristics and providing of the discharge voltage at
@10 kA and the associated decay factor.
a. Relay model
Fig 3 (a) and 3(b) shows the sampling, extraction of
fundamental component of voltage and computation of line-
to-line voltages. The currents are computed similarly. The
Fig.1: System modeled on RTDS
Fig. 2 MOV protected series capacitor
3. Int. Res. J. Power Energy Engin. 094
Relay logic diagram implemented on RTDS for computing
the line-to ground impedance and line-to-line impedance is
shown in Fig 3(c) and Fig 3(d).
The impedance computed by the relay model is plotted on
the operating characteristic (mho and quadrilateral
characteristic) of the relay model. The impedance locus in
the complex plane directly indicates whether the fault is
within or outside the protected zone. Under normal
operating conditions, the impedance locus remains outside
the operating characteristic. For internal faults, the
measured impedance locus moves into the operating
characteristic and there lay (model) is expected to issue a
trip command to the circuit breaker modeled in RTDS.
Fig 3(a) Voltage sampling for Relay model
Fig 3(b): Line to line Voltage computationsfor Relay model
Fig. 3(c): Line-to-Ground positive sequence impedance
computation
Fig 3(d): Line-to-Line positive sequence impedance
computation
Simulation Results and Analysis
The dynamic performance of the distance relay model is
studied for various fault locations. The relay model is first
validated by comparing the measured reactance and
resistance (without series compensation) with the
transmission line reactance and resistance from the relay
location to the fault position. It was observed that after
decaying oscillations in the reactance and resistance the
values settled to the desired values, thereby validating the
relay model.
A. Single Line to Ground fault (SLG) – 0 % line length
An SLG fault (R-phase) was created at 0 % of the line
length, with a fault resistance of 20 ohms. Figure 4 (a)
shows pre-fault and post-fault voltage and current
waveforms at the relay location, Arrester currents &
energies and also the status of the bypass switch as
obtained from the real-time simulation tests. Fig 4(b) shows
the Impedance seen by the relay with series capacitor in
the fault loop.
The results show that the fault current is 16.41 kA and the
energy dissipation across MOV is 38.8 MJ which is less
than the threshold energy limit of the MOV. So, the bypass
switch will not operate resulting in the capacitor as well as
MOV to remain in the fault loop. Due to the combination of
MOV and the series capacitor branch in the fault loop, the
impedance seen by relay is slightly capacitive as seen in
figure 4(b). It can also be observed from fig 4(a) that voltage
inversion is occurring in this case due to which, the locus of
the impedance seen by the relay lies outside the zone (mho
characteristic) leading to mal-operation of the relay.
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Fig 4 (a): Voltages and currents at relay location for a SLG
fault at 0% of the transmission line
Fig 4(b): Impedance seen by the relay with series
capacitor in the fault loop
.
Fig 4(c): Locus of Impedance seen at the relaylocation
forfault at 0 % along the line.
However, a relay with Quadrilateral characteristic having
memory polarization and also higher resistive reach setting
(Appendix II gives the settings calculations (Sub-committee
on relay/protection under task force for power system
analysis under contingencies, 2014), the locus of the
impedance lies in zone 1 of the relay as shown in figure
4(d). Therefore, the relay picks up and trips in zone 1.
Fig 4(d): Locus of Impedance seen by the relay for a fault
at 0% 0 % along the line
5. Int. Res. J. Power Energy Engin. 096
a. Three-phase bus fault (3 Phase)
Figure 5 (a) shows the CVT voltages, CT currents, MOV
currents & voltages and its energy dissipation, for a 3 phase
fault at sending end bus terminals. This is seen as a
forward fault by the relay leading to its mal-operation. Like
a normal fault in forward direction a phase shift in CT
currents which lags the CVT voltages is observed in figure
5(a). Locus of impedance as seen by i.e. shown in figures
5(b) and 5(c) respectively.
Fig 5 (a): Voltages and Currents at Relay location for a 3
Phasebus fault at sending end
Fig 5(b): Locus of Impedance seen by the relay for a 3
Phase bus fault
Fig 5(c): Locus of Impedance seen by the relay for a 3
Phase bus fault
b. Three-phase fault (3 Phase) – 100 % line length
A 3-phase fault was created at 100 % of the line length with
zero fault resistance. Fig 6 (a), 6(b) and 6(c) shows the
plots of CT currents and CVT voltages and the impedances
Fig 6 (a): Voltages and Currents at Relay location for a 3
Phase fault at 100% line length
As seen by relays located at the sending end with mho and
quadrilateral characteristic. For this case, the fault was
correctly identified by relays (mho as well as quadrilateral
characteristic) as a fault in Zone 2.
7. Int. Res. J. Power Energy Engin. 098
APPENDIX I
A. Source
VS = 400kV ∟0o, 50 Hz
Source Impedance ZS = 145.45∟86.18oΩ
B. Transmission Line
Positive Sequence Resistance, (r1) = 0.02897 Ω/Km
Positive Sequence Reactance, (x1) = 0.3072 Ω/Km
Zero Sequence Resistance, (r0) = 0.2597 Ω/Km
Zero Sequence Reactance, (x1) = 1.0223 Ω/Km
Zero Sequence Susceptance (b0) = 2.347 µmho/Km
Positive Sequence Susceptance (b1) = 3.630 µmho/Km
Line length =117.85 Km
C. Load
Real Power, P = 1000 MW
Reactive Power, Q = 30 MVAR
D. Fixed Series Compensation: 40 %, Xc =14.48Ω
APPENDIX II
Total positive sequence impedance, Z1
1 = 36.364 ∟84.61º
Total zero sequence impedance, Z0
1 = 124.30 ∟75.74º
Total positive sequence impedance (secondary)
Z1 = CT/PT ratio x Z1
1= 10∟84.61º Ω
Distance relay characteristics are set based on the NRPC guidelines for transmission line protection.
Zone1 protection = 0.8*Z1= 8∟84.61º Ω
Zero compensation factor, K0 =
(𝑍0−𝑍1)
3𝑍1
=0.812
Time delay for zone1, td1 = 0 S
Total zero sequence impedance (secondary)
Z0 = 34.184 ∟75.74º Ω
Zone2 protection = 1.2*Z1 = 12∟84.61º Ω
Time delay for Zone2, td2 = 0.35 S
Zone 3 protection = 2*Z1 = 20∟84.61º Ω
Time delay for Zone3, td3 = 1 S
Resistive reach, Rreach = 30 Ω
Directional angle for Distance protection zones,
rgDir = -30º
Negative restraint angle for Distance protection zone,
ArgNeg Res= 115º