The document discusses cache memory organization and mapping schemes between main memory and cache memory. It provides examples of direct mapping, fully associative mapping, 2-way set associative mapping, and 4-block sector mapping. It also calculates the effective memory access time for a memory hierarchy with a 16KB cache and 1MB main memory, assuming an 8-word block size and 256-word set size with 32-way set associative mapping and a 95% cache hit ratio.

1. EC6020 – ARSITEKTUR KOMPUTER LANJUT
TUGAS – 4
CHAPTER 5
BUS, CACHE AND SHARED MEMORY
SOAL-SOAL TENTANG ORGANISASI-ORGANISASI CACHE MEMORY
(CACHE MEMORY ORGANIZATIONS)
ARWIN
NIM. 232 06 008
MAGISTER TEKNIK ELEKTRO
SEKOLAH TINGGI ELEKTRONIKA DAN INFORMATIKA
INSTITUT TEKNOLOGI BANDUNG
2006

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Problem 5.8 – The main memory of a computer is organized as 64 blocks with a block size of eight
(8) words. The cache has eight (8) block frames. In parts (a) through (d), show the mapping from the
numbered blocks in main memory to the block frames in the cache. Draw all lines showing the
mappings as clearly as possible.
a. Show the direct mapping and the address bits that identify the tag field, the block
number, and the word number.
b. Show the fully associative mapping and the address bits that identify the tag field and the
word number.
c. Show the two-way set-associativity mapping and the address bits that identify the tag
field, the set number, and the word number.
d. Show the sector mapping with four blocks per sector and the address bits that identify
the sector number, the block number, and the word number
Answer :
From the above statement, we get the memory and cache configuration information to calculate the
identification bits and the addressing scheme. They are :
Main memory has 64 blocks → 64 6n s= ↔ = because 2s
n =
Cache memory has 8 block frames 8 3m r→ = ↔ = because 2r
m =
Block size is 8 words 8 3b w→ = ↔ = because 2w
b =
a. Direct mapping cache
Tag field = 6 3 3s r− = − = bit
Block field = 3r = bit
Word field = 3w = bit

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The addressing and mapping scheme are as followed :

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b. 8-way Fully associativity cache
Tag field = 6s = bit
Word field = 3w = bit
The addressing and mapping scheme are as followed :

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c. 2-way Set associativity cache
Set = 4 2v d= ↔ = because 2d
v =
Tag field = 6 2 4s d− = − = bit
Set field = 2d =
Word field = 3w = bit
For 2-way associativity cache implementation, there will be 4 sets where each set consists of 2
block frames (subsets) and each subset will cover 2 main memory blocks. The 4-bit tag
determines which 2 main memory’s blocks have right access to a particular set at a time (see
the table below).
Set Number
(2 bits)
Block Frame
Number
Memory Block Number
(2-way associativity)
0 (00) 0 1B dan B 0, 16 and 32, 48
1 (01) 2 3B dan B 1, 17 and 33, 49
2 (10) 4 5B dan B 2, 18 and 34, 50
3 (11) 6 7B dan B 3, 19 and 35, 51
0 (00) 0 1B dan B 4, 20 and 36, 52
1 (01) 2 3B dan B 5, 21 and 37, 53
2 (10) 4 5B dan B 6, 22 and 38, 54
3 (11) 6 7B dan B 7, 23 and 39, 55
0 (00) 0 1B dan B 8, 24 and 40, 56
1 (01) 2 3B dan B 9, 25 and 41, 57
2 (10) 4 5B dan B 10, 26 and 42, 58
3 (11) 6 7B dan B 11, 27 and 43, 59
0 (00) 0 1B dan B 12, 28 and 44, 60
1 (01) 2 3B dan B 13, 29 and 45, 61
2 (10) 4 5B dan B 14, 30 and 46, 62
3 (11) 6 7B dan B 15, 31 and 47, 63

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The addressing and mapping scheme are as followed :

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d. 4-block Sector cache
64 memory’s blocks are divided into 16 sectors which each sector contains 4 blocks.
8 cache’s block frames are divided into 2 sectors which each sector contains 4 block
frames.
Block field = 4 bits to cover 16 sectors of the main memory.
Tag field = 3 bits which is divided into 2 functions, selection bit and sector bit.
Sector Number
(1 bit)
Block Frame
Number
Sector Number
MemoryBlock
Number
0 0 3B dan B
1 4 7B dan B
0,1,.......,15 0 1 63, ,...........,B B B
0 0 3B dan B
1 4 7B dan B
0,1,.......,15 0 1 63, ,...........,B B B
The addressing and mapping scheme are as followed :

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This 4-block sector mapping scheme allows each memory’s sector placed in any of the
available cache’s block frames in fully associative mode.

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Problem 5.9 – Consider a cache ( )1M and memory ( )2M hierarchy with the following
characteristics :
1 :M 16 Kwords, 50 ns access time.
2 :M 1 Mwords, 400 ns access time.
Assume eight-word cache blocks and a set size of 256 words with set-associative mapping.
a. Show the mapping between 2M and 1M .
b. Calculate the effective memory access time with a cache hit ratio of 0.95h = .
Answers :
a. Mapping between 2M and 1M . From the above statement we collect some
information such that :
1 block = 8 word 3
2 3b w→ = ↔ = .
16 Kwords cache 14
2m m= ↔ = words = 14 3 11
2 2−
= block frames or
2,048 block frames starting from 0 2,047B B− . So that 11r = bits.
1 Mwords memory 20
2n n= ↔ = words = 20 3 17
2 2−
= memory blocks or
131,072 blocks starting from 0 131,071B B− . So that 17s = bits.
Set size, 8
256 2k = = words or 8 3 5
2 2k −
= = blocks. There will be 32-way
associativity. Then, number of sets,
11
6
5
2
2
2
m
v
k
= = = or 64 sets starting from
0 63S S− . Hence, each set will consist of 32 block frames. The bit set number,
2log 6d v= = bits.
Word field = 3 bits.
Set field = 6 bits to cover 64 sets of the cache memory.
Tag field = 17 6 11s d− = − = bits.

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Mapping Table
Set Number
(6 bits)
Block Frame Number Memory Block Number
(32-way associativity)
0 (000000) 0 1 32, ,.......,B B B
0, 64, 128, ……, 131008
1 (000001) 33 34 63, ,.......,B B B 1, 65, 129, ……, 131009
2 (000010) 64 65 95, ,.......,B B B 2, 66, 130, ……, 131010
3 (000011) 96 65 127, ,.......,B B B 3, 67, 131, ……, 131011
………….. …………. ……………….
36 (100100) 1152 65 1183, ,.......,B B B 36, 100, 167, ……, 131047
………….. …………. ……………….
63 (111111) 2016 65 2047, ,.......,B B B 63, 127, 191, ……, 131071

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The mapping scheme is as followed :

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b. The effective memory-access time can be derived as followed :
The general formula for effective memory-access time is :
1
.
n
eff i i
i
T f t
=
= ∑ where n is th
n -memory hierarchy.
Because ( )( ) ( )1 2 11 1 ........ 1i i if h h h h−= − − − , the above formula can be rewritten as
( ) ( ) ( )1 1 1 2 2 1 2 2 11 ............ 1 ....... 1eff n nT h t h h t h h t h t−= + − + + − −
What we’ve got are :
Cache ( )1M access time, 1 50t = ns
Memory ( )2M access time, 2 400t = ns
Cache hit ratio, 1 0.95h = and the access to the outermost memory, 2M , is always
hit or 2 1h =
So, the effective memory-access time is :
( )
( )( ) ( )( )( )
1 1 1 2 21
0.95 50 1 0.95 1 400
47.5 20
67.5
effT h t h h t
ns
= + −
= + −
= +
=