3. The 8 bit CPU with Registers A and B
Internal ROM 4KB
16-bit program counter(PC) and data pointer(DPTR)
Internal RAM of 128 bytes
8-bit Program Status word(PSW)
Two 16 bit Counter / timers
4 eight-bit ports
3 internal interrupts and 2 external interrupts.
Control register
Oscillator and clock circuits.
4. DPTR- Data Pointer register.
DPH,DPL- program counter higher and
lower bytes
PSEN- program store enable
5. CPU REGISTERS:
- ACC : Accumulator.
- B : B register.
- PSW : Program Status Word.
- SP : Stack Pointer.
- DPTR : Data Pointer (DPH, DPL).
INTERRUPT CONTROL:
- IE : Interrupt Enable.
- IP : Interrupt Priority.
I/O PORTS:
- P0 : Port 0.
- P1 : Port 1.
- P2 : Port 2.
- P3 : Port 3.
6. TIMERS:
- TMOD : Timer mode.
- TCON : Timer control.
- TH0 : Timer 0 high byte.
- TL0 : Timer 0 low byte.
- TH1 : Timer 1 high byte.
- TL1 : Timer 1 low byte.
SERIAL I/O:
- SCON : Serial port control.
- SBUF : Serial data registers.
OTHER:
PCON : Power control
FOUR 8-BIT I/O PORTS.
Port 0
Port 1
Port 2
Port 3
- MOST HAVE ALTERNATE FUNCTIONS.
- QUASI-BIDIRECTIONAL:
7. The 8051 contains 34 general purpose or
working registers. Two of these Register A and B.
The immediate result is stored in the
accumulator register (Acc) for next operation.
The B register is a register just for multiplication
and division operation which requires more
register spaces for the product of multiplication
and the quotient and the remainder for the
division.
8. The PSW contain the math flags, User program flag F0,and the register
select bits that identify which of the four General-purpose register banks is
currently in use by the program.
The math flags include carry(c),auxiliary carry(AC),overflow(OV) and parity(p)
9.
10. The 8051 requires an external oscillator circuit. The oscillator circuit usually runs around 12MHz. The
crystal generates 12M pulses in one second.
A machine cycle is minimum amount time must take by simplest machine instruction
An 8051 machine cycle consists of 12 crystal pulses (clock cycle).
The first 6 crystal pulses (clock cycle) is used to fetch the Opcode and the second 6 pulses are used to
perform the operation on the operands in the ALU.
This gives an effective machine cycle rate at 1MIPS (Million Instructions Per second). The program counter
points to the address of the next instruction to be Executed
As the CPU fetches the opcode from the program ROM,the program counter is increasing to point to the
next instruction.
The program counter is 16 bits wide
This means that it can access program addresses 0000 to FFFFH, a total of 64K bytes of code
11. The data pointer is 16 bit register.
It is used to hold the address of the data in the memory.
The DPTR register can be accessed separately as lower
eight bit(DPL) and higher eight bit (DPH).
It can be used as a 16 bit data register or two
independent data register.
The stack is a section of RAM used by the CPU to store
information temporarily
This information could be data or an address
‰ The register used to access the stack is called the SP
(stack pointer) register
The stack pointer in the 8051 is only 8 bit wide.
12.
13. Pins 1 – 8 (PORT 1):
Pins 1 to 8 are the PORT 1 Pins of 8051. PORT 1 Pins consists of 8 – bit
bidirectional Input / Output Port with internal pull – up resistors. In older 8051
Microcontrollers, PORT 1 doesn’t serve any additional purpose but just 8 – bit
I/O PORT.
In some of the newer 8051 Microcontrollers, few PORT 1 Pins have dual
functions. P1.0 and P1.1 act as Timer 2 and Timer 2 Trigger Input respectively.
P1.5, P1.6 and P1.7 act as In-System Programming Pins.
Pin 9 (RST):
Pin 9 is the Reset Input Pin. It is an active HIGH Pin i.e. if the RST Pin is HIGH
for a minimum of two machine cycles, the microcontroller will be reset. During
this time, the oscillator must be running.
Pins 10 – 17 (PORT 3):
Pins 10 to 17 form the PORT 3 pins of the 8051 Microcontroller. PORT 3 also
acts as a bidirectional Input / Output PORT with internal pull-ups. Additionally,
all the PORT 3 Pins have special functions. The following table gives the
details of the additional functions of PORT 3 Pins.
15. Pins 18 & 19: Pins 18 and 19 i.e. XTAL 2 and XTAL 1 are the pins for connecting external
oscillator. Generally, a Quartz Crystal Oscillator is connected here.
Pin 20 (GND):
Pin 20 is the Ground Pin of the 8051 Microcontroller. It represents 0V and is
connected to the negative terminal (0V) of the Power Supply.
Pins 21 – 28 (PORT 2):
These are the PORT 2 Pins of the 8051 Microcontroller. PORT 2 is also a Bidirectional Port i.e.
all the PORT 2 pins act as Input or Output. Additionally, when external memory is interfaced,
PORT 2 pins act as the higher order address byte. PORT 2 Pins have internal pull-ups.
Pin 29 (PSEN):
Pin 29 is the Program Store Enable Pin (PSEN). Using this pins, external Program Memory can
be read.
Pin 30 (ALE/PROG): Pin 30 is the Address Latch Enable Pin. Using this Pins, external
address can be separated from data (as they are multiplexed by 8051).During Flash
Programming, this pin acts as program pulse input (PROG).
16. Pin 31 (EA/VPP):
Pin 31 is the External Access Enable Pin i.e. allows external Program
Memory. Code from external program memory can be fetched only if
this pin is LOW. For normal operations, this pins is pulled HIGH.
During Flash Programming, this Pin receives 12V Programming
Enable Voltage (VPP).
Pins 32 – 39 (PORT 0):
Pins 32 to 39 are PORT 0 Pins. They are also bidirectional Input /
Output Pins but without any internal pull-ups. Hence, we need external
pull-ups in order to use PORT 0 pins as I/O PORT.
In addition to acting as I/O PORT, PORT 0 also acts as lower order
address/data bus when external memory is accessed.
Pin 40 (VCC):
Pin 40 is the power supply pin to which the supply voltage is given
(+5V).
17.
18. Pins 40 (VCC ) and 20 and (GND) are connected to +5V and GND respectively.
A logic HIGH (+5V) on Reset Pin for a minimum of two machine cycles (24 clock
cycles) will reset the 8051 Microcontroller
The reset circuit of the 8051 Microcontroller consists of a capacitor, a resistor and a
push button and this type of reset circuit provides a Manual Reset Option. If you
remove the push button, then the reset circuit becomes a Power-On Reset Circuit.
A Quartz Crystal Oscillator is connected across XTAL1 and XTAL2 pins i.e. Pins 19
and 18. The capacitors C1 and C2 can be selected in the range of 20pF to 40pF.
PORTS 1, 2 and 3, all have internal pull – ups and hence can be directly used as
Bidirectional I/O Ports
a 1KΩ Resistor Pack of 8 Resistors is used as a Pull – up for the PORT
19. The 8051 microcontroller's memory is divided into Program Memory and
Data Memory. Program Memory (ROM) is used for permanent saving
program being executed, while Data Memory (RAM) is used for temporarily
storing and keeping intermediate results and variables.
Program Memory (ROM)
Program Memory (ROM) is used for permanent saving program (CODE) being
executed. The memory is read only. Depending on the settings made in
compiler, program memory may also used to store a constant variables. The
8051 executes programs stored in program memory only. code memory
type specifier is used to refer to program memory.
8051 memory organization alows external program memory to be
added.
How does the microcontroller handle external memory depends on the
pin EA logical state.
20.
21.
22.
23.
24. External Data Memory
Access to external memory is slower than access to internal data memory. There
may be up to 64K Bytes of external data memory.
Several 8051 devices provide on-chip XRAM space that is accessed with the same
instructions as the traditional external data space
XRAM space is typically enabled via proper setting of SFR register and overlaps the
external memory space
Setting of that register must be manualy done in code, before any access to external
memory or XRAM space is made
SFR MeMoRy
The 8051 provides 128 bytes of memory for Special Function Registers
(SFRs)
25.
26.
27.
28.
29.
30. TIMER1 registers is also a 16 bits register and is split into two bytes, referred to
as TL1 and TH1.
31. TMOD (timer mode) Register:
This is an 8-bit register which is used by both timers 0 and 1 to set the
various timer modes. In this TMOD register, lower 4 bits are set aside for timer0
and the upper 4 bits are set aside for timer1. In each case, the lower 2 bits are
used to set the timer mode and upper 2 bits to specify the operation.
32. In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means
of starting and stopping. Some timers do this by software, some by
hardware, and some have both software and hardware controls. The
hardware way of starting and stopping the timer by an external source is
achieved by making GATE=1 in the TMOD register. And if we change to
GATE=0 then we do no need external hardware to start and stop the
timers.
The second bit is C/T bit and is used to decide whether a timer is used
as a time delay generator or an event counter. If this bit is 0 then it is used
as a timer and if it is 1 then it is used as a counter. In upper or lower 4
bits, the last bits third and fourth are known as M1 and M0 respectively.
These are used to select the timer mode.
33. M0 M1 Mode Operating Mode 0 0 0 13-bit timer mode, 8-bit timer/counter
THx and TLx as 5-bit prescalar.
0 1 1 16-bit timer mode, 16-bit timer/counters THx and TLx are cascaded;
There are no prescalar.
1 0 2 8-bit auto reload mode, 8-bit auto reload timer/counter; THx holds a
value which is to be reloaded into TLx each time it overflows. 1 1 3 Spilt
timer mode.
MODE0
Mode 0 is exactly same like mode 1 except that it is a 13-bit timer
instead of 16-bit. The 13- bit counter can hold values between 0000 to
1FFFH in TH-TL. Therefore, when the timer reaches its maximum of 1FFH,
it rolls over to 0000, and TF is raised.
34. MODE 1
IT IS A 16-BIT TIMER; therefore it allows values from 0000 to FFFFH to be
loaded into the timer’s registers TL and TH. After TH and TL are loaded with
a 16-bit initial value, the timer must be started.
“SETB TR0” for timer 0 and “SETB TR1” for timer 1. After the timer is
started. It starts count up until it reaches its limit of FFFFH. When it rolls over
from FFFF to 0000H, it sets high a flag bit called TF (timer flag). This timer
flag can be monitored.
When this timer flag is raised, one option would be stop the timer with
the instructions “CLR TR0“ or CLR TR1 for timer 0 and timer 1 respectively.
Again, it must be noted that each timer flag TF0 for timer 0 and TF1 for
timer1.
After the timer reaches its limit and rolls over, in order to repeat the
process the registers TH and TL must be reloaded with the original value and
TF must be reset to 0.
35. Mode 2
It is an 8 bit timer that allows only values of 00 to FFH to be loaded into the
timer’s register TH. After TH is loaded with 8 bit value, the 8051 gives a copy of it
to TL.
Then the timer must be started. It is done by the instruction “SETB TR0” for
timer 0 and “SETB TR1” for timer1. This is like mode 1. After timer is started, it
starts to count up by incrementing the TL register. It counts up until it reaches its
limit of FFH. When it rolls over from FFH to 00. It sets high the TF (timer flag).
If we are using timer 0, TF0 goes high; if using TF1 then TF1 is raised.
When Tl register rolls from FFH to 00 and TF is set to 1, TL is reloaded
automatically with the original value kept by the TH register. To repeat the
process, we must simply clear TF and let it go without any need by the
programmer to reload the original value.
This makes mode 2 auto reload, in contrast in mode 1 in which programmer
has to reload TH and TL.
36. MODE3
• Mode 3 is also known as a split timer mode. Timer 0 and 1 may be
programmed to be in mode 0, 1 and 2 independently of similar mode for
other timer.
• This is not true for mode 3; timers do not operate independently if
mode 3 is chosen for timer 0. Placing timer 1 in mode 3 causes it to stop
counting; the control bit TR1 and the timer 1 flag TF1 are then used by
timer0.
37.
38.
39. 7 TF1 Timer1 over flow flag. Set when timer rolls from all 1s to
0. Cleared When the processor vectors to execute
interrupt service routine Located at program address
001Bh.
6 TR1 Timer 1 run control bit. Set to 1 by programmer to
enable timer to count; Cleared to 0 by program to halt
timer.
5 TF0 Timer 0 over flow flag. Same as TF1.
4 TR0 Timer 0 run control bit. Same as TR1.
3 IE1 External interrupt 1 Edge flag. Not related to timer
operations.
2 IT1 External interrupt1 signal type control bit. Set to 1 by
program to Enable external interrupt 1 to be triggered
by a falling edge signal. Set To 0 by program to enable
a low level signal on external interrupt1 to generate an
interrupt
1 IE0 External interrupt 0 Edge flag. Not related to timer
operations
0 IT0 External interrupt 0 signal type control bit. Same as IT0.
40. Serial Interface SI program classified
(1) SIMPLEX
(2) HALF DUPLEX SYNCHRONOUS SERIAL
(3) FULL DUPLEX ASYNCHRONOUS UART MODE
(1) SBUF (8 serial received bits or transmission bits register depending upon
instruction is using SBUF as source or destination)
(2) (a) SCON (8-serial modes cum control bits register) (b) PCON both are SFR
The serial port of 8051 is full duplex it can transmit and receive simultaneously.
The register SBUF is used to hold the data. The special function register SBUF is
physically two registers. One is, write-only and is used to hold data to be transmitted
out of the 8051 via (a)TXD. The other is, read-only and holds the received data from
external sources via (b)RXD.
Both mutually exclusive registers have the same address 099H.
41.
42. Register SCON controls serial data communication.
Address: 098H (Bit addressable)
43. SM2: multi processor communication bit
REN: Receive enable bit
TB8: Transmitted bit 8 (Normally we have 0-7 bits transmitted/received)
RB8: Received bit 8
TI: Transmit interrupt flag
RI: Receive interrupt flag
Power Mode control Register (PCON)
Register PCON controls processor power down, sleep modes and serial data
band rate. Only one bit of PCON is used with respect to serial communication. The
seventh bit (b7)(SMOD) is used to generate the baud rate of serial communication.
Address: 87H
SMOD: Serial baud rate modify bit
GF1: General purpose user flag bit 1
GF0: General purpose user flag bit 0
PD: Power down bit
IDL: Idle mode bit
44. Data Transmission
Transmission of serial data begins at any time when data is written to SBUF. Pin
P3.1 (Alternate function bit TXD) is used to transmit data to the serial data network.
TI is set to 1 when data has been transmitted. This signifies that SBUF is empty so
that another byte can be sent.
Data Reception
Reception of serial data begins if the receive enable bit is set to 1 for all modes.
Pin P3.0 (Alternate function bit RXD) is used to receive data from the serial data
network. Receive interrupt flag, RI, is set after the data has been received in all
modes. The data gets stored in SBUF register from where it can be read.
Serial Data Transmission Modes:
Mode-0
In this mode, the serial port works like a shift register and the data
Transmission works synchronously with a clock frequency of fosc /12. Serial data
is received and transmitted through RXD. 8 bits are transmitted/ received at a
time.
Pin TXD outputs the shift clock pulses of frequency fosc /12, which is connected
to the external circuitry for synchronization. The shift frequency or baud rate is
always 1/12 of the oscillator frequency.
45. Mode-1
(standard UART mode)
In mode-1, the serial port functions as a standard Universal Asynchronous
Receiver Transmitter (UART) mode. 10 bits are transmitted through TXD or
received through RXD. The 10 bits consist of one start bit (which is usually '0'), 8
data bits (LSB is sent first/received first), and a stop bit (which is usually '1'). Once
received, the stop bit goes into RB8 in the special function register SCON. The
baud rate is variable.
The following figure shows the way the bits are transmitted/ received.
46. Bit time= 1/fbaud
In receiving mode, data bits are shifted into the receiver at the programmed baud
rate. The data word (8-bits) will be loaded to SBUF if the following conditions are
true.
1. RI must be zero. (i.e., the previously received byte has been cleared from SBUF)
2. Mode bit SM2 = 0 or stop bit = 1.
After the data is received and the data byte has been loaded into SBUF, RI
becomes one.
Mode-1
baud rate generation
Timer-1 is used to generate baud rate for mode-1 serial communication by using
overflow flag of the timer to determine the baud frequency. Timer-1 is used in timer
mode-2 as an auto-reload 8-bit timer. The data rate is generated by timer-1 using
the following formula.
47. SMOD is the 7th
bit of PCON register
fosc is the crystal oscillator frequency of the microcontroller It can be noted that fosc/
(12 X [256- (TH1)]) is the timer overflow frequency in timer mode-2, which is the
auto-reload mode.If timer-1 is not run in mode-2, then the baud rate is,
Timer-1 can be run using the internal clock, fosc/12 (timer mode) or from any
external source via pin T1 (P3.5) (Counter mode).
48.
49.
50.
51.
52.
53.
54. Interrupts are the events that temporarily suspend the main program, pass the
control to the external sources and execute their task. It then passes the
control to the main program where it had left off.
8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt
can be enabled or disabled by setting bits of the IE register and the whole
interrupt system can be disabled by clearing the EA bit of the same register.
Microcontrollers - 8051 Interrupts. ... 8051 has 5 interrupt signals, i.e.
INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled or disabled
by setting bits of the IE register and the whole interrupt system can be
disabled by clearing the EA bit of the same register.
• Timer 0 overflow interrupt- TF0
• Timer 1 overflow interrupt- TF1
• External hardware interrupt- INT0
• External hardware interrupt- INT1
• Serial communication interrupt- RI/TI
55.
56. This register is responsible for enabling and disabling the interrupt. EA register
is set to one for enabling interrupts and set to 0 for disabling the interrupts. Its bit
sequence and their meanings are shown in the following figure.
EA IE.7 It disables all interrupts. When EA = 0 no
interrupt will be acknowledged and EA = 1
enables the interrupt individually.
- IE.6 Reserved for future use.
- IE.5 Reserved for future use.
ES IE.4 Enables/disables serial port interrupt.
ET1 IE.3 Enables/disables timer1 overflow interrupt.
EX1 IE.2 Enables/disables external interrupt1.
ET0 IE.1 Enables/disables timer0 overflow interrupt.
EX0 IE.0 Enables/disables external
57. We can change the priority levels of the interrupts by changing the
corresponding bit in the Interrupt Priority (IP) register as shown in the following
figure. A low priority interrupt can only be interrupted by the high priority
interrupt, but not interrupted by another low priority interrupt.
If two interrupts of different priority levels are received simultaneously, the
request of higher priority level is served.
If the requests of the same priority levels are received simultaneously, then the
internal polling sequence determines which request is to be serviced.
58. Each interrupt source can be programmed to have one of the two priority
levels by setting (high priority) or clearing (low priority) a bit in the IP (Interrupt
Priority) Register
A low priority interrupt can itself be interrupted by a high priority interrupt,
but not by another low priority interrupt. If two interrupts of different priority
levels are received simultaneously, the request of higher priority level is
served.
If the requests of the same priority level are received simultaneously, an
internal polling sequence determines which request is to be serviced. Thus,
within each priority level, there is a second priority level determined by the
polling sequence, as follows.
59. •The external interrupts are the interrupts received from the (external) devices
interfaced with the microcontroller.
• They are received at INT x pins of the controller. The 8051 has two external
hardware interrupts PIN 12 (P3.2) and Pin 13 (P3.3) of the 8051, designated as
INT0 and INT1 are used as external hardware interrupts. Upon activation of these
pins, the 8051 gets interrupts in what ever it is doing and jumps to the vector table
to perform the interrupt service routine.
•Type of Interrupt
1)Level-TriggereInterrupt
2)Edge-TriggeredInterrupt
60. LEVEL-TRIGGERED
INTERRUPT
EDGE -TRIGGERED INTERRUPT
this mode, INT0 and INT1
are normally high and if the
low level signal is applied to
them
the microcontroller stops and
jumps to the interrupt vector
table to service that interrupt
.
8051 makes INT0 and INT1 is when
applied low l Level-Triggered
Interrupt.
When Edge -Triggered Interrupt
applied, we must program the bits of
the TCON Register.
The TCON register holds among
other bits and IT0 and IT1 flags bit
the determine level- or edge
triggered mode Of the hardware
interrupt.
61.
62. •TR1=0 mean, to stop timer 1 .
•TR1=1 mean, to start timer 1.
•TR0=0 mean, to start timer 0.
•TR0=1 mean, to start timer 0.
•TF1=1 mean overflow condition occur in Timer 1.
•TF1=0 mean Timer 1 is in running condition.
•TF0=1 mean overflow condition occur in Timer 0.
•TF0=0 mean Timer 0 is in running condition.
•IT1=1 mean interrupt trigger is negative edge
sensitive.
•IT1=0 mean interrupt trigger is positive edge
sensitive.
•IT0=1 mean interrupt trigger is negative edge
sensitive.
•IT0=0 mean interrupt trigger is positive edge
sensitive.
•IE1=1 mean interrupt enable Timer 1.
•IE1=0 mean interrupt enable Timer 1.
•IE0=1 mean interrupt enable Timer 0.
•IE0=0 mean interrupt enable Timer 0.
65. Addressing Modes Instruction
Register MOV A, B
Direct MOV 30H,A
Indirect ADD A,@R0
Immediate Constant ADD A,#80H
Relative* SJMP AHEAD
Absolute* AJMP BACK
Long* LJMP FAR_AHEAD
Indexed MOVC A,@A+PC
66. 1. Immediate addressing mode:
Ex: MOV A,#05H - Where MOV stands for move, # represents
immediate data. 05h is the data. It means the immediate date 05h
provided in instruction is moved into A register.
2.Register addressing mode:
Here the operand in contained in the specific register of microcontroller.
The user must provide the name of register from where the operand/data
need to be fetched. The permitted registers are A, R7-R0 of each register
bank.
Ex: MOV A,R0- content of R0 register is copied into Accumulator.
3. Direct addressing mode:
In this mode the direct address of memory location is provided in
instruction to fetch the operand. Only internal RAM and SFR's address
can be used in this type of instruction.
Ex: MOV A, 30H = Content of RAM address 30H is copied into
Accumulator.
67. 4. Register Indirect addressing mode:
Here the address of memory location is indirectly provided by a register.
The '@' sign indicates that the register holds the address of memory
location i.e. fetch the content of memory location whose address is
provided in register.
Ex: MOV A,@R0 = Copy the content of memory location whose address
is given in R0 register.
5. Indexed Addressing mode:
This addressing mode is basically used for accessing data from look up
table. Here the address of memory is indexed i.e. added to form the
actual address of memory.
Ex: MOVC A,@A+DPTR = here 'C' means Code. Here the content of A
register is added with content of DPTR and the resultant is the address of
memory location from where the data is copied to A register.
68.
69.
70. 8051 has about 111 instructions. These can be grouped into the following categories
1.Arithmetic Instructions
2.Logical Instructions
3.Data Transfer instructions
4.Boolean Variable Instructions
5.Program Branching Instructions
The following nomenclatures for register, data, address and variables are
used while write instructions.
A: Accumulator
B: B register
C: Carry bit
Rn: Register R0 - R7 of the currently selected register bank
71. Direct: 8-bit internal direct address for data. The data could be in lower 128bytes
of RAM (00 - 7FH) or it could be in the special function register (80 - FFH).
@Ri: 8-bit external or internal RAM address available in register R0 or R1. This
is used for indirect addressing mode.
#data8: Immediate 8-bit data available in the instruction.
#data16: Immediate 16-bit data available in the instruction.
Addr11: 11-bit destination address for short absolute jump. Used by instructions
AJMP ACALL. Jump range is 2 kbyte (one page).
Addr16: 16-bit destination address for long call or long jump.
Rel: 2's complement 8-bit offset (one - byte) used for short jump (SJMP) and all
conditional jumps.
bit: Directly addressed bit in internal RAM or SFR
72. Mnemonics Description Bytes Instruction
Cycles
ADD A, Rn A A + Rn 1 1
ADD A, direct A A + (direct) 2 1
ADD A, @Ri A A + @Ri 1 1
ADD A, #data A A + data 2 1
ADDC A, Rn A A + Rn + C 1 1
ADDC A, direct A A + (direct) + C 2 1
ADDC A, @Ri A A + @Ri + C 1 1
ADDC A, #data A A + data + C 2 1
DA A Decimal adjust
accumulator
1 1
DIV AB Divide A by B
A quotient
B remainder
1 4
73. DEC A A A -1 1 1
DEC RN RN RN - 1 1 1
DEC DIRECT (DIRECT) (DIRECT) - 1 2 1
DEC @RI @RI @RI - 1 1 1
INC A A A+1 1 1
INC RN RN RN + 1 1 1
INC DIRECT (DIRECT) (DIRECT) + 1 2 1
INC @RI @RI @RI +1 1 1
INC DPTR DPTR DPTR +1 1 2
MUL AB MULTIPLY A BY B
A LOW BYTE (A*B)
B HIGH BYTE (A* B) 1 4
SUBB A, RN A A - RN - C 1 1
SUBB A, DIRECT A A - (DIRECT) - C 2 1
SUBB A, @RI A A - @RI - C 1 1
SUBB A, #DATA A A - DATA - C 2 1
74. Mnemonics Description Bytes Instruction Cycles
ANL A, Rn A A AND Rn 1 1
ANL A, direct A A AND (direct) 2 1
ANL A, @Ri A A AND @Ri 1 1
ANL A, #data A A AND data 2 1
ANL direct, A (direct) (direct) AND A 2 1
ANL direct, #data (direct) (direct) AND data 3 2
CLR A A 00H 1 1
CPL A AA 1 1
ORL A, Rn A A OR Rn 1 1
ORL A, direct A A OR (direct) 1 1
ORL A, @Ri A A OR @Ri 2 1
ORL A, #data A A OR data 1 1
ORL direct, A (direct) (direct) OR A 2 1
ORL direct, #data (direct) (direct) OR data 3 2
75. RL A Rotate accumulator left 1 1
RLC A Rotate accumulator left
through carry
1 1
RR A Rotate accumulator right 1 1
RRC A Rotate accumulator right
through carry
1 1
SWAP A Swap nibbles within
Acumulator
1 1
XRL A, Rn A A EXOR Rn 1 1
XRL A, direct A A EXOR (direct) 1 1
XRL A, @Ri A A EXOR @Ri 2 1
XRL A, #data A A EXOR data 1 1
XRL direct, A (direct) (direct) EXOR A 2 1
XRL direct, #data (direct) (direct) EXOR data 3 2
76. Mnemonics Description Bytes Instruction Cycles
MOV A, Rn A Rn 1 1
MOV A, direct A (direct) 2 1
MOV A, @Ri A @Ri 1 1
MOV A, #data A data 2 1
MOV Rn, A Rn A 1 1
MOV Rn, direct Rn (direct) 2 2
MOV Rn, #data Rn data 2 1
MOV direct, A (direct) A 2 1
MOV direct, Rn (direct) Rn 2 2
MOV direct1, direct2 (direct1) (direct2) 3 2
MOV direct, @Ri (direct) @Ri 2 2
MOV direct, #data (direct) #data 3 2
MOV @Ri, A @Ri A 1 1
MOV @Ri, direct @Ri (direct) 2 2
77. MOV @Ri, #data @Ri data 2 1
MOV DPTR, #data16 DPTR data16 3 2
MOVC A, @A+DPTR A Code byte pointed by A + DPTR 1 2
MOVC A, @A+PC A Code byte pointed by A + PC 1 2
MOVC A, @Ri A Code byte pointed by Ri 8-bit address) 1 2
MOVX A, @DPTR A External data pointed by DPTR 1 2
MOVX @Ri, A @Ri A (External data - 8bit address) 1 2
MOVX @DPTR, A @DPTR A(External data - 16bit address) 1 2
PUSH direct (SP) (direct) 2 2
POP direct (direct) (SP) 2 2
XCH Rn Exchange A with Rn 1 1
XCH direct Exchange A with direct byte 2 1
XCH @Ri Exchange A with indirect RAM 1 1
XCHD A, @Ri Exchange least significant nibble of A with that of indirect RAM 1 1
78. Mnemonics Description Bytes Instruction Cycles
CLR C C-bit 0 1 1
CLR bit bit 0 2 1
SET C C 1 1 1
SET bit bit 1 2 1
CPL C C 1 1
CPL bit bit 2 1
ANL C, /bit C C . 2 1
ANL C, bit C C. bit 2 1
ORL C, /bit C C + 2 1
ORL C, bit C C + bit 2 1
MOV C, bit C bit 2 1
MOV bit, C bit C 2 2
79. Mnemonics Description Bytes Instruction
Cycles
ACALL addr11 PC + 2 (SP) ; addr 11 PC 2 2
AJMP addr11 Addr11 PC 2 2
CJNE A, direct, rel Compare with A, jump (PC + rel) if not equal 3 2
CJNE A, #data, rel Compare with A, jump (PC + rel) if not equal 3 2
CJNE Rn, #data, rel Compare with Rn, jump (PC + rel) if not
equal
3 2
CJNE @Ri, #data, rel Compare with @Ri A, jump (PC + rel) if not
equal
3 2
DJNZ Rn, rel Decrement Rn, jump if not zero 2 2
DJNZ direct, rel Decrement (direct), jump if not zero 3 2
JC rel Jump (PC + rel) if C bit = 1 2 2
JNC rel Jump (PC + rel) if C bit = 0 2 2
80. JB bit, rel Jump (PC + rel) if bit = 1 3 2
JNB bit, rel Jump (PC + rel) if bit = 0 3 2
JBC bit, rel Jump (PC + rel) if bit = 1 3 2
JMP @A+DPTR A+DPTR PC 1 2
JZ rel If A=0, jump to PC + rel 2 2
JNZ rel If A ≠ 0 , jump to PC + rel 2 2
LCALL addr16 PC + 3 (SP), addr16 PC 3 2
LJMP addr 16 Addr16 PC 3 2
NOP No operation 1 1
RET (SP) PC 1 2
RETI (SP) PC, Enable Interrupt 1 2
SJMP rel PC + 2 + rel PC 2 2
JMP @A+DPTR A+DPTR PC 1 2
JZ rel If A = 0. jump PC+ rel 2 2
JNZ rel If A ≠ 0, jump PC + rel 2 2
NOP No operation 1 1
81. 16 BIT ADDITION
1 a s s u m e c s : c o d e ,d s : d a t a
2
3 0000 data segment
4 0000 1243 n1 dw 1243h
5 0002 4567 n2 dw 4567h
6 0004 ???? n3 dw ?
7 0006 data ends
8
9 0000 code segment
1 0
1 1 0000 start:
1 2 0000 B8 0000s mov ax,data
1 3 0003 8E D8 mov ds,ax
1 4
1 5 0005 A1 0000r mov ax,n1
1 6 0008 8B 1E 0002r mov bx,n2
1 7 000C 03 C3 add ax,bx
1 8 000E A3 0004r mov n3,ax
1 9 0011 BE 0004r lea si,n3
2 0 0014 CC int 3
2 1
2 2 0015 code ends
2 3 end start
82. 1 a s s u m e c s :c o d e ,d s :d a ta
2
3 0000 data segment
4 0000 FFFF n1 dw 0ffffh
5 0002 4567 n2 dw 4567h
6 0004 ???? n3 dw ?
7 0006 data ends
8
9 0000 code segment
1 0
1 1 0000 start:
1 2 0000 B8 0000s mov ax,data
1 3 0003 8E D8 mov ds,ax
1 4
1 5 0005 A1 0000r mov ax,n1
1 6 0008 8B 1E 0002r mov bx,n2
1 7 000C 2B C3 sub ax,bx
1 8 000E A3 0004r mov n3,ax
1 9 0011 BE 0004r lea si,n3
2 0 0014 CC int 3
2 1
2 2 0015 code ends
2 3 end start
83. 16 BIT MULTIPLICATION
1 a s s u m e c s : c o d e ,d s : d a t a
2
3 0000 data segment
4 0000 4444 n1 dw 4444h
5 0002 4567 n2 dw 4567h
6 0004 ???????? n3 dd ?
7 0008 data ends
8
9 0000 code segment
1 0
1 1 0000 start:
1 2 0000 B8 0000s mov ax,data
1 3 0003 8E D8 mov ds,ax
1 4
1 5 0005 A1 0000r mov ax,n1
1 6 0008 8B 1E 0002r mov bx,n2
1 7 000C F7 E3 mul bx
1 8 000E BE 0004r lea si,n3
1 9 0011 89 04 mov [si],ax
2 0 0013 89 54 02 mov [si+2],dx
2 1
2 2 0016 CC int 3
2 3
24 0017 code ends
25 end start
84. 16 BIT ADDITION
1 a s s u m e c s : c o d e ,d s : d a t a
2
3 0000 data segment
4 0000 0444 n1 dw 0444h
5 0002 4545 n2 dw 4545h
6 0004 ???? n3 dw ?
7 0006 data ends
8
9 0000 code segment
1 0
1 1 0000 start:
1 2 0000 B8 0000s mov ax,data
1 3 0003 8E D8 mov ds,ax
1 4
1 5 0005 BE 0000r lea si,n1
1 6 0008 BF 0002r lea di,n2
1 7 000B 8B 04 mov ax,[si]
1 8 000D 8B 1D mov bx,[di]
1 9 000F 03 C3 add ax,bx
2 0
2 1 0011 BD 0004r lea bp,n3
2 2 0014 89 46 00 mov [bp],ax
2 3
2 4
2 5
2 6 0017 CC int 3
2 7
2 8 0018 code ends
2 9 end start
85. 16 BIT SUBTRACTION
1 a s s u m e c s : c o d e ,d s : d a t a
2
3 0000 data segment
4 0000 AAAA n1 dw 0aaaah
5 0002 4545 n2 dw 4545h
6 0004 ???? n3 dw ?
7 0006 data ends
8
9 0000 code segment
1 0
1 1 0000 start:
1 2 0000 B8 0000s mov ax,data
1 3 0003 8E D8 mov ds,ax
1 4
1 5 0005 BE 0000r lea si,n1
1 6 0008 BF 0002r lea di,n2
1 7 000B 8B 04 mov ax,[si]
1 8 000D 8B 1D mov bx,[di]
1 9 000F 2B C3 sub ax,bx
2 0
2 1 0011 BD 0004r lea bp,n3
2 2 0014 89 46 00 mov [bp],ax
2 3
2 4
2 5
2 6 0017 CC int 3
2 7
2 8 0018 code ends
2 9 end start
