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8051 presentation


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Basic points of micro controllers

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8051 presentation

  1. 1. 8051 presentation Some basic points: It is 8bit controller Working frequency of microcontroller upto 16MHz Two types of memory in microcontroller 1)RAM 2)ROM(flash memory) Flash memory size will be less i.e 4K Small operating systems can run on microcontroller eg.RTOS is small size operating system Application to application RTOS size can change i.e 4k to 4GB
  2. 2. RAW CODING: (firmware or bare metal code) without help of O.S we can control the hardware. there are so many microcontrollers are their they were using RAW coding eg. advanced virtual risc (AVR) periferal interface controller(PIC) advanced risc machine(ARM) There are three layers in O.S USER SPACE (application space) KERNEL SPACE BOOT SUPPORT PACKAGES Purpose of flash memory is to store the program like OTP chip Designer will never give a permission to write in flash memory EEPROM it is the permanent memory R/W data in memory EEPROM is electrically erasable
  3. 3. Every microcontroller have inbuilt CPU, flash , RAM Flash memory and RAM is mandatory MICROPROCESSOR: It is the general purpose CPU without on chip memory CPU components are  ALU REGISTERS TIMERS AND CONTROL UNIT BUSES INTERRUPT CONTROL LOGIC INTRUCTION AND DECODE UNIT
  4. 4. 8085 (8BIT MICROPROCESSOR) 8bits 16bits 8086 (16BIT MICROPROCESSOR) 16bits 20bits 8051 (8BIT Microcontroller) 8bits 16bits 8088 (16BIT MICROPROCESSOR) 8bits 20bits DATA BUS ADDRESS BUS ALU: It performs the arithmetic and logical operations
  5. 5. Registers: registers are faster and local storage memory of CPU Mov Acc,data //less time Mov addr,data //more time Accumulator called as varsatile register because it is used in many Stack pointer is initialize the default values Two types of stack 1) up growing stack 2) down growing stack Stack operations: PUSH->insert elements in to the stack POP->retrieving elements from the stack For push operation stack pointer is incrementing then it is up growing stack For push operation if stack pointer is decrementing it is down growing stack In up growing stack first pop operation will retrieve the data and decrement one stack pointer
  6. 6. Eg. 8086 stack is down growing 8051 is up growing Program counter: It points to next instruction to be executed in both microcontroller and microprocessor Every instruction have different unique opcode CPU operations Fetch Decode Execute Program counter always point to zero, zero opcode reserve for NO operation Buses: Three types of buses 1)data bus 2)address bus 3)control bus Buses are group of lines which can transfer data or addresses
  7. 7. Data bus is bidirectional Address bus is unidirectional Control bus can be uni or bidirectional For every internal activity of cpu, cpu needs clock pulses and clock pulses are nothing but electrical signals i.e 0’s & 1’s Machine cycle: It is group of clock pulses The time required to fetch +decode+execute the instruction called machine cycle 1 m/c of 8051==12clock pulses
  8. 8. Instruction decoding unit: Every instruction has unique opcode If processor supports 16 instructions then it has 16 opcodes Two instructions with same opcodes not present in processor It is a part of CPU If processor supports more number of instructions then IDU size is more CPU design policies: 1)Based on instructions set 2)Based on memory organization 1)Based on instruction set: CISC complex instruction set computing RISC reduced instrucion set computing
  9. 9. CISC RISC It supports more number of instructions IDU size is big Power consumption is more Heat dissipation is more Compiler complexity is less It supports multiclock cycle instructions Supports less number of registers Eg.8051 cpu, 8085,8086 etc… It supports less number of instructions IDU size is small Power consumption is less Heat dissipation is less Compiler complexity is more Mostly single clock cycled instruction More number of registers Eg.ARM,CPU,AVR,PIC etc…
  10. 10. Based on memory organization: 1)Harvard architecture 2)Von neumann architecture Harvard architecture have separate memory for both data and program Eg.8051, ARM9, AVR,PIC etc… Von neumann architecture have single memory for both data and program
  11. 11. 8051 block diagram:
  12. 12. Features of 8051: Employs CISC Harvard architecture 8bit ALU 8bit controller 8051 available in 40pin DIP(dual in line package) 4k on chip ROM/flash memory It has 128bytes of USER RAM Another 128bytes of RAM is reserved for sfr”s Four i/o ports are available Two 16bits timers/counters peripherals are available It has full duplex UART peripheral
  13. 13.  It supports 6 interrupt sources one is non maskable interrupt five is maskable interrupt  It have on-chip clock oscillator requires external crystal It supports upto 60kb of external flash memory Address bus size-16bits(A0 to A15) data bus-8bits(D0 to D7)
  14. 14. 8051’s memory structures: Whenever we want to design microcontroller these following four mandatory circuits are there 1)Reset 2)Crystal 3)PSU 4)Circuit to download into microcontroller
  15. 15. Name Internal RAM address(HEX) A E0 B FO DPH 83 DPL 82 IE A8 IP B8 P0 80 P1 90 P2 A0 P3 B0 PCON 87 PSW D0 SCON 98 Special function registers:
  16. 16. Name Internal RAM address(HEX) SBUF 99 SP 81 TMOD 89 TCON 88 TL0 8A TL1 8B TH0 8C TH1 8D PC Not available IR Not available
  17. 17. Memory mapped i/o’s i/o mapped i/o’s From the available of memory few address are reserved for i/o’s The instructions which is used to store data into memory that same instruction can be used for i/o operation Eg.8051,ARM7 etc… Memory address are different and i/o address are different The separate instructions are available for memory operation and i/o operation Eg.8085,8086 etc…
  18. 18. Addressing modes: the addressing modes are nothing but CPU in which deals with the information 1)Immediate address mode 2)Register address mode 3)Direct address mode 4)Indirect address mode 5)Indexed address mode
  19. 19. Instructions set: PUSH and POP opcodes PUSH address POP address This PUSH & POP operations possible only in internal RAM Stack operation is indirect operation P)How to debug PUSH & POP instruction CSEG AT 0H MOV 05H,#’A’ MOV 07H,#’B’ PUSH 05H PUSH 07H POP 05H POP 07H END