A Comb Filter with Switched Capacitor Delay Lines for Analog Video Processor.

1. 17.3
P or
ShimDosho,'HidehikoKurimot0,'MasayukiOzasa,'TatsuoOkamoto,Naoshi Yanagisawaand'NobuyukiTamagawa
Matsushita Electric Industrial Co.,Ltd. 'Matsushita Electronics Corporation
3-1-1 Yagumo-Nakamachi,Moriguchi,Osaka570 Japan
Abstract
This paper describes the design and development of an analog
comb filter that uses switchedcapacitor(SC)memory circuitsfor an ana-
log video processor.The fully monolithic video processor is realized by
using the comb filter instead of the conventional CCD delay line. New
circuit techniques improve the filter performance beyond commercial-
use specifications. In particular Fixed Pattern Noise(F.P.N.) is greatly
reduced to -69.4dB which is about 14dB lower than thatof the reported
data[4]. This chip was fabricated with 0.8um Bi-CMOS technology.
introduction
The last bottleneck when attempting to integrate fully mono-
lithic analog video processor is the analog comb filter[1-41,The analog
comb filter can solve the EM1 noise issue, which is the main problem of
the conventional CCD delay line, and alsocan reduce power dissipation
and implementation cost. Fig.1 shows the block diagram of SC comb
filterwhose clockfrequency is 2fsc(7-8MHz).This SC filterhas memory
array consisting 1I36(I6 memory buses with 71 memory cells) memory
cells that can store video signal data of two horizontal lines. First, input
signal is sampled as charge. Second, this charge is transferred to the
memory cell selected by row and column selectors via bus multiplexer.
The charge has been stored during the selector has been rounded. Third,
this charge is transferredto the sample hold circuit by the read amplifier,
then subtracted from input signal which come through a write amplifier.
The transfer function of the SC comb filter is given by the following
H(z)=l-Z-1136 (2-1: one clock delay)
equation.
Thereare some differences in signal path between the SC delay
line and the CCD delay line.CCD delay linehas only one signalpath. In
contrast, the SC delay line has many signal paths equal to the number of
memory cells, because SC delay line is a kind of analog FIFO memory.
This large number of signal paths cause large scattering of gain and
offset. The gain scattering degrades the comb filter performance, also
the offset scattering increases F.P.N.on the TV screen, seiiously. F.P.N.
less than -6OdB(commercial-~sespecification) is very difficult to real-
ize by using conventional SC circuits[3-4]. Therefore, we have intro-
duced following new circuit techniques to overcome these problems.
1. Memory Bus with Dummy Capacitor.
2. Bus Precharge with Parallel Bus Access.
3. Improved Comb Filter Circuit without Additional Delay.
Circuit Description
Fig.2 showsthe schematic of the SC memory. Non-overlapped
two phase clocks @ I and 4 2 are used. During @ I , both READ op-
eration and sampling input signalare performed. Input signal is sampled
and stored as charge into input capacitor (CI).At the same time, the
read amplifier transfer the charge stored in memory cell to output ca-
pacitor (C3). During @ 2, WRITE operation are performed in parallel
with BUS-PRECHARGE operation.The write amplifier transfer the
charge stored in the input capacitor previous 4 1 clock to the memory
cell (C2) selected by row and column selectors via write bus multi-
plexer. Somepart of this charge is also transferred to parasitic capacitor
of memoiy bus lines (Cp) and dummy capacitor (Cd)which are always
ON. Both Cp and Cd provide the supeifluous signal path which disturbs
the flat frequency response of SC memory. Hence, before executing
READ operation, the charges stored in both Cp and Cd have been re-
moved by the memory bus precharge. Therefore, the degradation of
frequency characteristics of SC memory can be suppressed completely
by the bus precharge. The outputlinput gain of SC memory is given by
v,,tNi,=c,/c, x C,/(C,+C,+C,)
vo"t/vi"=l/(1+cp/5C,)
Then we choose CI=5*C2,Cd=4*C2,C3=C2.The gain is wi-itten as
The dummy capacitor reduces the influence of Cp to the gain
scattering to one fifth of the SC memory without dummy capacitor.
Reductionof Fixed Pattern Noise
In this circuit, the noise caused by the MOS switches of both
WRITE and READ bus multiplexer is unacceptable.Becausethe size of
switchesare ten times largerthan that of memorycells in order to realize
the fast settling time. Fig.3(a) shows the operation of WRITE and BUS-
PRECHARGE in SC memory. In the WRITE operation, the ratio of
206 0-7803-4766-8/98/$10.0001998 IEEE
Qn/Qin must be as small as possible to reduce the influenceof thecharge
feedthrough noise, where Qn is the charge of the noise and Qin is the
charge of input signal. Therefore, we have to increase Qin as large as
possible. During @ 2, the total capacitance of memory cell seems to be
5*C2, because the capacitance of dummy capacitor (4*C2) is added to
that of memory cell(C2).Thus, we setQin five times largerthan value of
Qin when not using dummy capacitor.The ratio Qn/Qin can be reduced
to one fifth and this resulted in large reduction of the influence of the
feedthrough noise from write bus multiplexer. Simultaneously, the bus
precharge has done in next memory bus connecting memory cell whose
charge is read during next READ operation. Sincethe memory address
scans memory bus vertically,the parallel operation can be achieved, and
it results in no reduction of settling time in READ and WRITE opera-
tions. To close the switches of read amplifier and bus multiplexer, the
charges stored in both dummy capacitor and parasiticcapacitors are dis-
charged. Also, the feedthrogh noise from read bus multiplexer is dis-
charged. Fig.3(b)shows the READ operation in SC memory.Since only
the switch of memory cell turn on to transfer the charge to the output
capacitor,the feedthrough noise from read the bus multiplexer dose not
cause F.P.N.on output signal.
Improved Comb FilterCircuit
According to conventional switched capacitor theory, the sub-
traction for comb filter must be done on the memory bus where the
memory needs two system clocks due to parallel memory bus access, as
shown in Fig.4(a). This clock delay needs adjustment of timing for all
the other functional blocks of the video processor and it causes quite
large overhead of the system design. Fig.4(b) shows a improved comb
filter circuits. The signal through line transfers the signal as voltage.
Since the signal path was provided outside of the SC memory, the im-
proved circuits need no additional delay. Moreover, the through signal
which comes through the write amplifier has the same output gain as
that of SC memory, because the output gain of the write amplifier is
affectedby Cp as well as that of SC memory. It ensures accurate subtrac-
tion of comb filter without additional delay.
ExperimentalResults
We fabricated two types of SC analog memory for analog video
processor, as shown in. Fig.5. The circuits have been designed in fully
differentialscheme. One is for luminescence signal processing with 574
memory cells (Y. delay Line) and the other is comb filter for chromi-
nance signal processing with 1136memory cells (C.Comb Filter). Fig.6
shows the output spectrum of Y.Delay Line. The measured F.P.N.is
-69.4dB, which is sufficiently low for practical use and about 14 dB
lower than that of repoited data[4]. Fig.7 shows the frequency character-
istics of C. Comb Filter. The comb notch depth is higher than 40dB
without any gain control circuits. The measured comb notch depths of
twenty C. Comb Filters is 45dB +- 2dB. Table 1 summarizes the mea-
sured performances. The harmonic distortion is IOdB lower than that of
CCD and the other performances are almost same as that of CCD.
Conclusion
A switchedcapacitorcomb filter for analog video processor has
been successfully developed. New circuit techniques(I . Memory Bus
with Dummy Capacitor 2. Bus Precharge with Parallel Bus Access) re-
duce the F.P.N.effectively and ensures noble comb filter operation. Suf-
ficiently low F.P.N.of -69.4dB, which is about 14dB lower than that of
t h e repotted data[4], and very deep comb notch about 45dB are success-
fully obtained. Thus, the last bottleneck to realize fully monolithic analog
video processorhas been successfully solved.
Acknowledgments
References
The authors would like to thank Takashi Kakimoto,Shil-o
Sakiyama and Akira Matsuzawa for their supports and suggestions.
[ I ] Wqi Vm Gurp,A-iiboudewiQns.Afcw Van Keekrn "Switched CapacitorChroinlnunce B3se-
Bandk l a y Lines forColor kcoders".lEEE Tiansaclions on Consumer Electronics. Vol CE-
33.No.3.pp.45l4SS.August 1987
[2]Hosktler,DavidA.,"A digitalCMOS 2HAdnptiveComb FilterIC.' I C E DIGESTOFTECH-
NICAL PAPERS,pp.3W307, Feb. 1989.
[3] Matsui, K., T. Matcuura, et al.."CMOS wdeo Filterc Usmg Switched Capacitor IlMHz
Circuitc".lEEEJournal ofSolid-SwteCircuit?.pp. 1096-1101.1'18S.
[J] Ken A. Nishimura.et al "A Monolithic Analog Video Comb Filter in 1.Z-umCMOS".IEEE
Jw"lof Solid-StateCircuiu. VOL. 28. NO l?.pp1331-1339. DECEMBER 1993.
1998 Symposium on VLSl Circuits Digest of Technical Papers

2. Memory Array
Column :Selector I
Zf,,CLK
Fig.1 Block Diagramof Comb Filter
REf -10.0 d
1WI
W 3 kHz
vBll3 kk
SPAN 2.000 MHZ
Fig.6 MeasuredSpectrumof SC MemoryOutput
Write Bus M u . LDuu"y 71Memory Cells LParasiticA Read Bus M u .
I ' I' 1 - 1 -
Row Sel.
1
output
Column Sel. PrechargeSei.
Fig.2 Schematic of Switched Capacitor Memory
ReduceNoise(Qnl5) Remove Noise #
! Mem. Cell(ReadNext) i
(a) MemoryWrite and Precharge
off
ChargeTransfer,
+r3,1
SampleInputSignal
t Mei.dlI?Rlad) TI
a
!
(b) Memory Read
Fig.3 Memory Bus Prechargewith ParallelBusAccess
0 MKR I783 478.980 Hz
T/R -51.8949 dB
NETWORK
A: REF
1
CENTER I789 772.500 HZ
SPAN I S 733.800 Hz
D I V
s.om
Fig.7 FrequencyCharacteristicsof Comb Filter
Table 1
Summary of Measured Performance~~=z~'%;VDD=SV)
Parameter Value
Dynamic Range(randomnoise) 54.8 dB
2nd,3rd Distortion -53.4 dB(2nd),-60dB(3rd)
(@1.5Vp-p Input)
Fixed Pattern Noise
(Vp-p/FuilScaleOutput)
-69.4 dB
Full Scale Input Voltage 1.5vp.p
Comb Filter Notch Depth @f,,/Z
Delay Line Frequency Ripple
Chip Area of Comb Filter
(wilh 1136 Memory Cells)
Power Consumption of Comb Filter
Technology 0.8um BiCMOS
45 *2 d B
< 0.05 d B
4.5 mm2
75mW
Write A& 7 M ~ ; : y r AddtionalDeky =SystemOverhead
h-1
(a) ConventionalComb Filter
71
1-2-1'36
hlEhlORY
Write Amp.
'Si@nalThrough Line
(b)ImprovedComb Filter
Fig.4 ImprovedComb FilterArchitecture Fig5 Chip Micrographof Analog Video Processor
1998 Symposium onVLSl Circuits Digest of Technical Papers 207