This document provides information about a course on computer architecture and hardware/software interface including: - The instructor, their contact information, lecture times and office hours. Required textbooks and the course topics that will be covered over the semester. - The grading system including exams, homework assignments, projects and their weights. - A calendar of course topics, assigned readings, exams and homework due dates over the 14 week semester.

1. M.TECH ADMISSIONS
INDIA
By:
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2. CSE 243: INTRODUCTION
TO COMPUTER
ARCHITECTURE AND
HARDWARE/SOFTWARE
INTERFACE
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3. General information
3
CSE 243 : Introduction to Computer Architecture and Hardware
/Software Interface.
Instructor : Swapna S. Gokhale
Phone : 6-2772.
Email : ssg@engr.uconn.edu
Office : UTEB 468
Lecture time : TuTh 2:00pm – 3:15 pm.
Office hours : By appointment.
(I will hang around for a few minutes at the end of
each class).
Web page : http://www.engr.uconn.edu/~ssg/cse243.html
(Lecture notes, homeworks, homework solutions etc.
will be posted on the web page)
TA : Tobias Wolfertshofer
Email : tobi@engr.uconn.edu
Office hours : Discuss with the TA
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4. Course Objective
4
Describe the general organization and architecture of computers.
Identify computers’ major components and study their functions.
Introduce hardware design issues of modern computer architectures.
Build the required skills to read and research the current literature in
computer architecture.
Learn assembly language programming.
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5. Textbooks
5
•“Computer Organization,” by Carl Hamacher, Zvonko Vranesic and
Safwat Zaky. Fifth Edition McGraw-Hill, 2002.
•“SPARC Architecture, Assembly Language Programming and C,” Richard
P. Paul, Prentice Hall, 2000.
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6. Course topics
6 1. Introduction (Chapter 1): Basic concepts, overall organization.
2. Addressing methods (Chapter 2): fetch/execute cycle, basic
addressing modes, instruction sequencing, assembly language and
stacks. CISC vs. RISC architectures.
3. Examples of ISAs (Chapter 3): 68000 instruction set architecture
and ARM instruction set architecture
4. CPU architecture (Chapter 7): Single-bus CPU, Multiple-bus CPU
Hardware control, and Microprogrammed control.
5. Arithmetic (Chapter 6): Integer arithmetic and floating-point
arithmetic.
6. Memory architecture (Chapter 5): Memory hierarchy, Primary
memory, Cache memory, virtual memory.
7. Input/Output organization (Chapter 4): I/O device addressing, I/O
data transfers, Synchronization, DMA, Interrupts, Channels, Bus
transfers, and Interfacing.
8. I/O Devices (Chapter 5): Disk systems.
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7. Grading System
7
Exam #1: (8%)
- Addressing methods, CISC and RISC architectures.
Exam #2 (8%)
- CPU Architecture
Exam #3 (8%)
- Arithmetic
Exam #4 (8%)
- Memory architecture.
Final (28%)
- All topics.
Homework assignments (15%)
- 4 homework assignments.
Lab Assignments/Projects (25%)
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8. Course topics, exams and
assignment calendar 8 Week #1 (Jan 27):
- Addressing methods.
Week #2 (Feb 3):
- Instruction Set Architectures of 68000 and ARM processors.
- Assignment #1 handed out.
Week #3 (Feb 10):
- Problem solving -- assembly language programming.
- CPU Architecture.
Week #4 (Feb 17):
- CPU Architecture.
- Assignment #1 due, Assignment #2 handed out.
- Exam #1 (Addressing modes, etc.).
Week #5 (Feb 24)
- CPU Architecture.
Week #6 (March 3)
- Arithmetic.
- Assignment #2 due, Assignment #3 handed out.
- Exam Admission. e#d2h (CoPleU. Acorcmhitecture)

9. Course topics, exams and
assignment calendar 9 Week #7 (March 10):
- Arithmetic
Week #8 (March 24):
- Memory architecture.
- Assignment #3 due.
- Exam #3 (arithmetic).
Week #9 (March 31):
- Memory architecture.
- Assignment #4 handed out.
Week #10 (April 7):
- Memory organization
- I/O organization.
Week #11 (April 14):
- I/O organization.
- Assignment #4 due.
- Exam #4 (Memory architecture).
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10. Course topics, exams and
assignment calendar 10 Week #12 (April 21):
- I/O organization
- I/O devices.
Week #13 (April 28)
- Disk systems
- Pipelining
Week #14: (May 5)
- Pipelining
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11. Grading policy
11 •Refer to the University policy regarding Student Conduct (Plagiarism, etc.)
•Grading of assignments/exams is handled by the TA, if you cannot resolve
a problem with the TA, see me.
•Assignments may be submitted by email. Hard copy will also be accepted,
but you have to submit in the department office to stamp the date. Please
submit all the assignments to the TA.
• Late assignments are penalized by a loss of 33% per day late (so 3 days late
is as late as you can get). Solution will be posted on the course web page
No assignments will be accepted after the solution is posted.
•The weeks during which exams will be held have been announced. The actual
day of that week, (Tuesday or Thursday) when the exam will be held will be
announced two weeks prior to the exam. It will be also posted on the course
web page at the same time.
If you have any conflict with the exam date, please see me in advance.
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12. Important prerequisite material
12
•CSE 207/208 is fundamental to CSE 243.
•Review issues in:
- Basic computer organization: CPU, Memory, I/O, Registers.
- Fundamentals of combinatorial design and sequential design.
- Simple ALU, simple register design.
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13. Reading
13 •Reading the text is imperative.
•Computer architecture especially processor design, changes rapidly.
You really have to keep up with the changes in the industry. This is
especially important for job interviews later.
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14. Labs
14 •Lab times (as per catalog) are not fixed. Work can be done outside of
scheduled lab hours. But expect to spend at least the time allotted in
the lab.
•Lab assignments will involve tkisem. tkisem is a tool from University
of New Mexico. Information can be found at:
http://www.cs.unm.edu/~maccabe/tkisem/begin.html
•tkisem is a Tcl/Tk version of isem (Instructional Sparc Emulator).
•tkisem involves assembly language programming.
•If you have PC (Mac running virtual PC) you can install tkisem on your
own machines. Otherwise tkisem will be in the learning center.
•Lab assignments should be submitted electronically to the TA.
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15. Feedback
15
Please provide informal feedback early and often, before the formal
review process.
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16. What is a computer?
16
 Simply put, a computer is a sophisticated electronic
calculating machine that:
 Accepts input information,
 Processes the information according to a list of internally
stored instructions and
 Produces the resulting output information.
 Functions performed by a computer are:
 Accepting information to be processed as input.
 Storing a list of instructions to process the information.
 Processing the information according to the list of
instructions.
 Providing the results of the processing as output.
 What are the functional units of a computer?
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17. Functional units of a computer
17
Arithmetic
Instr1 & Logic
Instr2
Instr3
Data1
Data2
I/O Processor
Output
Memory
Input
Control
Input unit accepts
information:
•Human operators,
•Electromechanical devices
•Other computers
Output unit sends
results of processing:
•To a monitor display,
•To a printer
Arithmetic and logic unit(ALU):
•Performs the desired
operations on the input
information as determined
by instructions in the memory
Control unit coordinates
various actions
•Input,
•Output
•Processing
Stores
information:
•Instructions,
•Data
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18. Information in a computer --
Instructions 18
 Instructions specify commands to:
 Transfer information within a computer (e.g., from memory to ALU)
 Transfer of information between the computer and I/O devices (e.g., from
keyboard to computer, or computer to printer)
 Perform arithmetic and logic operations (e.g., Add two numbers, Perform a
logical AND).
 A sequence of instructions to perform a task is
called a program, which is stored in the memory.
 Processor fetches instructions that make up a
program from the memory and performs the
operations stated in those instructions.
 What do the instructions operate upon?
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19. Information in a computer --
Data 19
 Data are the “operands” upon which
instructions operate.
 Data could be:
 Numbers,
 Encoded characters.
 Data, in a broad sense means any digital
information.
 Computers use data that is encoded as a
string of binary digits called bits.
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20. Input unit
20
Binary information must be presented to a computer in a specific format. This
task is performed by the input unit:
- Interfaces with input devices.
- Accepts binary information from the input devices.
- Presents this binary information in a format expected by the computer.
- Transfers this information to the memory or processor.
Input Unit
Memory
Processor
Real world Computer
Keyboard
Audio input
……
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21. Memory unit
21  Memory unit stores instructions and data.
 Recall, data is represented as a series of bits.
 To store data, memory unit thus stores bits.
 Processor reads instructions and reads/writes
data from/to the memory during the execution
of a program.
 In theory, instructions and data could be fetched one bit at a time.
 In practice, a group of bits is fetched at a time.
 Group of bits stored or retrieved at a time is termed as “word”
 Number of bits in a word is termed as the “word length” of a computer.
 In order to read/write to and from memory, a
processor should know where to look:
 “Address” is associated with each word location.
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22. Memory unit (contd..)
22  Processor reads/writes to/from memory based
on the memory address:
 Access any word location in a short and fixed amount of time based on
the address.
 Random Access Memory (RAM) provides fixed access time independent
of the location of the word.
 Access time is known as “Memory Access Time”.
 Memory and processor have to “communicate”
with each other in order to read/write
information.
 In order to reduce “communication time”, a small amount of RAM
(known as Cache) is tightly coupled with the processor.
 Modern computers have three to four levels of RAM units with different
speeds and sizes:
 Fastest, smallest known as Cache
 Slowest, largest known Admission.edhole.com as Main memory.

23. Memory unit (contd..)
23
 Primary storage of the computer consists of RAM
units.
 Fastest, smallest unit is Cache.
 Slowest, largest unit is Main Memory.
 Primary storage is insufficient to store large amounts
of data and programs.
 Primary storage can be added, but it is expensive.
 Store large amounts of data on secondary storage
devices:
 Magnetic disks and tapes,
 Optical disks (CD-ROMS).
 Access to the data stored in secondary storage in slower, but take advantage of the
fact that some information may be accessed infrequently.
 Cost of a memory unit depends on its access time,
lesser access time implies higher cost. Admission.edhole.com

24. Arithmetic and logic unit (ALU)
24
 Operations are executed in the Arithmetic and
Logic Unit (ALU).
 Arithmetic operations such as addition, subtraction.
 Logic operations such as comparison of numbers.
 In order to execute an instruction, operands need
to be brought into the ALU from the memory.
 Operands are stored in general purpose registers available in the ALU.
 Access times of general purpose registers are faster than the cache.
 Results of the operations are stored back in the
memory or retained in the processor for
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25. Output unit
25 •Computers represent information in a specific binary form. Output units:
- Interface with output devices.
- Accept processed results provided by the computer in specific binary form.
- Convert the information in binary form to a form understood by an
output device.
Output Unit
Memory
Processor
Computer Real world
Printer
Graphics display
Speakers
……
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26. Control unit
26
 Operation of a computer can be summarized as:
 Accepts information from the input units (Input unit).
 Stores the information (Memory).
 Processes the information (ALU).
 Provides processed results through the output units (Output unit).
 Operations of Input unit, Memory, ALU and Output
unit are coordinated by Control unit.
 Instructions control “what” operations take place
(e.g. data transfer, processing).
 Control unit generates timing signals which
determines “when” a particular operation takes
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27. How are the functional units
connected? 27 •For a computer to achieve its operation, the functional units need to
communicate with each other.
•In order to communicate, they need to be connected.
Input Output Memory Processor
Bus
•Functional units may be connected by a group of parallel wires.
•The group of parallel wires is called a bus.
•Each wire in a bus can transfer one bit of information.
•The number of parallel wires in a bus is equal to the word length of
a computer
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28. Organization of cache and main
memory 28
Main
memory Processor
Bus
Cache
memory
Why is the access time of the cache memory lesser than the
access time of the main memory?
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