Chapter 3: Digital memories & Logic Families.

1. By
Mr. C.R.Shinde
Electrical Engineering Department
Matoshri College of Engineering & Research centre, Nashik

2. Unit 03: Digital memories and logic families
Digital memories:
SRAM, DRAM, ROM, EPROM
Digital logic families:
PAL,PLA, CPLD, FPGA
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3. Module4 :- PLA
(Programmable Logic Array)
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1. Introduction.
2. Block Diagram of PLA.
3. Basic Structure of PLA.
4. Advantages & Disadvantage of PLA.
5. Comparison of PAL & PLA.

4. Classification of PLDs.
PLD
SPLD
PAL PLA
CPLD FPGA
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5. Block diagram
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6. Block diagram
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7. Basic Structure
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8. Advantages of PLA
 PLA basic design required less time.
 Design can also be quickly tested.
 Design layout is much simpler .
 They can be produce in large volume.
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9. Disadvantages of PLA
 The product term count restrict the application of PLA.
 It is not easy to use.
 It is difficult to manufacture,test and programmed.
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10. Application.
 PLA is used as counter.
 PLA is used as Decoder.
 PLA is used to provide control over datapath.
 In programmed input/output PLA used as bus interface.
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Matoshri College of Engineering & Research Center
Nashik 10

11. SR.NO PLA PAL
1 Both AND & OR array are
programmed
OR array is fixed AND array is
programmed
2 It is costly and complex They are simple.
3 AND array can be programmed to
get desired minterms
AND array can be programmed to get
desired Maxterm
4 Any Boolean function in SOP form
can be implemented using PLA
Any Boolean function in SOP form can
be implemented using PAL
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12. Module 4
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1. Introduction.
2. Block Diagram of PLA.
3. Basic Structure of PLA.
4. Advantages & Disadvantage of PLA.
5. Comparison of PAL & PLA

13. Thank you
Mr. C. R. Shinde
Electrical Engineering Department
Matoshri College of Engineering & Research centre, Nashik
If you have any query, ask me anytime on…… … .. . . .
cshinde58@gmail.com
chandrakant.shinde@matoshri.edu.in
9970031353
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Matoshri College of Engineering & Research Center
Nashik 13