introduction to FPGA

1. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
FPGA 101
FPGA Origins and Architecture
Logic Design with FPGAs
FPGA Design with Quartus Prime
LECTURE 1
By : Khldun Said

2. LECTURE 1
DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
FPGA
THE HISTORY OF

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LECTURE 1

4. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
PLD
programmable array logic:
consists of a programmable array
of AND gates that connects to a
fixed array of OR gates
The PAL structure allows any
sum-of-products (SOP) logic
expression with a defined
number of variables to be
implemented.

5. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
PLD
PLD package configurations
range from 20 pins to 28 pins
PLD could only handle up to
10-20 logic equations

6. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
CPLD
The complex programmable logic
device (CPLD): is basically a single
device containing multiple SPLDs
and providing more capacity for
larger logic designs.
The programmable interconnections
are generally called the PIA
(programmable interconnect
array)

7. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
CPLD
The CPLD Top Level Architecture
is PAL Macrocell connected with
Interconnection wires.
Densities can range from tens of
macrocells to over 1500
macrocells in packages with up
to several hundred pins.
MAX 7000 CPLD Architecture.

8. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
CPLD Microcell
Altera MAX 7000 Microcell

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LECTURE 1
CPLD
The CPLD introduced reprogrammability
to programmable logic devices
The architecture of the CPLD allowed for
easy design of wide input combinational
logic functions, like address decoders
and state machines with deterministic
timing.
However, the CPLD architecture did not
scale effectively for designs that required
many flip-flops – this has become the
province of the FPGA.

10. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
FPGA DEFINITION
Field programmable gate arrays (FPGAs) are digital integrated
circuits (ICs) that contain configurable (programmable)
blocks of logic along with configurable interconnects
between these blocks.
Design engineers can configure, or program, such devices to
perform a tremendous variety of tasks.

11. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
FPGA architecture

12. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
FPGA architecture
programmable logic blocks called
Logic Elements (LEs)
1000+ ------> 100,000
LEs described as islands in a
“sea” of interconnects.
LABs are Logic Array Blocks
each LABs have 10-16 LE

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LECTURE 1
Logic Elements

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LECTURE 1
Logic Elements

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LECTURE 1
LUT
LUT contains memory cells to
implement small logic functions.
Each cell holds ‘0’ or ‘1’.
Programmed with outputs of
truth tables.
Inputs select content of one of
the cells as output.

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LECTURE 1
Designing Adders with FPGA

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LECTURE 1
Designing Adders with FPGA

18. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
Designing Adders with FPGA

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LECTURE 1
Adaptive Logic Module (ALM)

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LECTURE 1
Adaptive Logic Module (ALM)

21. DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
LECTURE 1
FPGA design flow

22. LECTURE 1
DAMASCUS UNIVERSITY | FACULTY OF MECHANICAL & ELECTRICAL ENGINEERING
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