1. Universidad técnica de
Manabí
TEMA:
• TOPIC: UNIT III
• LANGUAGE VHDL hardware descripion
• ARCHITECTURE FIRM
• SIGNAL DATA TYPES AND VARIABLES
• OPERATORS AND SYNTAX
• ESTRUCTURAES DESCRIPTION FOR DATA FLOW
AND BEHAVIOR VHDL
• Concurrent and sequential
• PACKAGES AND BLIBLIOTECAS hierarchical design
• Quartus SOFTWARE WITH EXAMPLE I...
• Nivel:
3⁰ ¨A¨
2. INTRODUCCIÓN
Digital designs is a need
to describe a circuit efficient and
practical. A programming language
provides the possibility of a high level
of abstraction and is the right solution
for the task.
Among the languages for describing
digital circuits, the VHDL is the most
popular is achieving, as a standard and
its wide range of applications, from
modeling for circuit simulation, to
automatic synthesis of circuits.
3. ENTIDADES EN VHDL
GENERIC defines and
The entity is used to declares the module
define the inputs and properties or constants.
outputs that have a
particular circuit. To PORT define the inputs
define an entity is held and outputs of the
by keyword ENTITY. module defined.
Signal Name: address
type;
EJEMPLO:
ENTITY nombre IS
[GENERIC(lista de parámetros);]
[PORT(lista de puertos);]
END [ENTITY] nombre;
4. Señales
The signal is not an object of language, but what it does is store a
value and make it visible at the right time. one can say that the
signal has two parts, one where you type that stores the value, and
one that is read and not have to coincide with what is written.
The signal assignments are performed with the operator "<=",
while the constants and variables used by the operator "=".
We must distinguish the signals and variables, signals and are
declared between BEGIN ARCHITECTURE while variables are
declared between BEGIN PROCESS and. Within a PROCESS can be
used both.
6. Operadores.
&
Concatena
cadenas
"110" & "001" asignación <= :=
"110001".
**
exponencial
4**2
valor absoluto ABS()
multiplicación * división /
(módulo) MOD REM (resto)
Desplaza Desplaza y
un vector SLL, SRL conserva el SLA, SRA
de bits signo
Rotación a igualdad o
izquierda o a ROL, ROR desigualdad =, /=
derecha
menor, menor
o igual, mayor,
<, <=, >, Not, and, nand, or, nor,
mayor o igual >= xor, xnor.
7. RECOMENDACIÓN
After obtaining research results suggest together all members of the
research group to manipulate and create móldela VHDL hardware has to
have several aspects that should be clear that they are:
Knowledge of digital systems both use and function of digital circuits
Knowledge and handling of gates
Basic guidelines mean level programming
And having had a good understanding and application quartus and ways
of working
These points are mentioned in our research have resulted and therefore
recommend that students meet by 70% with these points to achieve a
successful work.
