This document describes the design of a frequency hopping signal generation system based on a direct digital synthesizer (DDS) implemented on an FPGA. It discusses the basic principles of DDS and how it can be used to generate frequency hopping signals. The key components of the system include a logical address control unit to generate frequency control words and a DDS unit with a phase accumulator and ROM lookup table to generate signals. Simulation results show the DDS generates stable frequency hopping signals with low error.

1. Designof Frequency-hopping Signal GenerationSystemfor DDS Based
on FPGA Hardware. Frequency-hopping communication has good
anti-interference, anti-multipath fading, anti-interception capabilities,
and fastsynchronization. Itis widely used in military, transportation,
commercial and other fields. There are three key technologies:
frequency-hopping sequencegenerator, frequency-hopping frequency
synthesizer, and frequency-hopping synchronizer. Thefrequency
synthesizer is the heart of the frequency hopping system, which directly
affects the stability of the frequency hopping signaland the accuracy of
the generated frequency. Among the frequency hopping frequency
synthesizers, DirectDigitalSynthesizer (DDS) is the most widely used .
DDS is simple and reliable, easy to control, and has high frequency
resolution and conversion speed, which is very suitable for the
requirements of frequency hopping communication.
01 、 The basic principles of DDS
In simple terms, DDS is a signalsynthesis technology that converts a
series of signals in digital form into analog form through D / A. There are
two basic ways to synthesizeDDS: oneis to calculate the digital recursive
relationship using a computer according to the sinefunction relationship
formula at a certain time interval, solvethe instantaneous sine function
amplitude and send it to the D / A converter in real time to synthesizeTo

2. producea sine wave signalof the required frequency. This synthesis
method has the characteristics of simple circuit and low cost, and the
frequency resolution of the synthesized signalcan be very high. The
other is to replace the computer softwareoperation process with a
hardwarecircuit. The high-speed memory is used as a look-up table, and
a high-speed digital-to-analog converter is used to generate a sine wave
that has been stored in digital form. This is currently the mostwidely
used direct digital frequency synthesis method.
According to the Nyquistsampling theorem, any continuous signalf (t)
with a frequency bandwidth of B is sampled. As long as the time interval
between these sampled values is less than 1 / 2B (2 times the power of
B), this representation Itmay contain all the information of the
continuous signal f (t). After quantizing the sampled signal, the original
analog signalf (t) becomes a series of digital sequences. This series of
quantized values is fixed in the read-only memory by a certain means.
The address of each storageunit is the corresponding phasesampling
address, and the content of the storageunit is the quantized sinewave
amplitude. Such a read-only memory constitutes a sine function function
table corresponding to the phase sampling in a period of 2π. Under the
action of a clock signalof a certain frequency, the obtained sine
waveformmemory is scanned cyclically through a sampling address
generated by a linear counting sequence number generator, and the

3. data in the memory is read periodically and periodically, and its output
passes The D / A converter and the low-pass filter can synthesizea
complete sine wavewith a certain frequency.
With each clock pulse, the N-bit adder adds the frequency controldata K
output fromthe data latch to the accumulation phase output from the
N-bit accumulation register, and the resultof the addition is sent to the
data input terminal of the N-bit accumulation register. The accumulation
register feeds back the new phasedata generated by the adder after the
previous clock is applied to the input of the adder, so that the adder
continues to add to the frequency controldata under the effect of the
next clock. In this way, the phaseaccumulator continuously performs
linear phase accumulation on the frequency control data under the
function of the reference frequency clock. When the accumulator
accumulates a full amount, an overflow occurs, thereby completing a
periodic action. This action is the DDS synthesis signal. For one
frequency cycle, the overflow frequency of the accumulator is the
frequency of the DDS output signal.
For a sine wavewaveformmemory with M phasesamples, when the
minimum frequency of the DDS output, that is, the frequency control
word is set to 1, reading a cycle of signals requires M reference
frequency clock cycles, which is equivalent to outputting

4. Generate a sinewave compositesignal with frequency fmin = fc / M. If
the frequency controldata is K, it takes M / K reference clock cycles to
read one cycle of signal, and the frequency of the synthesized signalis fo
= fc * K / M, which is the expression of the frequency relationship of the
DDS output signal, and the frequency resolution of DDS The rate is Δf =
fc / M, where M = 2N (N to the power of 2).
In a direct digital synthesizer, thenumber of bytes of the sine function
waveformmemory (ROM) determines the phasequantization error, and
the number of bits in each unit determines the amplitude quantization
error. In the actual DDS, using the symmetry of a sine wave, the
amplitude and phase points in the 360 ° range can be reduced to within
90 ° to reduce the ROM memory capacity. Since the D / A converter
actually samples and synthesizes sinewaves of different frequencies at a
fixed clock rate fc, as the output frequency fo increases, the number of
phasesamples decreases, the phasequantization error increases, and
quantization noiseand clutter Increase, according to the conditions of
the sampling theorem, the theoretical maximum output frequency of
DDS is fmax= fc / 2, and the maximum frequency fo max = fc / 2 in
actual work.
02. Designof core module for frequency hopping signal generation
basedon DDS

5. The entire systemconsists of two parts, a logical address controlunit
and a DDS unit. The logical address controlunit is used to generate
different frequency controlwords and change the accumulation valueof
the phaseaccumulator. The DDS unit generates signals with
corresponding frequencies according to the frequency controlword,
including a phase accumulator and a ROM lookup table.
Logical address control unit
In this design, the logical address controlunit consists of a 6-level shift
register and 6-bit memory. The system clock clk is divided by 64 to
obtain the clock clk_64, which is used as the driving clock of the logical
address controlunit. When a clock clk_64 rises, r (1: 5) = r (0: 4). In this
way, the state in the shift register will be changed and stored in the
memory to obtain the frequency control word k (5: 0).
DDS unit
The DDS unit is the core part of the design and consists of a phase
accumulator and a ROM lookup table. Under the control of the
frequency controlword (5: 0), a signalof the corresponding frequency is
generated.
① Phase Accumulator

6. The phase accumulator is an important part of DDS. Itis used to
implement phaseaccumulation and store the accumulated result. φn is
a sequence of firstdifference. If the initial value of the phase
accumulator is φ0, after one clock cycle, the value of the phase
accumulator is φ1, that is, φ1 = φ0 + k, wherek is the frequency control
word. When n clock cycles have passed, φn = φ0 + nk.
The FPGA-based phaseaccumulator design is shown in the figureabove.
As can be seen from the figure above, the phaseaccumulator consists of
a digital full adder and a digital memory. In order to improvethe
resolution of the DDS output frequency, n must be large enough, which
requires a large amount of data to be stored in ROM. However,
considering the limited hardwareresources, a truncation process is used
in the phaseaccumulator, which not only guarantees a small frequency
resolution, but also saves hardwareresources.
② ROM inquiry table
The data stored in ROM is the amplitude of the digital waveform. Within
one systemclock cycle, the phaseaccumulator can output a sequence
with a bit width of L to address it. After passing the low-pass filter, the
required waveformis obtained. If the bit width of the output sequence
of the phase accumulator is L = 16 and the bit width of the data stored in
ROM is M = 16, the storagecapacity of ROM can be calculated as 2L × M

7. = 1048576bits, although a large number of ROM can significantly
improvethe accuracy of the output signal frequency and the accuracy of
the signalamplitude, but this will increase the cost and power
consumption.
Considering the aboveproblems, on the premise of ensuring that the
output signal has good frequency resolution, taking the generation of a
sine signal as an example. Considering that the sine wavegenerated
based on DDS has periodicity, a 1/4 cycle sinewave is stored in the ROM
of this design . The figureabove shows theROM look-up table design for
storing 1/4 cycle sine waveform. Utilizing the symmetry of the sine signal,
by changing the address of the ROM memory and controlling its output
end, a full cycle sine signal is obtained.
03. Simulationresults andanalysis
DDS unit simulation results and analysis
① Simulationparameters
Now compare the DDS IP Corein Xilinx ISE8.11 to analyzethe accuracy
of the frequency generated by DDS in this design. Under the conditions
of the same simulation parameters, the DDS and DDS IP Coreof this
design weresimulated and tested.

8. ② Simulationresults andanalysis
As shown in the figurebelow, clk is the system clock, new_dds_sineis a
sine wavewith a frequency of 1.5625MHz (theoreticalvalue) based on
the design DDS when the frequency controlword k = 16, and
dds_ip_core_sineis a frequency based on the DDS IP Corewhich is
1.5625 MHz (theoretical) sine wave.
FPGA-based frequency hopping signalsimulation results
The design consists of a system clock, a frequency divider, a logical
address controlunit, and a DDS unit. The frequency-hopping signalis
generated by randomly changing the frequency control word to change
the output frequency of the signal.
The systemclock clk is divided by 64 to obtain clk_64. The logic control
unit consists of a 6-stageshiftregister. On each rising edge of clk_64, the
logic control unit will generate a 6-bit frequency control word (k). If the
DDS enable signal ce is high, the DDS will stop working; if ce is low, the
DDS will be triggered at the rising edge of clk. Under the controlof k in
the currentstate, the signal amplitude corresponding to the
corresponding address is obtained. . If k does not change, the frequency
of the DDS output sinusoidalsignal does not change. When a rising edge
of clk_64 arrives, k changes, which causes the frequency of the

9. sinusoidalsignal output by the DDS to change. When the resetsignal
reset is high, the logical address controlunit and the DDS unit return to
the initial state at the same time and remain unchanged, and the output
dds_FH output is always zero. When reset goes low, the system starts
working on a rising clk edge.
In order to easily observethe simulation results, this design uses
ModelSim SE 6.1d as the simulation waveform testsoftware. Through
the aboveanalysis, the frequency performance produced by the
designed DDS is stable, and the error of the frequency hopping signal
does not accumulate.
04.Concluding remarks
Designing a DDS-based frequency-hopping signalgeneration system
under the FPGA hardwareplatform, not only realizes fastcalculation of a
large amount of data, improves the simulation speed, but also can more
flexibly and repeatedly optimize the configuration of system parameters,
which is convenient to improve frequency System performance. The DDS
designed in this paper has simple structure, low hardwareresource
occupancy, and relatively accurate frequency. According to the different
requirements for the accuracy of the required frequency hopping signal,
the parameters are reasonably configured, thecontradiction between
the hardwareresources and thefrequency accuracy is coordinated, and

10. finally the optimal configuration of the frequency hopping system is
realized.
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