3. Transfer characteristics of FET
⇒ In an amplifier application, the FET is used in the region beyond
pinch-off.
⇒ It is also called as constant current, pentode, or current saturation
region.
⇒ Let the saturation current is IDS and IDSS is the saturation current at
VGS = 0V then
IDS = IDSS
1 −
VGS
VP
2
⇒ Above relation is called as the transfer characteristics.
⇒ Relation between IDS and VGS can be approximated by the parabola.
Dr. Varun Kumar (IIIT Surat) 3 / 9
4. Cutoff
Case 1
⇒ Consider an FET operating at a fixed value of VDS in constant
current region.
⇒ As −VGS increases (reverse bias), the conducting channel will narrow.
⇒ When VGS = VP then → IDS = IDSS
1 − VGS
VP
2
= 0
⇒ With physical device, some small current also flow from drain to
source in n-channel JFET, when VGS = VP.
⇒ This small leakage current is called as ID,OFF , when |VGS | |VP|.
⇒ ID,OFF ∼ order of nanoamperes for silicon FET.
Case 2
⇒ Gate reverse current also called gate cutoff current designated by
IGSS , when |VGS | |VP| and VDS = 0
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5. FET small signal model
⇒ The linear small signal model is same as the BJT.
⇒ We can formally express as
iD = f (vGS , vDS )
Transconductance gm and Drain Resistance rd
⇒ If both vGS and vDS both are variable.
4iD =
∂iD
∂vGS
11. vGS
4vDS
⇒ In small signal model, 4iD = id , 4vGS = vgs, 4vDS = vd s
⇒ From above relation,
id = gmvgs +
1
rd
vds
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39. id =0
We can verify that µ, rd , gm are related by
µ = gmrd
by setting id = 0
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40. Continued–
gm = gmo
1 −
VGS
VP
=
2
|VP|
(IDSS IDS )
1
2
where, gmo = −2IDSS
VP
⇒ gmo is the value of gm for VGS = 0
⇒ IDSS and VP are of opposite sign, gmo is always positive.
⇒ Transconductance varies as the square root of the drain current, or
gm ∝
√
IDS
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41. FET Model
⇒ (a) The low-frequency small-signal FET model.
⇒ (b) The high-frequency model, taking node capacitors into account
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42. Continued–
⇒ FET is much more ideal amplifier than the conventional transistor
amplifier at low frequency.
⇒ Unfortunately, this is not true beyond the audio range (20Hz-20KHz).
⇒ Cgs → Barrier capacitance between gate and source.
⇒ Cgd → Barrier capacitance between gate and drain.
⇒ Cds → Drain to source capacitance of the channel.
⇒ These internal capacitance, feedback exists between input and output
circuits and voltage amplification drops rapidly as frequency is
increased.
Parameter JFET
gm 0.1-10 mA/V
rd 0.1-1M Ω
Cds 0.1-1 pF
Cgs,Cgd 1-10pF
rgs 108
rgd 108
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