Mini Project- Dual Processor Computation

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The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes.

The objectives of this module are to demonstrate, within an embedded development environment:
Processor – to – processor communication
Multiple processors to perform one computation task using parallel processing

This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team.

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  • First test i/o board Next connect up as in resource map and try to get motor to single step. How could this be broken down? – delay, step
  • Mini Project- Dual Processor Computation

    1. 1. Mini Project – Dual Processor Computation <ul><li>Author: University of Hertfordshire </li></ul><ul><li>Date created: </li></ul><ul><li>Date revised: 2009 </li></ul><ul><li>Abstract </li></ul><ul><li>The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes. </li></ul><ul><li>The objectives of this module are to demonstrate, within an embedded development environment: </li></ul><ul><li>Processor – to – processor communication </li></ul><ul><li>Multiple processors to perform one computation task using parallel processing </li></ul><ul><li>This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team. </li></ul><ul><li>In addition to the resources found below there are supporting documents which should be used in combination with this resource. Please see: </li></ul><ul><li>Mini Projects - Introductory presentation. </li></ul><ul><li>Mini Projects - E-Log. </li></ul><ul><li>Mini Projects - Staff & Student Guide. </li></ul><ul><li>Mini Projects - Standard Grading Criteria. </li></ul><ul><li>Mini Projects - Reflection. </li></ul><ul><li>You will also need the ‘Mini Project- Dual Processor Computation’ text document. </li></ul>© University of Hertfordshire 2009 This work is licensed under a Creative Commons Attribution 2.0 License .
    2. 2. Contents <ul><li>Lecture Overview ………………………………………………………………………….3 </li></ul><ul><li>Day 1- Communication Between Two Processors …………………………………….4 </li></ul><ul><ul><li>The Problem </li></ul></ul><ul><ul><li>Resources </li></ul></ul><ul><ul><li>Asynchronous Communication </li></ul></ul><ul><ul><li>Asynchronous Communication with Only Two Handshaking Signals </li></ul></ul><ul><ul><li>Definition of Master/Slave </li></ul></ul><ul><ul><li>The handshaking signals ACK and STROBE </li></ul></ul><ul><ul><li>Preparation </li></ul></ul><ul><li>Day 2- Dual Processor Computation …………………………………………………..17 </li></ul><ul><ul><li>The Problem </li></ul></ul><ul><ul><li>Resources </li></ul></ul><ul><ul><li>Bandwidth Calculation </li></ul></ul><ul><ul><li>Unit of transfer </li></ul></ul><ul><ul><li>Asynchronous Communication with Only Two Handshaking Signals </li></ul></ul><ul><ul><li>Handshake Cycle Time </li></ul></ul><ul><ul><li>Bandwidth Measurement for this system </li></ul></ul><ul><ul><li>An example calculation </li></ul></ul><ul><ul><li>If one processor does the calculation </li></ul></ul><ul><ul><li>Two processors sharing the calculation </li></ul></ul><ul><ul><li>Time saving in first computation </li></ul></ul><ul><ul><li>Repeated Computation – see improved time saving during 1s... </li></ul></ul><ul><ul><li>Simpler notation: Normalise using tc </li></ul></ul><ul><ul><li>Normalised values for example </li></ul></ul><ul><ul><li>Method for timing each part of the calculation </li></ul></ul><ul><ul><li>Preparation </li></ul></ul><ul><li>Background Reading ……………………………………………………………………42 </li></ul><ul><li>Reflection …………………………………………………………………………………43 </li></ul><ul><li>Remember ………………………………………………………………………………..45 </li></ul><ul><li>Credits …………………………………………………………………………………….46 </li></ul>
    3. 3. BH Dual Processor Computation Today’s Lecture <ul><li>The problem </li></ul><ul><ul><li>Breakdown to each day </li></ul></ul><ul><li>Resources </li></ul><ul><ul><li>List for each day </li></ul></ul><ul><li>Preparatory work </li></ul><ul><ul><li>Remind you for each day </li></ul></ul><ul><li>Reflection process </li></ul><ul><ul><li>Reflect on each day </li></ul></ul>
    4. 4. Day 1 Communication between Two Processors
    5. 5. The Problem <ul><li>To establish Master-to-Slave asynchronous data transfer between two 68000 processors, using one 8-bit port and two additional control lines only. </li></ul><ul><ul><ul><li>between two 68000 processors </li></ul></ul></ul><ul><ul><ul><li>Master-to-Slave </li></ul></ul></ul><ul><ul><ul><li>asynchronous </li></ul></ul></ul><ul><ul><ul><li>using one 8-bit port </li></ul></ul></ul><ul><ul><ul><li>two additional control only </li></ul></ul></ul>BH Dual Processor Computation
    6. 6. Resources <ul><li>I/O Expansion board </li></ul><ul><li>Coloured wires </li></ul>BH Dual Processor Computation
    7. 7. Asynchronous Communication BH Dual Processor Computation Addr AS Data DTACK 1. AS signals valid address available on address bus – start of transfer 2. DTACK is asserted to signal that the data has been stored 4. ACK is negated to signal ready for next transfer 3. AS is negated to signal transfer complete Addr AS Data DTACK Master Slave
    8. 8. Asynchronous Communication with Only Two Handshaking Signals BH Dual Processor Computation Master Strobe Slave ACK I have data for you! Thanks, I’ve stored it! I might send some more Ok, I’m ready
    9. 9. Definition of Master/Slave <ul><li>Only the Master can initiate a data transfer </li></ul><ul><li>The Slave can only respond </li></ul>BH Dual Processor Computation
    10. 10. The handshaking signals ACK and STROBE <ul><li>Master </li></ul><ul><ul><ul><ul><ul><li>Controls STROBE </li></ul></ul></ul></ul></ul><ul><li>Slave </li></ul><ul><ul><ul><ul><ul><li>Controls ACK </li></ul></ul></ul></ul></ul>BH Dual Processor Computation
    11. 11. Preparation – Order of attack <ul><li>Plan your day (Friday) </li></ul><ul><li>Break down the problem into steps and decide: </li></ul><ul><ul><ul><li>How to start, </li></ul></ul></ul><ul><ul><ul><li>what to do next… </li></ul></ul></ul><ul><ul><ul><li>etc… </li></ul></ul></ul>BH Dual Processor Computation
    12. 12. Preparation – Resource map BH Dual Processor Computation Variable name Possible states Input or Output Allocated port pin
    13. 13. Preparation - Algorithms <ul><li>To transmit a single byte to the Slave </li></ul><ul><li>To receive a single byte from the Master </li></ul>BH Dual Processor Computation
    14. 14. Modular Structure BH Dual Processor Computation This is only an example ! main function 1 function 2 function 3 function 4 function 5 function 6
    15. 15. Preparation – message format <ul><li>You must define a message format for data block transfer. </li></ul><ul><li>Define a message header which contains: </li></ul><ul><ul><li>An address where the first byte will be stored in the slave’s memory (subsequent bytes will be stored contiguously) </li></ul></ul><ul><ul><li>The number of bytes in the data block (max 256) </li></ul></ul>BH Dual Processor Computation
    16. 16. Preparation Summary <ul><li>Create Resource Map: </li></ul><ul><ul><ul><li>Define & allocate handshaking signals </li></ul></ul></ul><ul><ul><ul><li>Define i/o port </li></ul></ul></ul><ul><li>Write Algorithms: </li></ul><ul><ul><ul><li>To transfer a single byte from Master to Slave </li></ul></ul></ul><ul><li>Define message format </li></ul>BH Dual Processor Computation
    17. 17. Day 2 Dual Processor Computation
    18. 18. The Problem <ul><li>To establish the basic requirements for engaging a number of processors in solving a common problem. </li></ul><ul><li>A simultaneous equation with obvious parallelism will be used to develop the necessary functions in ‘C’. </li></ul><ul><li>A state-time diagram will be developed to summarise the efficiency of the proposed solution. </li></ul>BH Dual Processor Computation
    19. 19. Resources <ul><li>I/O Expansion board </li></ul><ul><li>Coloured wires </li></ul>BH Dual Processor Computation
    20. 20. Bandwidth Calculation <ul><li>This is the maximum number of bits that can be transferred in a second. </li></ul><ul><li>Units: Mbits/second </li></ul><ul><li>How much data is transferred each during one complete handshaking cycle? </li></ul>BH Dual Processor Computation
    21. 21. Unit of transfer <ul><li>In our system, how much data is transferred during one handshaking cycle? </li></ul><ul><li>1 byte </li></ul>BH Dual Processor Computation If we continuously transmit bytes, we can measure the time taken to transfer a byte…..
    22. 22. Asynchronous Communication with Only Two Handshaking Signals BH Dual Processor Computation Master Strobe Slave ACK I have data for you! Thanks, I’ve stored it! I might send some more Ok, I’m ready
    23. 23. Handshake Cycle Time BH Dual Processor Computation Strobe ack time Unit transfer time 1 st cycle 2 nd cycle (µ s)
    24. 24. Bandwidth Measurement for this system <ul><li>Bandwidth = 8bits/ 20 µ s </li></ul><ul><li>= 0.4Mbits/sec </li></ul>BH Dual Processor Computation
    25. 25. An example calculation <ul><li>Calculation of ‘z’ </li></ul><ul><ul><ul><ul><ul><li>z = x / y </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>x = (a * b) / e </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>y = c + d </li></ul></ul></ul></ul></ul>BH Dual Processor Computation
    26. 26. If one processor does the calculation BH Dual Processor Computation x = a*b/e y = c+d z = x/y This is how long it would take a single processor to calculate z Processor 1 time
    27. 27. Two processors sharing the calculation BH Dual Processor Computation Processor 1 Processor 2 x = a*b/e y = c+d z = x/y time
    28. 28. Two processors sharing the calculation BH Dual Processor Computation Processor 1 x = a*b/e y = c+d z = x/y time to transfer data to processor 1 time Processor 2 tc
    29. 29. Two processors sharing the calculation BH Dual Processor Computation Processor 1 y = c+d z = x/y time Processor 2 tc x = a*b/e
    30. 30. Two processors sharing a calculation BH Dual Processor Computation time x = a*b/e y = c+d z = x/y Processor 1 x = a*b/e y = c+d z = x/y Processor 2 tc time saving over single processor
    31. 31. Two processors sharing a calculation BH Dual Processor Computation Processor 1 x = a*b/e y = c+d z = x/y time Processor 2 tc Processor 1 x = a*b/e y = c+d z = x/y Processor 2 tc time saving over single processor Single processor x = a*b/e y = c+d z = x/y
    32. 32. Time saving in first computation BH Dual Processor Computation Processor 1 tx y = c+d tz time Processor 2 tc Processor 1 tx y = c+d tz Processor 2 tc Single processor ty ty time saving over single processor tx ty tz
    33. 33. Repeated Computation – see improved time saving during 1 st repetition of calculation BH Dual Processor Computation tx tc tx tz tc tx tc ty tx tc tz tz tz ty ty ty End of 1 st calculation tx tz Single processor ty time saving over single processor P1 P2 P1 P2
    34. 34. Simpler notation: Normalise using tc <ul><li>To simplify the diagram, the calculation times can be described in units of tc . </li></ul><ul><li>To do this, just divide each time by the time for tc </li></ul><ul><li>eg: </li></ul><ul><li>if tx takes 7 times as long as tc then it will become: </li></ul><ul><ul><ul><ul><ul><li> tx/tc = 7 </li></ul></ul></ul></ul></ul>BH Dual Processor Computation
    35. 35. Normalised values for example <ul><li>Assume, just for the sake of argument, that: </li></ul><ul><ul><ul><ul><ul><li>tc = 1 </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>tx = 7 </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>ty = 3 </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>tz = 4 </li></ul></ul></ul></ul></ul>BH Dual Processor Computation
    36. 36. BH Dual Processor Computation Repeated Computation – see improved time saving during 1 st repetition of calculation tx tc tx tz tc tx tc ty tx tc tz tz tz ty ty ty tx tz Single processor ty P1 P2 12 12 14 8 P1 P2
    37. 37. Method for timing each part of the calculation <ul><li>Write a probe function – just an output pin which is asserted by the processor when it starts a calculation and negated at the end. </li></ul><ul><li>This “probe” pin should be included in the resource map. </li></ul><ul><li>Calls to the probe function should be added to the code at the beginning and the end of the calculation (the probe function itself will of course increase the measured time) </li></ul>BH Dual Processor Computation
    38. 38. BH Dual Processor Computation For this project, your level of preparation will be assessed. We will look at your logbook and the materials you have chosen to bring with you
    39. 39. Preparation – Resource map BH Dual Processor Computation Variable name Possible states Input or Output Allocated port pin
    40. 40. Preparation - Algorithms <ul><li>Probe function </li></ul><ul><li>Review receive/transmit single byte function and handshaking </li></ul>BH Dual Processor Computation
    41. 41. Preparation Summary <ul><li>Create Resource Map: </li></ul><ul><ul><ul><li>Define & allocate handshaking signals </li></ul></ul></ul><ul><ul><ul><li>Define i/o port </li></ul></ul></ul><ul><li>Write Algorithm: </li></ul><ul><ul><ul><li>Probe </li></ul></ul></ul><ul><li>Review transmit/receive byte algorithms </li></ul>BH Dual Processor Computation
    42. 42. Background Reading <ul><li>From previous modules: </li></ul><ul><ul><ul><li>68000 architecture and C language programming </li></ul></ul></ul><ul><ul><ul><li>Useful C program template </li></ul></ul></ul><ul><ul><ul><li>Review related module lecture notes </li></ul></ul></ul><ul><li>A general book on ‘C’ ( bring this to the lab too!!) </li></ul>BH Dual Processor Computation
    43. 43. Reflection Cycle BH Dual Processor Computation Reflection Observation Action
    44. 44. Reflection <ul><li>Would you break the problem down in the same way now? </li></ul><ul><li>Did you spend enough time planning what you were going to do? </li></ul><ul><li>What did you waste time on – what could you do to reduce the amount of time spent </li></ul><ul><li>Do you think that you asked for too much help, or should you have asked for help sooner </li></ul><ul><li>With hindsight, what preparation could you have done to help you make faster progress? </li></ul><ul><li>Did you find the notes that you had made during preparation useful? – how could they be improved? </li></ul><ul><li>Do you think that you could repeat the project in six months using only your logbook record as a reference. </li></ul>BH Dual Processor Computation
    45. 45. Remember <ul><li>Be methodical: </li></ul><ul><ul><li>Make progress in SMALL steps </li></ul></ul><ul><ul><li>Document as you go (comments in code and diagrams, notes in logbook) </li></ul></ul><ul><ul><li>Don’t go onto the next step until this one works FULLY and has been archived!! </li></ul></ul>BH Dual Processor Computation
    46. 46. This resource was created by the University of Hertfordshire and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme. © University of Hertfordshire 2009                  This work is licensed under a Creative Commons Attribution 2.0 License . The name of the University of Hertfordshire, UH and the UH logo are the name and registered marks of the University of Hertfordshire. To the fullest extent permitted by law the University of Hertfordshire reserves all its rights in its name and marks which may not be used except with its written permission. The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence.  All reproductions must comply with the terms of that licence. The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher.

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