Dsp Datapath

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This project is based on Data Path Architecture which consists of Shift register, MAC Unit, 16-Bit ALU and Tri-State Buffer. This whole architecture is implemented by using VHDL and simulated by using Modelsim.

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Dsp Datapath

  1. 1. AMini Project SeminaronDSP DATAPATH<br />M.Tech Microelectronics<br />Manipal Institute of Technology<br />By:<br />Abhishek Tiwari<br />B. Dhaval Kumar<br />K .Sravan Kumar<br />Rajkumar Patidar<br />
  2. 2. Introduction <br />Datapath<br />Architecture of Datapath<br />Datapath in DSP Processors<br />Modules using in Datapath<br />Modules Function <br />
  3. 3. Problem Definition <br />DSPs<br /><ul><li>Performs all key arithmetic operations in 1 cycle.
  4. 4. Hardware support for managing numeric fidelity:
  5. 5. Shifters
  6. 6. Guard bits
  7. 7. Saturation</li></ul>GPPs<br /><ul><li>Multiplies often take >1 cycle
  8. 8. Shifts often take >1 cycle
  9. 9. Other operations typically take multiple cycles</li></li></ul><li>DataPath:<br />A datapath is a collection of functional units, registers, buffers.<br />Most central processing units consist of a datapath and a control unit.<br />Processor has Two Main Units in its Architecture <br />
  10. 10. General Processor<br />
  11. 11. Datapath<br />Second Main Part in Microprocessor.<br />Contains Several Unit.<br />It Referred RTL Design.<br />
  12. 12. Basic Architecture<br />
  13. 13. A Simple DSP Processor<br />
  14. 14. DSP Datapath<br />
  15. 15. Modules<br />Registers<br />MAC<br />ALU<br />Shifter<br />Tristate Buffer<br />Control Unit<br />
  16. 16. Registers<br />Storing Multiple Bits<br />Register File <br />Synchronized by same Clock<br />8 Bit Register, 16 Bit Register <br />
  17. 17. Basic Register Circuit<br />
  18. 18. Register File<br />
  19. 19. 4 x 8 Register File<br />
  20. 20. Design Summary<br /><ul><li>Word Length: 8 bit, 16 bit
  21. 21. Input Registers 8 Bit
  22. 22. Modeling : Behavioral Modeling
  23. 23. Used Generic Statement, If – Else Statement
  24. 24. ACC Reg. is 16 bit.
  25. 25. A load control Signal for enabling Storing function.
  26. 26. A Clear for reset the stored value.
  27. 27. Functions on Falling Edge. </li></li></ul><li>Register’s Result<br />
  28. 28. Multiply-Accumulate (MAC)<br />What is MAC ?<br />Multiplication followed by accumulation.<br />Where is MAC Use ?<br />Common operation in many digital systems, particularly those highly interconnected, like digital filters, neural networks, data quantizers, etc.<br />What are the Features of MAC ?<br />Multiplying two values ,then adding the result to the previously accumulated value, which must then be re-stored in the registers for future accumulations and Checking for Overflow.<br />
  29. 29. Basic MAC Unit<br />Types of Multiplier:<br />1.Unsigned Multiplier<br />2. Signed Multiplier<br />
  30. 30. Design Summary <br />MAC is 8-bit  A,B: 8 bit I/P Registers<br /> prod: 16 bit O/P Register<br />2 Control Signals :- Start and Stop<br />Overflow Function, which might happen when the number of MAC operations is large.<br />Signed Adder<br />
  31. 31. Timing Diagram & Result<br />
  32. 32. Arithmetic Logic Unit <br />It consists of arithmetic and logic unit.<br />Arithmetic Operation : Addition Subtraction<br />Logical Operation : And,or,not etc..<br />It performs the operations according to control signal given<br />It is basic building block of microprocessor.<br />
  33. 33. ALU Architecture <br />
  34. 34. Practical Modal<br />
  35. 35. Design Summary <br />ALU is 16-bit  A,B: 16 bit i/p reg<br /> y: 16 bit o/p register<br />Control Signal is of 4-bitIt can support up to 16 different operations.<br />There is a separate flag register for carry and borrow, parity and sign flag.<br />Comparator is also included in this Alu design.<br />ALU is working on falling edge clock.<br />
  36. 36. Design Details:<br />Addition<br /> variable q : std_logic_vector(16 downto 0);<br /> when "0000" => q := ('0'& a) + ('0'& b); <br /> y <= q(15 downto 0);<br /> if ( q(16) = '1' ) then f(3) <= '1'; --carry flag<br /> end if;<br /> f(1) <= '0'; --Sign flag is zero<br /> Cont………<br />
  37. 37. Cont….<br />Subtraction<br /> variable q : std_logic_vector(16 downto 0);<br /> when "0001" => q := ('0'& a) - ('0'& b);<br /> y <= q(15 downto 0);<br /> if ( q(16) = '1' ) then f(1) <= '1'; --sign flag <br /> end if;<br /> f(3) <= '0'; --Carry flag is zero<br />
  38. 38. Cont…<br />Parity and Zero flag<br /> variable p,z : std_logic;<br /> We are checking results separately for parity and zero flag for all the operations.<br />Parity flag (even):<br /> p := y(15) xor y(14)……..…xor y(0);<br /> if ( p = '0') then f(2) <= '1';<br />Zero flag:<br /> z := y(15) or y(14)……..…or y(0);<br /> if (z = '0') then f(0) <= '1';<br />
  39. 39. Cont…<br />Comparator<br /> when "1110" =><br /> if(a>b)then y<="0000000000000100"; <br />elsif(a<b)then y<="0000000000000010";<br />elsif(a=b)then y<="0000000000000001";<br /> f(3) <= '0'; <br /> f(1) <= '0';<br /> Here instead of extra resistor for comparator o/p, o/p resistery is used for comp o/pt to save one resister.<br />At later stage we can use this results by using first 3 bit of o/p resister.<br />
  40. 40. Cont…<br />Other function<br /> when “case" => y <= a “function” b; <br /> f(3) <= '0'; <br /> f(1) <= '0';<br />Syntax for functions other then addition, subtraction and comparator is like above.<br />For these functions sign flag and zero flag is always zero.<br />
  41. 41. Control Word for Different Functions<br /><ul><li>1000 XNOR
  42. 42. 1001 PassA
  43. 43. 1010 Pass B
  44. 44. 1011 NOT B
  45. 45. 1100 Increment A
  46. 46. 1101 Decrement B
  47. 47. 1110 Compare A & B
  48. 48. 1111 Reset o/p</li></ul>0000 Addition<br />0001 Subtraction<br />0010 AND<br />0011 OR<br />0100 NAND<br />0101 NOR<br />0110 NOT A<br />0111 XOR<br />
  49. 49. ALU Results<br />Addition<br /><ul><li>Comparator</li></li></ul><li>Cont…<br />Pass A<br />A XOR B<br />
  50. 50. Shifter<br />The shifter is used for shifting bits one position either to the left or to the right.<br />The Shifter operations are referred to either as shifting or rotating depends on how the end bits are shifted in or out.<br />Here Shown Simple Shifter :<br />
  51. 51. Basic Shifter Circuit<br />
  52. 52. Design Summary<br />Word Length: 16 bit <br />Modeling : Behavioral Modeling<br />Used case statements and if else statements.<br />A ‘shift_sel’ 2-bit control Signal for selecting type of shift.<br />Functions on Falling Edge.<br />Operations: 00 – No Operation<br /> 01 – Left shift by 8 bit<br /> 10 – Right shift by 8 bit<br /> 11 – Rotate Right by 8 bit <br />
  53. 53. Shifter Result:<br />
  54. 54. Tristate Buffer<br />A Tristate Buffer, as the name suggest, has three states: 0, 1 & Z.<br />Z : Represents High Impedance State<br />
  55. 55. Control Unit<br />
  56. 56. What is Control Unit<br />The Control Unit inside the Processor is a FSM.<br />By Stepping through a Sequence of States, it controls the operation of Datapath.<br />Contains Next – State circuit, State Memory Register & Output Logic circuit.<br />Control Inputs, Status Signals.<br />Control output, Control Signal or Control Word.<br />
  57. 57. Counting 1 to 10<br />
  58. 58. Control unit Circuit<br />
  59. 59. Control Signals<br />For Registers: Load and Clear Signals<br />1 bit Start signal for enable & disable the operation of MAC unit<br />Shifter operation depend on shift_sel signal.<br />ALU has 4 bit control signal for performing operation alu_sel.<br />Tristate Buffer has Out_en control signal. <br />
  60. 60.
  61. 61. Control Unit Result<br />
  62. 62. Conclusion<br />Designed to support high-performance, repetitive, numerically intensive tasks.<br />Ability to complete several accesses to memory in a single instruction cycle.<br />Performance, cost, integration, ease of development, power consumption, and other factors for the application at hand.<br />Datapath functions have become the dominant logic type in complex logic devices.<br />
  63. 63. Applications<br />From radar systems to consumer electronics.<br />DSP data path synthesis for low-power applications.<br />Application-specific function units.<br />
  64. 64. Web Links & Information<br /><ul><li>Digital Logic and Microprocessor Design by Enoch O. Hwang
  65. 65. Circuit design with VHDL by Volnei A. Pedroni
  66. 66. A VHDL Primer by J. Bhasker</li></li></ul><li>Thank You<br />

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