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A A B B C C D D E E 1 1 2 2 3 3 4 4 Intel ULV Processor with DDRIIIL Broadwell M/B Schematics Document Compal Confidential Date : 2015/01/31 Version 0.3 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Cover Page B 1 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Cover Page B 1 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Cover Page B 1 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc.
A A B B C C D D E E 1 1 2 2 3 3 4 4 Model Name : Broadwell File Name : AHL50 / ABL52 LA-C701P Compal Confidential Ultra Light & Thin (BDW ULT) DDR3L 1600MHz 1.35V Dual Channel DDR3L-SO-DIMM X 2 SATA 3.0 USB3.0 port USB2.0 port Camera Port 0 Port 1 USB2.0 Port 3 USB3.0 Port 0 Broadwell SPI ENE KB9022 Int.KBD Touch Pad Lid switch SPI ROM 8M Port 0 Port 1 HDMI Conn HDMI DDPB port 2.5" SATA HDD ODD Port 2 FAN LAN 8166EH 1168P BGA PCI-E WLAN(MiniPCIe slot) P31 SMBUS USB2.0 Port eDPx1 eDP to LVDS Transmitter RTD2132N LVDS panel Card reader RTS5141 Lane 5 PS2 HDA Combo Jack HDA Aduio codec ALC3227 AMD EXO-Pro M330 18W PCI-Ex4 VRAM DDR3 X4 PCI-E USB2.0 Port 3 (Reserved) Lane 7-Lane10 Lane 11 Port 3 Internal SPK 24MHz LPC 33MHz PCIe 1.0:2.5Gb/s PCIe 2.0:5Gb/s GEN1 1.5Gb/s GEN2 3Gb/s GEN3 6Gb/s 2.7Gb/s PCIe 2.0:5Gb/s PCIe 3.0:8Gb/s 297MHz PCIe 1.0:2.5Gb/s PCIe 2.0:5Gb/s 480Mb/s 5Gb/s 1MHz 480Mb/s 50MHz P41~P42 P36~P40 P18 P19 P20 P24 P22 P15~16 P29 P29 P30 P30 P34 P31 P23 P25 P7 WLAN Port 4 DDIx2 CRT Conn P21 P21 TPM P27 SLB 9665 Touch Screen Port 5 P19 P19 P26 Port 6 DP to VGA Transmitter RTD2168 P37 Thermal sensor NCT7718 eDPx1 2.7Gb/s eDP panel FHD P26 P33 On small board eDP@ eDP@ LVDS@ Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Block Diagrams Custom 2 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Block Diagrams Custom 2 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Block Diagrams Custom 2 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Dr-Bios.com
A A B B C C D D E E 1 1 2 2 3 3 4 4 R=2.2K +3VALW_EC EC_SMB_CK1 EC_SMB_DA1 BAT SMBCLK SMBDATA 2N7002 R=2.2K +3V_PCH R=10K +3VS PCH_SMBCLK PCH_SMBDATA SO-DIMM 0 SO-DIMM 1 SML0CLK SML0DATA R=1K +3V_PCH 2N7002 R=2.2K +3V_PCH R=2.2K +3VS Charger SML1CLK SML1DATA EC_SMB_CK2 EC_SMB_DA2 R=100 EC_SMB_CK2 EC_SMB_DA2 CPU EC AP2 AH1 AN1 AK1 AU3 AH3 77 78 79 80 UK1:+3VALW_EC UCPU1 @ is NO SMT part (empty) PM_SLP_S5#/PM_SLP_S4# X X X X +3V_PCH VIN Power rail SUSP# X Source (CPU) X SUSP# +0.6V_0.675VS X X PM_SLP_S3# +3VALW_EC +3VALW SUSP# +5VS X SUSP# VR12.5_VR_ON X EC_ON +1.05VS +3VL +3VS PCH_PWR_EN +RTCVCC +5VALW X B+ SYSON PM_SLP_S3# +VCC_CORE PM_SLP_S3# X X +1.5VS +VL EC_ON BATT+ SUSP# X X X PM_SLP_S3# X Control (EC) EC_ON +1.35V_VDDQ RF@ : RF team request, must add. EMI@ : EMI team request, must add. ESD@ : ESD team request, must add. LVDS@ : Support LVDS panel. @EMI@,@ESD@,@RF@ : Reserve , don't pop. DIS@ : for AMD EXO <USB2.0 port> USB2.0 port DESTINATION 0 1 USB 2.0/3.0(left side) USB 2.0(right side) UMA Dis USB 2.0/3.0(left side) USB 2.0(left side) WLAN/BT 2 3 Camera 4 5 6 7 Touch screen X USB 2.0(left side) USB 2.0(right side) WLAN/BT Camera X eDP to LVDS bridge RTD2132R +3VS_RT Touch screen GCLK@ : Support GCLK GCLKUMA@ : UMA GCLKDIS@: DIS eDP@ : Support eDP panel 2N7002 +3VS_VGA R=2.2K GPU XDP Thermal Sensor for GPU Card reader Card reader DP to VGA RTD2168 +3VS_CRT USB3.0 0 <PCI-E,SATA,USB3.0> USB3.0 Dis DESTINATION Lane# 1 USB3.0 UMA HDD DESTINATION Dis SATA 0 1 Lane# UMA ODD ODD HDD Dis PCIE 0 WLAN Lane# DESTINATION UMA LAN 1 2 LAN WLAN 3 Dis PEG 0 Lane# DESTINATION UMA 1 GPU 3 2 2 PR2 PR2 RC72 RC73 QC2 RC78 RC79 QC6 VGA_SMB_CK3 VGA_SMB_DA3 DIS@ Q2416 DIS@ R327 R328 +3VS_VGA CIICSCL1 CIICSDA1 R=0 R=0 RTD2168_SMB_SCL RTD2168_SMB_SDA @ 0 ohm @ 0 ohm Touch Pad TP_SMBCLK TP_SMBDATA +3V_PCH 2N7002 R=2.2K +3VS QC7 Dis Lane# PCIE REQ UMA DESTINATION 0 1 2 3 GPU LAN LAN WLAN WLAN 4 5 PU PU PU PU X X X XTAL@ : for HSW SMT in DB phase only TP@ : TP SMBus Board ID control 15K ohm RK4 SI DB MV PV RK4 UMA 15" 0 ohm 43K ohm 27K ohm DIS 12k ohm 56k ohm 33k ohm 20k ohm SPI@ : SPI ROM request UMA@ : for UMA only 8111@ : for LAN giga 8166@ : for LAN 10/100 83 84 2N7002 Thermal Sensor for CPU EC_SMB_CK3 EC_SMB_DA3 R=10K R=2.2K +3VS_VGA +3VS Thermal Sensor CPU internal : PECI protocal PCH internal : 0x90 GPU internal : 0x82 CPU external : 0x98 GPU external : 0x98 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Notes List Custom 3 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Notes List Custom 3 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Notes List Custom 3 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. LA-C701P
5 5 4 4 3 3 2 2 1 1 D D C C B B A A LA-8661P Compal Electronics, Inc. <HDMI> <eDP> DDR3 COMPENSATION SIGNALS Layout notes DG V0.5 Trace width=12~15 mil Max length=500mil L COMPENSATION PU FOR eDP <eDP> Layout notes DG V0.9 PEG_COMP Trace width=20mil and spacing=25mil Max length=100mil L <DP TO CRT> remove BKL_PWM_CPU 20141113 DB phase For XDP 20151112 DB phase : add eDP Lan1 for FHD 20141117 SI : pop CC88 SI : pop CC99 SI : pop C295 DDR3_DRAMRST# XDP_TCK XDP_TDO_CPU XDP_TRST#_CPU XDP_TMS_CPU XDP_TDI_CPU XDP_PRDY# XDP_PREQ# PROC_DETECT# XDP_TRST#_CPU XDP_OBS3_R XDP_OBS5_R XDP_OBS2_R XDP_OBS4_R XDP_OBS6_R XDP_OBS7_R DDR3_DRAMRST# XDP_TDI_CPU XDP_PREQ# SM_RCOMP2 SM_RCOMP0 SM_RCOMP1 DDR_PG_CNTL EDP_COMP EDP_COMP PROCHOT# DDR_PG_CNTL H_PROCHOT#_R H_CPUPWRGD_R SM_RCOMP1 SM_RCOMP2 SM_RCOMP0 H_CPUPWRGD_R +1.05VS_VCCST <11,6,9> +1.35V_VDDQ <11,15,16,17,34,49> +3V_PCH <10,11,12,24,36,6,7,9> +VCCIOA_OUT <11> +VCCIO_OUT <11,6> PCH_DPC_P1 <21> PCH_DPC_N1 <21> PCH_DPC_P0 <21> PCH_DPC_N0 <21> XDP_TDI_CPU <6> XDP_TDO_CPU <6> XDP_TMS_CPU <6> XDP_TRST#_CPU <6> PCH_DPB_N3 <20> PCH_DPB_P3 <20> XDP_TCK <6> +1.05VS_PG <11,6> DDR3_DRAMRST# <15,16> PCH_DPB_N0 <20> PCH_DPB_P0 <20> PCH_DPB_N2 <20> PCH_DPB_P2 <20> PCH_DPB_N1 <20> PCH_DPB_P1 <20> EDP_CPU_LANE_N0_C <18> EDP_CPU_LANE_P0_C <18> EDP_CPU_AUX#_C <18> EDP_CPU_AUX_C <18> SM_PG_CTRL <15,49> H_PECI <25> PROCHOT# <25> H_CPUPWRGD_R <6> XDP_PRDY# <6> XDP_PREQ# <6> XDP_OBS0_R <6> XDP_OBS1_R <6> EDP_CPU_LANE_N1_C <18> EDP_CPU_LANE_P1_C <18> +1.05VS_VCCST +1.35V_VDDQ +3V_PCH +VCCIOA_OUT +VCCIO_OUT +1.35V_VDDQ +1.05VS_VCCST +VCCIOA_OUT +1.35V_VDDQ +VCCIO_OUT +3V_PCH Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDI,MSIC,XDP C 4 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDI,MSIC,XDP C 4 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDI,MSIC,XDP C 4 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P BDW_ULT_DDR3L(Interleaved) EDP DDI 1 OF 19 UCPU1A BDW-ULT-DDR3L-IL_BGA1168 SA011306191 BDW_ULT_DDR3L(Interleaved) EDP DDI 1 OF 19 UCPU1A BDW-ULT-DDR3L-IL_BGA1168 SA011306191 DDI1_TXN0 C54 DDI1_TXP0 C55 DDI1_TXN1 B58 DDI1_TXP1 C58 DDI1_TXN2 B55 DDI1_TXP2 A55 DDI1_TXN3 A57 EDP_TXP0 B46 EDP_TXN0 C45 EDP_TXN1 A47 EDP_TXP1 B47 EDP_TXN2 C47 EDP_TXP2 C46 EDP_TXN3 A49 EDP_TXP3 B49 EDP_AUXP B45 EDP_AUXN A45 DDI1_TXP3 B57 DDI2_TXP1 B54 DDI2_TXP0 C50 DDI2_TXN0 C51 DDI2_TXN1 C53 DDI2_TXN2 C49 DDI2_TXP2 B50 DDI2_TXN3 A53 DDI2_TXP3 B53 EDP_RCOMP D20 EDP_DISP_UTIL A43 RC308 470_0402_5% RC308 470_0402_5% 1 2 RC19 120_0402_1% RC19 120_0402_1% 1 2 UC10 74AUP1G07GW_TSSOP5 SA00004BV00 UC10 74AUP1G07GW_TSSOP5 SA00004BV00 GND 3 A 2 NC 1 VCC 5 Y 4 RC13 51_0402_1% @ RC13 51_0402_1% @ 1 2 T51 PAD @ T51 PAD @ CC88 0.1U_0402_16V7K ESD@ CC88 0.1U_0402_16V7K ESD@ 1 2 C295 10P_0402_50V8J ESD@ C295 10P_0402_50V8J ESD@ 1 2 RC7 1K_0402_1% @ RC7 1K_0402_1% @ 1 2 RC3 24.9_0402_1% RC3 24.9_0402_1% 1 2 T57 PAD @ T57 PAD @ T55 PAD @ T55 PAD @ CC99 0.1U_0402_16V7K ESD@ CC99 0.1U_0402_16V7K ESD@ 1 2 DDR3L BDW_ULT_DDR3L(Interleaved) MISC THERMAL PWR JTAG 2 OF 19 UCPU1B BDW-ULT-DDR3L-IL_BGA1168 SA011306191 DDR3L BDW_ULT_DDR3L(Interleaved) MISC THERMAL PWR JTAG 2 OF 19 UCPU1B BDW-ULT-DDR3L-IL_BGA1168 SA011306191 BPM#4 K59 BPM#5 H63 BPM#6 K60 SM_RCOMP0 AU60 BPM#7 J61 BPM#3 H62 BPM#1 H60 BPM#2 H61 BPM#0 J60 PROC_TDO F62 PROC_TDI F63 PROC_TMS E61 PECI N62 CATERR K61 PROCPWRGD C61 PROCHOT K63 PROC_TRST E59 PROC_TCK E60 PRDY J62 PREQ K62 SM_PG_CNTL1 AV61 SM_DRAMRST AV15 SM_RCOMP2 AU61 SM_RCOMP1 AV60 PROC_DETECT D61 T54 PAD @ T54 PAD @ T56 PAD @ T56 PAD @ RC20 100_0402_1% RC20 100_0402_1% 1 2 RC6 56_0402_5% RC6 56_0402_5% 1 2 T53 PAD @ T53 PAD @ RC18 200_0402_1% RC18 200_0402_1% 1 2 T52 PAD @ T52 PAD @ RC234 10K_0402_5% RC234 10K_0402_5% 1 2 RC4 62_0402_5% RC4 62_0402_5% 1 2 RC11 10K_0402_5% RC11 10K_0402_5% 1 2 RC12 51_0402_1% @ RC12 51_0402_1% @ 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. <DDR3L> <DDR3L> Interleaved Memory DDR_A_D63 DDR_A_D62 DDR_A_D8 DDR_A_D3 DDR_A_D4 DDR_A_D7 DDR_A_D5 DDR_A_D6 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D47 DDR_A_D46 DDR_A_D42 DDR_A_D43 DDR_A_D34 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_D35 DDR_A_D41 DDR_A_D40 DDR_A_D38 DDR_A_D36 DDR_A_D37 DDR_A_D32 DDR_A_D33 DDR_A_D61 DDR_A_D60 DDR_A_D2 DDR_A_D1 DDR_A_D0 DDR_A_D55 DDR_A_D54 DDR_A_D51 DDR_A_D48 DDR_A_D50 DDR_A_D49 DDR_A_D52 DDR_A_D53 DDR_A_D31 DDR_A_D14 DDR_A_D15 DDR_A_D25 DDR_A_D24 DDR_A_D26 DDR_A_D27 DDR_A_D30 DDR_A_D9 DDR_A_D13 DDR_A_D12 DDR_A_D10 DDR_A_D11 DDR_A_D29 DDR_A_D28 DDR_A_D19 DDR_A_D20 DDR_A_D16 DDR_A_D21 DDR_A_D17 DDR_A_D22 DDR_A_D18 DDR_A_D23 DDR_A_DQS#7 DDR_A_DQS#0 DDR_A_DQS#2 DDR_A_DQS#5 DDR_A_DQS#3 DDR_A_DQS#1 DDR_A_DQS#4 DDR_A_DQS#6 DDR_A_DQS0 DDR_A_DQS2 DDR_A_DQS1 DDR_A_DQS6 DDR_A_DQS5 DDR_A_DQS4 DDR_A_DQS3 DDR_A_DQS7 DDR_B_D33 DDR_B_D42 DDR_B_D14 DDR_B_D55 DDR_B_D43 DDR_B_D63 DDR_B_D59 DDR_B_D34 DDR_B_D24 DDR_B_D29 DDR_B_D53 DDR_B_D10 DDR_B_D13 DDR_B_D26 DDR_B_D4 DDR_B_D44 DDR_B_D57 DDR_B_D11 DDR_B_D21 DDR_B_D3 DDR_B_D46 DDR_B_D7 DDR_B_D0 DDR_B_D35 DDR_B_D30 DDR_B_D27 DDR_B_D15 DDR_B_D25 DDR_B_D23 DDR_B_D49 DDR_B_D40 DDR_B_D36 DDR_B_D48 DDR_B_D37 DDR_B_D19 DDR_B_D9 DDR_B_D47 DDR_B_D8 DDR_B_D18 DDR_B_D52 DDR_B_D62 DDR_B_D50 DDR_B_D60 DDR_B_D39 DDR_B_D56 DDR_B_D51 DDR_B_D2 DDR_B_D45 DDR_B_D6 DDR_B_D28 DDR_B_D22 DDR_B_D31 DDR_B_D61 DDR_B_D58 DDR_B_D17 DDR_B_D5 DDR_B_D41 DDR_B_D1 DDR_B_D54 DDR_B_D32 DDR_B_D38 DDR_B_D20 DDR_B_D12 DDR_B_D16 DDR_B_DQS#1 DDR_B_DQS#7 DDR_B_DQS#5 DDR_B_DQS#4 DDR_B_DQS#0 DDR_B_DQS#3 DDR_B_DQS#6 DDR_B_DQS#2 DDR_B_DQS7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS5 DDR_B_DQS4 DDR_B_DQS3 DDR_B_DQS2 DDR_B_DQS6 DDR_A_MA15 DDR_A_MA0 DDR_A_MA14 DDR_A_MA5 DDR_A_MA4 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA9 DDR_A_MA7 DDR_A_MA6 DDR_A_MA12 DDR_A_MA13 DDR_A_MA8 DDR_A_MA11 DDR_A_MA10 DDR_B_MA15 DDR_B_MA7 DDR_B_MA0 DDR_B_MA9 DDR_B_MA2 DDR_B_MA13 DDR_B_MA4 DDR_B_MA11 DDR_B_MA10 DDR_B_MA5 DDR_B_MA8 DDR_B_MA6 DDR_B_MA3 DDR_B_MA12 DDR_B_MA1 DDR_B_MA14 DDR_A_D[0..63] <15> DDR_A_DQS#[0..7] <15> DDR_A_DQS[0..7] <15> DDR_B_D[0..63] <16> DDR_B_DQS#[0..7] <16> DDR_B_DQS[0..7] <16> DDR_A_BS0 <15> DDR_A_BS1 <15> DDR_A_BS2 <15> DDR_A_RAS# <15> DDR_A_CAS# <15> DDR_A_WE# <15> DDR_A_MA[0..15] <15> DDR_CS0_DIMMA# <15> DDR_CS1_DIMMA# <15> DDR_CKE0_DIMMA <15> DDR_CKE1_DIMMA <15> M_CLK_DDR#0 <15> M_CLK_DDR0 <15> M_CLK_DDR#1 <15> M_CLK_DDR1 <15> DDR_B_MA[0..15] <16> DDR_CS0_DIMMB# <16> DDR_CS1_DIMMB# <16> DDR_CKE0_DIMMB <16> DDR_CKE1_DIMMB <16> M_CLK_DDR2 <16> M_CLK_DDR#2 <16> M_CLK_DDR#3 <16> M_CLK_DDR3 <16> DDR_B_RAS# <16> DDR_B_BS0 <16> DDR_B_BS1 <16> DDR_B_BS2 <16> DDR_B_CAS# <16> DDR_B_WE# <16> +V_SM_VREF_CNT <17> +V_DDR_REFA_R <17> +V_DDR_REFB_R <17> +V_DDR_REFA_R +V_DDR_REFB_R +V_SM_VREF_CNT +V_SM_VREF_CNT +V_DDR_REFA_R +V_DDR_REFB_R Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDRIII Custom 5 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDRIII Custom 5 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDRIII Custom 5 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P BDW_ULT_DDR3L(Interleaved) DDR CHANNEL B 4 OF 19 UCPU1D BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) DDR CHANNEL B 4 OF 19 UCPU1D BDW-ULT-DDR3L-IL_BGA1168 SB_DQ14 AR54 SB_DQSN5 AN25 SB_DQSN7 AN18 SB_DQSP4 AM28 SB_DQSP5 AM25 SB_DQSP6 AM21 SB_DQSP3 AL49 SB_DQSP7 AM18 SB_DQSP2 AL42 SB_DQSP0 AN58 SB_DQSP1 AN55 SB_DQSN6 AN21 SB_DQSN2 AL43 SB_DQSN3 AL48 SB_DQSN4 AN28 SB_DQSN1 AM55 SB_DQSN0 AM58 SB_MA14 AR46 SB_MA15 AP46 SB_MA13 AK33 SB_MA9 AU46 SB_MA10 AK36 SB_MA11 AV47 SB_MA8 AY47 SB_MA12 AU47 SB_MA4 AR45 SB_MA5 AP45 SB_MA6 AW46 SB_MA3 AR42 SB_MA7 AY46 SB_MA2 AP42 SB_MA0 AP40 SB_MA1 AR40 SB_BA2 AU49 SB_WE AK35 SB_CAS AM33 SB_BA0 AL35 SB_BA1 AM36 SB_RAS AM35 SB_CS#1 AK32 SB_ODT0 AL32 SB_CS#0 AM32 SB_CKE1 AU50 SB_CKE2 AW49 SB_CKE3 AV50 SB_CKE0 AY49 SB_CK#1 AK38 SB_CK1 AL38 SB_CK0 AN38 SB_CK#0 AM38 SB_DQ61 AM20 SB_DQ63 AP18 SB_DQ62 AR18 SB_DQ57 AR20 SB_DQ56 AN20 SB_DQ58 AK18 SB_DQ59 AL18 SB_DQ60 AK20 SB_DQ51 AM22 SB_DQ52 AN22 SB_DQ53 AP21 SB_DQ54 AK21 SB_DQ55 AK22 SB_DQ46 AK25 SB_DQ47 AL25 SB_DQ48 AR21 SB_DQ49 AR22 SB_DQ50 AL21 SB_DQ45 AM26 SB_DQ41 AR26 SB_DQ42 AR25 SB_DQ43 AP25 SB_DQ44 AK26 SB_DQ40 AN26 SB_DQ36 AR29 SB_DQ37 AN29 SB_DQ38 AR28 SB_DQ39 AP28 SB_DQ35 AK28 SB_DQ31 AK51 SB_DQ32 AM29 SB_DQ33 AK29 SB_DQ30 AM51 SB_DQ34 AL28 SB_DQ26 AM49 SB_DQ25 AK46 SB_DQ27 AK49 SB_DQ28 AM48 SB_DQ29 AK48 SB_DQ20 AK45 SB_DQ21 AK43 SB_DQ22 AM40 SB_DQ23 AM42 SB_DQ24 AM46 SB_DQ15 AN54 SB_DQ16 AK40 SB_DQ17 AK42 SB_DQ18 AM43 SB_DQ19 AM45 SB_DQ10 AM54 SB_DQ11 AK54 SB_DQ13 AK55 SB_DQ5 AK58 SB_DQ7 AN57 SB_DQ8 AP55 SB_DQ9 AR55 SB_DQ0 AP58 SB_DQ1 AR58 SB_DQ2 AM57 SB_DQ3 AK57 SB_DQ4 AL58 SB_DQ12 AL55 SB_DQ6 AR57 BDW_ULT_DDR3L(Interleaved) DDR CHANNEL A 3 OF 19 UCPU1C BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) DDR CHANNEL A 3 OF 19 UCPU1C BDW-ULT-DDR3L-IL_BGA1168 SM_VREF_DQ0 AR51 SM_VREF_DQ1 AP51 SM_VREF_CA AP49 SA_DQSP7 AW18 SA_DQSP5 AW26 SA_DQSP6 AV22 SA_DQSP2 AW57 SA_DQSP3 AW53 SA_DQSP4 AV30 SA_DQSP0 AJ62 SA_DQSP1 AN61 SA_DQSN6 AW22 SA_DQSN7 AV18 SA_DQSN4 AW30 SA_DQSN5 AV26 SA_DQSN3 AV53 SA_DQSN1 AN62 SA_DQSN2 AV57 SA_DQSN0 AJ61 SA_MA15 AU42 SA_MA13 AR35 SA_MA14 AV42 SA_MA10 AP35 SA_MA12 AU41 SA_MA11 AW41 SA_MA8 AY39 SA_MA9 AU40 SA_MA6 AV40 SA_MA7 AW39 SA_MA5 AR36 SA_MA4 AU39 SA_MA3 AP36 SA_MA2 AR38 SA_MA0 AU36 SA_MA1 AY37 SA_BA2 AY41 SA_BA1 AV35 SA_BA0 AU35 SA_WE AW34 SA_CAS AU34 SA_RAS AY34 SA_ODT0 AP32 SA_CS#0 AP33 SA_CS#1 AR32 SA_CKE3 AY43 SA_CKE0 AU43 SA_CKE1 AW43 SA_CKE2 AY42 SA_DQ15 AP60 SA_DQ63 AU17 SA_DQ62 AV17 SA_DQ61 AU19 SA_DQ60 AV19 SA_DQ59 AW17 SA_DQ58 AY17 SA_DQ57 AW19 SA_DQ56 AY19 SA_DQ55 AU21 SA_DQ54 AV21 SA_DQ53 AU23 SA_DQ52 AV23 SA_DQ51 AW21 SA_DQ50 AY21 SA_DQ49 AW23 SA_DQ48 AY23 SA_DQ47 AU25 SA_DQ46 AV25 SA_DQ45 AU27 SA_DQ44 AV27 SA_DQ43 AW25 SA_DQ42 AY25 SA_DQ41 AW27 SA_DQ40 AY27 SA_DQ39 AU29 SA_DQ38 AV29 SA_DQ37 AU31 SA_DQ36 AV31 SA_DQ35 AW29 SA_DQ34 AY29 SA_DQ33 AW31 SA_DQ32 AY31 SA_DQ31 AU52 SA_DQ30 AV52 SA_DQ29 AU54 SA_DQ26 AY52 SA_DQ27 AW52 SA_DQ24 AY54 SA_DQ23 AU56 SA_DQ22 AV56 SA_DQ21 AU58 SA_DQ20 AV58 SA_DQ19 AW56 SA_DQ18 AY56 SA_DQ17 AW58 SA_DQ16 AY58 SA_DQ14 AP61 SA_DQ13 AM60 SA_DQ12 AM61 SA_DQ11 AP62 SA_DQ10 AP63 SA_DQ9 AM62 SA_DQ8 AM63 SA_DQ7 AK60 SA_DQ6 AK61 SA_DQ5 AH60 SA_DQ3 AK62 SA_DQ2 AK63 SA_DQ1 AH62 SA_DQ0 AH63 SA_CLK#0 AU37 SA_CLK0 AV37 SA_CLK#1 AW36 SA_CLK1 AY36 SA_DQ28 AV54 SA_DQ25 AW54 SA_DQ4 AH61
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. ME CMOS CMOS ODD 2.5" HDD 15mils 15mils 15mils RTC BAT conn H：Integrated VRM enable L：Integrated VRM disable INTVRMEN * Default Setting: Dual TCK S can Chains (also known as "Shared JTAG" in other docum ent) Topolog J1s, J2s, J3s R6,R7,R8,R9 R1d,R2,R3d, R4,R5,J1d J2d,J3d* J4d and Rs5* Resistors ufStuffed Resistors Stuffed Single TCK scan chain (also known as "Com m on JTAG" in other docum ent) - Run control oper. - ME/Sx debug Be st Use for In th is topolog y, PCH TDI- TDO and CPU TDI-TDO will be chained to form one JTAG scan chain controlled by TCK0 In this topology, the CPU JTAG chain will be controlled by TCK0 and TCK1 will control the PCH JTAG chain. Description -B oundary Scan/ Manufacturing est J1s,J2s,J3s** R2,R4,R5,R5s** R1d,r3d,J1d,J2d J3d**,J4d, R6,R7,R8,R9 R5 R3d R4 R8 RF solution Add RC367 EMI@ to isolate Audio Clock by EMI request 15mils Contact ok Contact ok <XDP> <CPU and XDP> J2S J1S XDP_TCK:XDP contact with CPU No 0ohm(RS5) S1 <CPU site> <PCH site> <PCH site> S2 <CPU site> <PCH site> <XDP> <XDP> <XDP> <XDP> <PCH site> <PCH site> <PCH site> <PCH site> <PCH site> <XDP> S3 <CPU> J4d J3D J3S R2 R6 R1d R9 R7 J2D Layout notes DG V0.9 SATA_COMP Width=12mil Max length=500mil L RC17 need to close to JCPU1 Place near JXDP1 S4 DB phase : For ESD request 20141117 WLAN HDA_SDOUT: ME Flash Descriptor Security Override Low : Disabled(Default) High : Enabled 2014-10-01: Follow skyfall/pixar Direct shorted Intel ME update DB phase : For ESD request 20141117 Layout notes RC367 place near CPU DB phase 2014-11-14 Add ME_Flash_EN DB phase : For XDP 20141117 <CPU,XDP,XDP Switch> SI：Change BOM con/ig SI : pop D23 PV:RG122 change to 0-ohm shortpad PV:RC353 change to 0-ohm shortpad PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# PCH_INTVRMEN PCH_JTAG_TMS XDP_TCK_JTAGX PCH_JTAG_TDO PCH_JTAG_TDI HDA_SYNC_R HDA_SYNC HDA_SYNC HDA_RST# HDA_BIT_CLK HDA_SDOUT HDA_BITCLK_AUDIO HDA_RST_AUDIO# HDA_RST# HDA_SYNC_R HDA_SDOUT HDA_BIT_CLK ODD_PLUG# EC_+1.05VS_PG XDP_TDO XDP_TMS XDP_TDI_SWITCH XDP_TRST# XDP_TDO_CPU XDP_TDI_CPU XDP_TRST#_CPU XDP_TMS PCH_JTAG_TMS PCH_JTAG_TDO XDP_TDI PCH_JTAG_TCK XDP_TCK_JTAGX XDP_TMS_CPU XDP_TDO XDP_TRST# PCH_JTAG_RST# XDP_TDI_SWITCH XDP_TDI_CPU XDP_TDI_SWITCH PCH_JTAG_TDO XDP_TDI_SWITCH XDP_TRST#_CPU PCH_JTAG_TCK XDP_TDO_CPU XDP_TRST#_CPU XDP_TDO XDP_TCK XDP_TCK PCH_JTAG_TDI XDP_TCK_JTAGX XDP_TDI SATA_LED# SATA_COMP ODD_PLUG# PCH_GPIO36 mSATA_DET# PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO XDP_TCK_JTAGX PCH_JTAG_RST# SM_INTRUDER# PCH_SRTCRST# PCH_RTCRST# PCH_INTVRMEN PCH_RTCX1 PCH_RTCX2 CFG9 CFG8 CFG15 CFG14 CFG17 CFG2 CFG3 CFG11 CFG10 CFG3 XDP_OBS0_R XDP_OBS1_R CFG13 CFG16 CFG12 XDP_TMS XDP_PREQ# XDP_PRDY# XDP_TDO XDP_TRST# XDP_TDI XDP_TCK H_CPUPWRGD_R H_CPUPWRGD_XDP XDP_RST#_R CFG1 CFG0 CFG19 CFG4 CFG5 CFG6 CFG7 CFG18 XDP_TCK1 XDP_TCK1 PCH_JTAG_TCK XDP_TDO_CPU XDP_TDO PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 HDA_SDOUT H_CPUPWRGD_R PCH_RTCX1_0_R HDA_SDOUT SATA_PTX_DRX_P1 <29> SATA_PRX_DTX_N1 <29> SATA_PTX_DRX_N1 <29> SATA_PRX_DTX_P1 <29> HDA_SDIN0 <23> HDA_RST_AUDIO# <23> HDA_SYNC_AUDIO <23> HDA_SDOUT_AUDIO <23> HDA_BITCLK_AUDIO <23> SATA_PTX_DRX_N0 <29> SATA_PRX_DTX_N0 <29> SATA_PTX_DRX_P0 <29> SATA_PRX_DTX_P0 <29> +3VS <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,7,8,9> +RTCVCC <12,28,8> PCH_RTCX1 <28> +RTCBATT <28> +VCCIO_OUT <11,4> +1.05VS_VCCST <11,4,9> +3V_PCH <10,11,12,24,36,4,7,9> +1.5VS <12,23,37,53> +1.05VS_VCCSATA3PLL <12,34> +3VL <25,28,32,46,47,48> MPHY_PWREN <9> XDP_TMS_CPU <4> XDP_TRST#_CPU <4> XDP_TCK <4> XDP_TDI_CPU <4> SATA_LED# <32,9> mSATA_DET# <7> ODD_PLUG# <29> SYS_PWROK <25,8> CFG0 <14> CFG1 <14> CFG2 <14> CFG3 <14> CFG6 <14> CFG7 <14> CFG4 <14> CFG5 <14> CFG10 <14> CFG11 <14> CFG8 <14> CFG9 <14> CFG12 <14> CFG13 <14> CFG17 <14> CFG16 <14> CFG19 <14> CFG18 <14> CFG14 <14> CFG15 <14> CPU_PWR_DEBUG <11> PCH_SMBDATA <15,16,18,21,7> PCH_SMBCLK <15,16,18,21,7> PBTN_OUT# <25,8> PLT_RST# <22,25,27,31,35,8> XDP_PREQ# <4> XDP_PRDY# <4> XDP_DBRESET# <7,8> XDP_OBS0_R <4> XDP_OBS1_R <4> CLK_CPU_ITP <7> CLK_CPU_ITP# <7> H_CPUPWRGD_R <4> XDP_TDO_CPU <4> PCIE_PRX_DTX_N6 <31> PCIE_PRX_DTX_P6 <31> PCIE_PTX_C_DRX_N6 <31> PCIE_PTX_C_DRX_P6 <31> ME_Flash_EN <25> +3VALW <12,19,22,24,25,26,28,29,32,37,48,50,53,56,7> EC_+1.05VS_PG <25> +1.05VS_PG <11,4> +RTCVCC +RTCVCC +RTCBATT +3VL +RTCBATT_R +RTCVCC +RTCVCC +3V_PCH +3V_PCH +3V_PCH +3V_PCH +3V_PCH +RTCBATT +3VS +RTCVCC +RTCBATT +VCCIO_OUT +1.05VS_VCCST +3V_PCH +1.5VS +1.05VS_VCCSATA3PLL +3VL +3VS +3VS +1.05VS_VCCST +1.05VS_VCCST +1.05VS_VCCSATA3PLL +VCCIO_OUT +VCCIO_OUT +VCCIO_OUT +3VALW +1.05VS_VCCST +1.5VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 RTC,SATA,HDA,JTAG Custom 6 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 RTC,SATA,HDA,JTAG Custom 6 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 RTC,SATA,HDA,JTAG Custom 6 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P RC39 3K_0402_1% RC39 3K_0402_1% 1 2 RC372 1K_0402_1% RC372 1K_0402_1% 1 2 RC217 10K_0402_5% RC217 10K_0402_5% 1 2 T156 PAD T156 PAD DC1 BAV70W 3P C/C_SOT-323 DC1 BAV70W 3P C/C_SOT-323 2 3 1 CC17 0.1U_0402_16V7K CC17 0.1U_0402_16V7K 1 2 CM29 22P_0402_50V8J @ CM29 22P_0402_50V8J @ 1 2 RC373 1K_0402_1% RC373 1K_0402_1% 1 2 RC196 0_0201_5% @ RC196 0_0201_5% @ 1 2 UC5 74CBTLV3126DS_SSOP16 @ UC5 74CBTLV3126DS_SSOP16 @ 2B 7 3A 11 2A 6 3OE 12 3B 10 4OE 15 VCC 16 1B 4 1A 3 2OE 5 1OE 2 NC 1 NC 9 GND 8 4A 14 4B 13 RG117 0_0402_5% UMA@ RG117 0_0402_5% UMA@ 1 2 D23 CK0402101V05_0402-2 ESD@ SCV00001K00 D23 CK0402101V05_0402-2 ESD@ SCV00001K00 1 2 T157 PAD T157 PAD RC16 51_0402_1% @ RC16 51_0402_1% @ 1 2 RC45 210_0402_5% @ RC45 210_0402_5% @ 1 2 RC303 100_0402_1% @ RC303 100_0402_1% @ 1 2 RC283 210_0402_5% @ RC283 210_0402_5% @ 1 2 RC353 0_0402_5% short@ RC353 0_0402_5% short@ 1 2 RP1 33_0804_8P4R_5% RP1 33_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC374 1K_0402_1% RC374 1K_0402_1% 1 2 RC218 100K_0402_5% RC218 100K_0402_5% 1 2 RC199 0_0201_5% @ RC199 0_0201_5% @ 1 2 RC195 0_0201_5% short@ RC195 0_0201_5% short@ 1 2 RC236 330K_0402_5% RC236 330K_0402_5% 1 2 T159 PAD T159 PAD RC198 0_0201_5% @ RC198 0_0201_5% @ 1 2 RC14 51_0402_1% @ RC14 51_0402_1% @ 1 2 JCMOS1 SHORT PADS JCMOS1 SHORT PADS 1 2 CC5 1U_0402_6.3V6K CC5 1U_0402_6.3V6K 1 2 RC15 51_0402_1% RC15 51_0402_1% 1 2 G D S Q32 2N7002_SOT23-3 G D S Q32 2N7002_SOT23-3 2 1 3 RC307 0_0201_5% @ RC307 0_0201_5% @ 1 2 RC46 210_0402_5% @ RC46 210_0402_5% @ 1 2 CC2 1U_0402_6.3V6K CC2 1U_0402_6.3V6K 1 2 RC302 100_0402_1% @ RC302 100_0402_1% @ 1 2 RC197 0_0201_5% @ RC197 0_0201_5% @ 1 2 RC240 10K_0402_5% @ RC240 10K_0402_5% @ 1 2 CC6 1U_0402_6.3V6K CC6 1U_0402_6.3V6K 1 2 RC201 0_0201_5% short@ RC201 0_0201_5% short@ 1 2 R511 10K_0402_5% R511 10K_0402_5% 1 2 RC32 20K_0402_5% RC32 20K_0402_5% 1 2 BDW_ULT_DDR3L(Interleaved) JTAG RTC AUDIO SATA 5 OF 19 UCPU1E BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) JTAG RTC AUDIO SATA 5 OF 19 UCPU1E BDW-ULT-DDR3L-IL_BGA1168 RSVD L11 RSVD K10 PCH_TMS AD62 PCH_TDO AE61 PCH_TDI AD61 PCH_TCK AE62 PCH_TRST AU62 HDA_DOCK_RST/I2S1_SFRM AV10 HDA_DOCK_EN/I2S1_TXD AW10 HDA_SDI1/I2S1_RXD AU12 HDA_SDO/I2S0_TXD AU11 HDA_SDI0/I2S0_RXD AY10 HDA_RST/I2S_MCLK AU8 HDA_SYNC/I2S0_SFRM AV11 HDA_BCLK/I2S0_SCLK AW8 RSVD AC4 RSVD AL11 RSVD AV2 I2S1_SCLK AY8 SATALED U3 JTAGX AE63 RTCX2 AY5 SATA_RCOMP C12 SATA_IREF A12 SATA3GP/GPIO37 AC1 SATA2GP/GPIO36 V6 SATA1GP/GPIO35 U1 SATA0GP/GPIO34 V1 SATA_TP3/PETP6_L0 D17 SATA_TN3/PETN6_L0 C17 SATA_RP3/PERP6_L0 E5 SATA_RN3/PERN6_L0 F5 SATA_TP2/PETP6_L1 C15 SATA_TN2/PETN6_L1 B14 SATA_RN2/PERN6_L1 J6 SATA_RP2/PERP6_L1 H6 SATA_TP1/PETP6_L2 B17 SATA_TN1/PETN6_L2 A17 SATA_RN1/PERN6_L2 J8 SATA_RP1/PERP6_L2 H8 SATA_TP0/PETP6_L3 A15 SATA_TN0/PETN6_L3 B15 SATA_RP0/PERP6_L3 H5 SATA_RN0/PERN6_L3 J5 RTCX1 AW5 RTCRST AU7 SRTCRST AV6 INTVRMEN AV7 INTRUDER AU6 RC38 51_0402_5% @ RC38 51_0402_5% @ 1 2 YC1 32.768KHZ Q13FC1350000500 UMA@ YC1 32.768KHZ Q13FC1350000500 UMA@ 1 2 U16 74AUP1G07GW_TSSOP5 @ U16 74AUP1G07GW_TSSOP5 @ GND 3 A 2 NC 1 VCC 5 Y 4 CC86 .1U_0402_16V7K @ CC86 .1U_0402_16V7K @ 1 2 RC356 1K_0402_5% RC356 1K_0402_5% 1 2 CC4 18P_0402_50V8J UMA@ CC4 18P_0402_50V8J UMA@ 1 2 RC35 1M_0402_5% RC35 1M_0402_5% 1 2 RC306 0_0201_5% @ RC306 0_0201_5% @ 1 2 RG122 0_0402_5% short@ RG122 0_0402_5% short@ 1 2 RC304 100_0402_1% @ RC304 100_0402_1% @ 1 2 CC3 18P_0402_50V8J UMA@ CC3 18P_0402_50V8J UMA@ 1 2 RC31 10M_0402_5% UMA@ RC31 10M_0402_5% UMA@ 1 2 RC193 0_0201_5% short@ RC193 0_0201_5% short@ 1 2 JXDP1 SAMTE_BSH-030-01-L-D-A CONN@ JXDP1 SAMTE_BSH-030-01-L-D-A CONN@ GND0 1 OBSFN_A0 3 OBSFN_A1 5 GND2 7 OBSDATA_A0 9 OBSDATA_A1 11 GND4 13 OBSDATA_A2 15 OBSDATA_A3 17 GND6 19 OBSFN_B0 21 OBSFN_B1 23 GND8 25 OBSDATA_B0 27 OBSDATA_B1 29 GND10 31 OBSDATA_B2 33 OBSDATA_B3 35 GND12 37 PWRGOOD/HOOK0 39 HOOK1 41 VCC_OBS_AB 43 HOOK2 45 HOOK3 47 GND14 49 SDA 51 SCL 53 TCK1 55 TCK0 57 GND16 59 GND1 2 OBSFN_C0 4 OBSFN_C1 6 GND3 8 OBSDATA_C0 10 OBSDATA_C1 12 GND5 14 OBSDATA_C2 16 OBSDATA_C3 18 GND7 20 OBSFN_D0 22 OBSFN_D1 24 GND9 26 OBSDATA_D0 28 OBSDATA_D1 30 GND11 32 OBSDATA_D2 34 OBSDATA_D3 36 GND13 38 ITPCLK/HOOK4 40 ITPCLK#/HOOK5 42 VCC_OBS_CD 44 RESET#/HOOK6 46 DBR#/HOOK7 48 GND15 50 TD0 52 TRST# 54 TDI 56 TMS 58 GND17 60 RC10 51_0402_1% RC10 51_0402_1% 1 2 RC194 0_0201_5% short@ RC194 0_0201_5% short@ 1 2 JME1 SHORT PADS JME1 SHORT PADS 1 2 RC301 100_0402_1% @ RC301 100_0402_1% @ 1 2 CC127 0.1U_0402_16V4Z CC127 0.1U_0402_16V4Z 1 2 JRTC1 LOTES_AAA-BAT-054-K01 CONN@ JRTC1 LOTES_AAA-BAT-054-K01 CONN@ + 1 - 2 RC41 210_0402_5% @ RC41 210_0402_5% @ 1 2 RC310 0_0402_5% @ RC310 0_0402_5% @ 1 2 RC367 33_0402_5% EMI@ RC367 33_0402_5% EMI@ 1 2 CC128 2.2U_0402_6.3V6M CC128 2.2U_0402_6.3V6M 1 2 CM28 22P_0402_50V8J @ CM28 22P_0402_50V8J @ 1 2 RC34 20K_0402_5% RC34 20K_0402_5% 1 2 CC16 0.1U_0402_16V7K CC16 0.1U_0402_16V7K 1 2 RC33 1K_0402_5% RC33 1K_0402_5% 1 2 RC37 0_0201_5% @ RC37 0_0201_5% @ 1 2 RC200 0_0201_5% short@ RC200 0_0201_5% short@ 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. PCIE LAN WLAN GPU RF solution SPI ROM (8MByte ) EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P <EC> <XDP CLK > Layout notes RC368 place near CPU RC369 place near EC RC56 place near SPI ROM L Layout notes avoid stub trace too long L SI phase : Modify CLK request channel 20141214 CPU THERMAL SENSOR Address: 1001100xb NCT7718W (x is R/W bit) SI : add CPU thermal sensor 12/23 SI：Change BOM con/ig SI : add net name EC_SPI_CLK_R. PV phase : Add pull-up at PCIECLKREQ1# 20150125 SML1CLK SMBCLK CPU_XTAL24_OUT CPU_XTAL24_IN PCH_SPI_SI PCH_SPI_CS0# LPC_AD3 PCH_SPI_CLK LPC_AD0 SMBDATA PCH_SPI_SO LPC_AD2 LPC_FRAME# LPC_AD1 SML1DATA CLK_PCI_LPC CLK_PCI_TPM PCH_SPI_CLK_R PCH_SPI_SIO2 PCH_SPI_SIO3 PCH_SPI_HOLD# PCH_SPI_WP# SMBCLK SMBDATA SML1CLK SML1DATA SML0CLK SML0DATA CPU_XTAL24_OUT TESTLOW1 TESTLOW2 TESTLOW3 TESTLOW4 +1.05VS_AXCK_LCPLL PCH_CLK_BIASREF CLK_CPU_ITP# CLK_CPU_ITP CLK_PCI_TPM CLK_PCI1 CLK_PCI_LPC CLK_PCI0 USB_CR_PWREN SMBALERT# SML0CLK SML0DATA SML1CLK SMBDATA SMBCLK SML1ALERT# SML1DATA PCH_SPI_CLK_R PCH_SPI_CLK_R EC_SPI_CLK_R PCH_SPI_CS0#_R PCH_SPI_SO_R PCH_SPI_SI_R PCH_SPI_WP# PCH_SPI_SIO2 PCH_SPI_HOLD# PCH_SPI_SIO3 PCH_SPI_CS0# PCH_SPI_CS0#_R PCH_SPI_SO PCH_SPI_SO_R PCH_SPI_SI_R PCH_SPI_SI PCH_SPI_CLK PCH_SPI_CS0#_R LAN_CLKREQ# PCIECLKREQ0# SMBDATA SMBCLK CPU_XTAL24_IN_R PCH_GPIO33 WLAN_CLKREQ# PCIECLKREQ3# PCH_SPI_SI_R PCH_SPI_CLK_R PCH_SPI_HOLD# PCH_SPI_WP# PCH_SPI_CS0#_R PCH_SPI_SO_R PCIECLKREQ0# PCIECLKREQ3# GPU_CLKREQ# CPU_THERM# H_THERMDA H_THERMDC EC_SMB_CK2 EC_SMB_DA2 ALERT_L PCIECLKREQ1# PCIECLKREQ1# EC_SMB_CK2 <18,21,25,36> PCH_SMBCLK <15,16,18,21,6> PCH_SMBDATA <15,16,18,21,6> CLK_PCIE_LAN <22> CLK_PCIE_LAN# <22> CLK_PCIE_WLAN# <31> CLK_PCIE_WLAN <31> LPC_AD3 <25,27> LPC_AD0 <25,27> LPC_FRAME# <25,27> LPC_AD2 <25,27> LPC_AD1 <25,27> EC_SMB_DA2 <18,21,25,36> CLK_PCIE_GPU# <35> CLK_PCIE_GPU <35> MSATA_DET# <6> EC_KBRST# <25,9> XDP_DBRESET# <6,8> +3VS <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,8,9> +3V_PCH <10,11,12,24,36,4,6,9> +1.05VS_AXCK_LCPLL <12> CLK_PCI_TPM <27> CLK_PCI_LPC <25> CPU_XTAL24_IN <28> SMBALERT# <9> SML1ALERT# <9> USB_CR_PWREN <8> EC_SPI_CS0# <25> EC_SPI_SO <25> EC_SPI_SI <25> EC_SPI_CLK <25> CLK_CPU_ITP <6> CLK_CPU_ITP# <6> TP_SMBDATA <26> TP_SMBCLK <26> PCH_GPIO33 <9> LAN_CLKREQ# <22> WLAN_CLKREQ# <31> GPU_CLKREQ# <36> +3VS +3VS +3VS +3VS +3VS +3VS +3V_PCH +1.05VS_AXCK_LCPLL +3V_PCH +3V_PCH +3V_PCH +3V_PCH +3VALW +3V_PCH +3V_PCH +3VS +3VS +3VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 CLK,SPI,SMB,LPC C 7 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 CLK,SPI,SMB,LPC C 7 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 CLK,SPI,SMB,LPC C 7 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P CC10 18P_0402_50V8J UMA@ CC10 18P_0402_50V8J UMA@ 1 2 RC96 33K_0402_5% RC96 33K_0402_5% 1 2 RC73 1K_0402_5% RC73 1K_0402_5% 1 2 YC2 24MHZ 12PF 5YEA24000122IF40Q3 UMA@ YC2 24MHZ 12PF 5YEA24000122IF40Q3 UMA@ GND 2 3 3 1 1 GND 4 RC56 0_0402_5% RC56 0_0402_5% 1 2 RPH20 15_0804_8P4R_5% RPH20 15_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC119 2200P_0402_50V7K CC119 2200P_0402_50V7K 1 2 UC2 W25Q64FVSSIQ_SO8 UC2 W25Q64FVSSIQ_SO8 CLK 6 GND 4 DI(IO0) 5 DO(IO1) 2 /WP(IO2) 3 VCC 8 /HOLD(IO3) 7 /CS 1 RPH12 10K_0804_8P4R_5% RPH12 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC120 0.1U_0402_16V4Z CC120 0.1U_0402_16V4Z 1 2 RC125 10K_0402_5% @ RC125 10K_0402_5% @ 1 2 QC7B 2N7002DWH_SOT363-6 TP@ QC7B 2N7002DWH_SOT363-6 TP@ 3 4 5 RC368 0_0402_5% EMI@ RC368 0_0402_5% EMI@ 1 2 RC78 10K_0402_5% RC78 10K_0402_5% 1 2 UC3 NCT7718W_MSOP8 UC3 NCT7718W_MSOP8 ALERT# 6 T_CRIT# 4 GND 5 D+ 2 D- 3 SCL 8 SDA 7 VDD 1 RPH11 10K_0804_8P4R_5% RPH11 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CM33 22P_0402_50V8J @RF@ CM33 22P_0402_50V8J @RF@ 1 2 RC376 10K_0402_5% RC376 10K_0402_5% 1 2 RPH22 10K_0804_8P4R_5% RPH22 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC369 0_0402_5% EMI@ RC369 0_0402_5% EMI@ 1 2 QC2B 2N7002DWH_SOT363-6 QC2B 2N7002DWH_SOT363-6 3 4 5 RC81 10K_0402_5% TP@ RC81 10K_0402_5% TP@ 1 2 RC79 10K_0402_5% RC79 10K_0402_5% 1 2 RC48 1M_0402_5% UMA@ RC48 1M_0402_5% UMA@ 1 2 RC62 22_0402_5% EMI@ RC62 22_0402_5% EMI@ 1 2 RC80 3.3K_0402_5% @ RC80 3.3K_0402_5% @ 1 2 CC9 18P_0402_50V8J UMA@ CC9 18P_0402_50V8J UMA@ 1 2 RC82 10K_0402_5% TP@ RC82 10K_0402_5% TP@ 1 2 RC52 3K_0402_1% RC52 3K_0402_1% 1 2 QC2A 2N7002DWH_SOT363-6 QC2A 2N7002DWH_SOT363-6 6 1 2 RP2 2.2K_0804_8P4R_5% RP2 2.2K_0804_8P4R_5% 1 8 2 7 3 6 4 5 QC6B 2N7002DWH_SOT363-6 QC6B 2N7002DWH_SOT363-6 3 4 5 RG120 0_0402_5% UMA@ RG120 0_0402_5% UMA@ 1 2 QC6A 2N7002DWH_SOT363-6 QC6A 2N7002DWH_SOT363-6 6 1 2 QC7A 2N7002DWH_SOT363-6 TP@ QC7A 2N7002DWH_SOT363-6 TP@ 6 1 2 RC61 22_0402_5% EMI@ RC61 22_0402_5% EMI@ 1 2 RC85 3.3K_0402_5% RC85 3.3K_0402_5% 1 2 RC97 33K_0402_5% RC97 33K_0402_5% 1 2 BDW_ULT_DDR3L(Interleaved) LPC SMBUS C-LINK SPI 7 OF 19 UCPU1G BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) LPC SMBUS C-LINK SPI 7 OF 19 UCPU1G BDW-ULT-DDR3L-IL_BGA1168 CL_RST AF4 CL_DATA AD2 CL_CLK AF2 SML1CLK/GPIO75 AU3 SML1DATA/GPIO74 AH3 SML1ALERT/PCHHOT/GPIO73 AU4 SML0DATA AK1 SML0CLK AN1 SMBDATA AH1 SML0ALERT/GPIO60 AL2 SMBCLK AP2 SMBALERT/GPIO11 AN2 SPI_IO3 AF1 SPI_IO2 Y6 SPI_MISO AA4 SPI_MOSI AA2 SPI_CS2 AC2 SPI_CS1 Y4 SPI_CLK AA3 SPI_CS0 Y7 LFRAME AV12 LAD3 AW11 LAD2 AY12 LAD1 AW12 LAD0 AU14 C4965 0.1U_0402_16V4Z C4965 0.1U_0402_16V4Z 1 2 CM31 22P_0402_50V8J @RF@ CM31 22P_0402_50V8J @RF@ 1 2 RC84 3.3K_0402_5% RC84 3.3K_0402_5% 1 2 CM30 22P_0402_50V8J @RF@ CM30 22P_0402_50V8J @RF@ 1 2 CLOCK SIGNALS BDW_ULT_DDR3L(Interleaved) 6 OF 19 UCPU1F BDW-ULT-DDR3L-IL_BGA1168 CLOCK SIGNALS BDW_ULT_DDR3L(Interleaved) 6 OF 19 UCPU1F BDW-ULT-DDR3L-IL_BGA1168 CLKOUT_PCIE_N1 B41 CLKOUT_PCIE_P1 A41 PCIECLKRQ1/GPIO19 Y5 PCIECLKRQ0/GPIO18 U2 CLKOUT_PCIE_P0 C42 CLKOUT_ITPXDP B35 CLKOUT_LPC_0 AN15 CLKOUT_LPC_1 AP15 PCIECLKRQ4/GPIO22 U5 CLKOUT_PCIE_P4 B39 CLKOUT_PCIE_N4 A39 PCIECLKRQ3/GPIO21 N1 CLKOUT_PCIE_N0 C43 XTAL24_OUT B25 XTAL24_IN A25 PCIECLKRQ5/GPIO23 T2 CLKOUT_PCIE_P5 A37 CLKOUT_PCIE_N5 B37 CLKOUT_PCIE_P3 C37 CLKOUT_PCIE_N3 B38 PCIECLKRQ2/GPIO20 AD1 CLKOUT_PCIE_N2 C41 CLKOUT_PCIE_P2 B42 DIFFCLK_BIASREF C26 RSVD K21 RSVD M21 TESTLOW_C35 C35 TESTLOW_C34 C34 TESTLOW_AK8 AK8 TESTLOW_AL8 AL8 CLKOUT_ITPXDP_P A35 RC72 1K_0402_5% RC72 1K_0402_5% 1 2 RPH19 15_0804_8P4R_5% RPH19 15_0804_8P4R_5% 1 8 2 7 3 6 4 5
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. <HDMI> <HDMI> <eDP HPD> L:Disable DSWODVREN - On Die DSW VR Enable * Deep S3 Deep S3 RC93-->SMT Non Deep S3 RC91-->SMT Deep S3 RC286-->SMT Non Deep S3 RC286-->@ H:Enable <CPU> DP TO CRT HPD ( RTD2168) DP TO CRT ( RTD2168) Displayport Port C Enable pin RC102 pull high +3VS DB phase : For ESD request 20141117 SI: pop D25 PV:RC300 change to 0-ohm shortpad PV:RC114,RC115,RC116,RC118,RC121,RC122 change to 0-ohm shortpad SUSACK#_R PM_PWROK_R PBTN_OUT#_R PM_BATLOW# PCH_PCIE_WAKE# PCH_RSMRST# SUSWARN#_R DSWODVREN SUS_STAT# PLT_RST#_PCH SYS_PWROK BKL_PWM_CPU_R ENBKL_CPU ENVDD_CPU_R DGPU_PWR_EN_CPU DGPU_HOLD_RST#_CPU PCH_HP_DET PCH_GPIO80 ENVDD_CPU PCH_SLP_WLAN# PCH_DPWROK_R DGPU_PWROK_CPU DSWODVREN PCH_MC_WAKE# DEVSLP1 DSWODVREN PM_SLP_S3# PM_SLP_S0#_R PM_SLP_S0#_R PCH_RSMRST# PLT_RST#_PCH PCH_DPWROK_R SYS_PWROK PM_CLKRUN# PCH_HP_DET PCH_MIC_DET USB_CR_PWREN ACIN_R ACIN_R PCH_GPIO80 PCH_PWROK AOAC_PME#_R PCH_PWROK PM_BATLOW# PCH_SLP_WLAN# SUSCLK SYS_PWROK SUSACK# PM_PWROK_R SYS_RESET# PCH_MC_WAKE# AOAC_PME# APWROK_R SUSACK# <25> ACIN <25,36,47> PBTN_OUT# <25,6> PCH_RSMRST# <25> PCH_SUSWARN# <25> PM_SLP_S5# <25> PM_SLP_SUS# <25> PM_SLP_S3# <25> PM_SLP_S4# <25> PCH_DDPB_CLK <20> PCH_DDPB_DAT <20> PCH_DDPB_HPD <20> ENVDD_CPU <19> ENBKL <25> BKL_PWM_CPU <18,19> EDP_HPD <18> PCH_DPWROK <25> PCH_PWROK <25> PLT_RST# <22,25,27,31,35,6> PCH_PCIE_WAKE# <31> PM_CLKRUN# <25> AOAC_PME# <25> SYS_PWROK <25,6> SUSWARN#_R <9> USB_CR_PWREN <7> DDI2_AUX_DP <21> DDI2_AUX_DN <21> DDI2_HPD <21> DEVSLP1 <9> SPOK <48> XDP_DBRESET# <6,7> +3V_PCH <10,11,12,24,36,4,6,7,9> +3VS <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,9> +RTCVCC <12,28,6> +3V_DSW_P <12,9> SUSCLK <31> DGPU_PWR_EN <25,37,54,9> DGPU_HOLD_RST# <35,9> DGPU_PWROK <36,9> +3VS +3VS +RTCVCC +3V_DSW_P +3VS +3V_DSW_P +3VS +3V_PCH +3VS +RTCVCC +3V_DSW_P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PM,GPIO,DDI C 8 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PM,GPIO,DDI C 8 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PM,GPIO,DDI C 8 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P RC122 0_0402_5% short@ RC122 0_0402_5% short@ 1 2 RC371 0_0201_5% short@ RC371 0_0201_5% short@ 1 2 RC93 0_0201_5% short@ RC93 0_0201_5% short@ 1 2 RC305 0_0402_5% @ RC305 0_0402_5% @ 1 2 RC106 10K_0402_5% RC106 10K_0402_5% 1 2 RC91 0_0201_5% @ RC91 0_0201_5% @ 1 2 T147 PAD @ T147 PAD @ RC104 0_0201_5% short@ RC104 0_0201_5% short@ 1 2 T143 PAD @ T143 PAD @ RC107 2.2K_0402_5% @ RC107 2.2K_0402_5% @ 1 2 RC101 10K_0402_5% RC101 10K_0402_5% 1 2 RC254 330K_0402_5% RC254 330K_0402_5% 1 2 UC9 SN74AHC1G08DCKR_SC70-5 @ UC9 SN74AHC1G08DCKR_SC70-5 @ IN1 1 IN2 2 G 3 O 4 P 5 BDW_ULT_DDR3L(Interleaved) eDP SIDEBAND PCIE DISPLAY 9 OF 19 UCPU1I BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) eDP SIDEBAND PCIE DISPLAY 9 OF 19 UCPU1I BDW-ULT-DDR3L-IL_BGA1168 DDPC_AUXN B6 DDPC_AUXP A6 DDPB_AUXP B5 EDP_BKLEN A9 GPIO53 L4 GPIO51 R5 GPIO54 L3 GPIO52 L1 GPIO55 U7 PME AD4 PIRQD/GPIO80 N2 PIRQC/GPIO79 N4 DDPB_CTRLCLK B9 DDPB_CTRLDATA C9 DDPC_CTRLCLK D9 DDPC_CTRLDATA D11 DDPB_HPD C8 EDP_HPD D6 DDPC_HPD A8 DDPB_AUXN C5 EDP_VDDEN C6 EDP_BKLCTL B8 PIRQA/GPIO77 U6 PIRQB/GPIO78 P4 D24 CK0402101V05_0402-2 @ESD@ D24 CK0402101V05_0402-2 @ESD@ 1 2 RC269 0_0201_5% @ RC269 0_0201_5% @ 1 2 RC102 2.2K_0402_5% RC102 2.2K_0402_5% 1 2 RC120 100K_0402_5% RC120 100K_0402_5% 1 2 D25 CK0402101V05_0402-2 ESD@ SCV00001K00 D25 CK0402101V05_0402-2 ESD@ SCV00001K00 1 2 RC115 0_0402_5% short@ RC115 0_0402_5% short@ 1 2 T145PAD @ T145PAD @ RC100 0_0201_5% short@ RC100 0_0201_5% short@ 1 2 RC286 0_0201_5% short@ RC286 0_0201_5% short@ 1 2 RC110 8.2K_0402_5% RC110 8.2K_0402_5% 1 2 RC116 0_0402_5% short@ RC116 0_0402_5% short@ 1 2 DC3 CH751H-40PT_SOD323-2 DC3 CH751H-40PT_SOD323-2 2 1 RC94 0_0201_5% short@ RC94 0_0201_5% short@ 1 2 DC2 CH751H-40PT_SOD323-2 DC2 CH751H-40PT_SOD323-2 2 1 RC121 0_0402_5% short@ RC121 0_0402_5% short@ 1 2 RPH15 10K_0804_8P4R_5% RPH15 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC109 10K_0402_5% RC109 10K_0402_5% 1 2 RC112 100K_0402_5% RC112 100K_0402_5% 1 2 C592 0.047U_0402_16V7K ESD@ C592 0.047U_0402_16V7K ESD@ 1 2 RC98 1K_0402_5% RC98 1K_0402_5% 1 2 T142 PAD @ T142 PAD @ RC268 0_0201_5% short@ RC268 0_0201_5% short@ 1 2 RC316 0_0201_5% short@ RC316 0_0201_5% short@ 1 2 RC118 0_0402_5% short@ RC118 0_0402_5% short@ 1 2 T154 PAD @ T154 PAD @ BDW_ULT_DDR3L(Interleaved) SYSTEM POWER MANAGEMENT 8 OF 19 UCPU1H BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) SYSTEM POWER MANAGEMENT 8 OF 19 UCPU1H BDW-ULT-DDR3L-IL_BGA1168 SLP_A AL5 SLP_SUS AP4 SLP_LAN AJ7 SLP_S3 AT4 SLP_S5/GPIO63 AP5 SLP_S4 AJ6 SUSCLK/GPIO62 AE6 CLKRUN/GPIO32 V5 SUS_STAT/GPIO61 AG4 WAKE AJ5 DSWVRMEN AW7 DPWROK AV5 SLP_WLAN/GPIO29 AM5 SLP_S0 AF3 SUSWARN/SUSPWRDNACK/GPIO30 AV4 PWRBTN AL7 BATLOW/GPIO72 AN4 ACPRESENT/GPIO31 AJ8 RSMRST AW6 PCH_PWROK AY7 SUSACK AK2 PLTRST AG7 APWROK AB5 SYS_PWROK AG2 SYS_RESET AC3 DC4 CH751H-40PT_SOD323-2 DC4 CH751H-40PT_SOD323-2 2 1 RC103 0_0201_5% short@ RC103 0_0201_5% short@ 1 2 T83 PAD T83 PAD RC255 330K_0402_5% @ RC255 330K_0402_5% @ 1 2 RC300 0_0402_5% short@ RC300 0_0402_5% short@ 1 2 RC114 0_0402_5% short@ RC114 0_0402_5% short@ 1 2 RPH27 10K_0804_8P4R_5% RPH27 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 C127 0.1U_0402_10V6K @ESD@ C127 0.1U_0402_10V6K @ESD@ 1 2 RC99 0_0201_5% short@ RC99 0_0201_5% short@ 1 2 T144 PAD @ T144 PAD @
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Dummy GPIO27 * PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable 0 SPI * Boot BIOS Location PCH_GPIO86 Boot BIOS Strap Layout notes DG V0.9 PCH_OPIRCOMP Width=12mil,spacing=12mil Max length=500mil L <SI> PRH14.4 change from +3V_PCH to +3VS for S3 leakage <PV>PRH14 change to RPH23. PRH15 change to RPH24. PRH16 change to RPH25. PV:RC124 change to 0-ohm shortpad I2C_1_SDA EC_KBRST# PCH_OPIRCOMP EC_SCI# H_THERMTRIP#_C SERIRQ EC_LID_OUT# PCH_AUDIO_PWREN I2C_1_SCL PCH_GPIO85 NGFF_WIFI_3.3_PWREN SATA1_PWREN USB32_P0_PWREN_R# USB_CAM_PWREN PCH_GPIO9 WWAN_PWREN PCH_GPIO33 BT_ON EC_FB_CLAMP_TGL_REQ# DEVSLP1 H_THEMTRIP# LPDDR3_ID1 DGPU_PRSNT# LPDDR3_ID1 LPDDR3_ID2 DGPU_PRSNT# LPDDR3_ID2 MSATA_SSD_PWREN LAN_PWR_EN PCH_GPIO58 EC_PME# WL_OFF# UART_WAKE# PCH_LAN_WAKE# PCH_LAN_RST# PCH_CR_WAKE# PCH_CR_RST# HDA_SPKR TOUCH_PANEL_PWREN NGFF_WIFI_3.3_PWREN WWAN_PWREN MSATA_SSD_PWREN TOUCH_PANEL_PWREN PCH_CR_RST# PCH_CR_WAKE# PCH_LAN_RST# PCH_LAN_WAKE# SATA1_PWREN PCH_AUDIO_PWREN EC_LID_OUT# UART_WAKE# BT_ON USB_CAM_PWREN LAN_PWR_EN I2C_0_SDA I2C_0_SCL EC_SCI# SMBALERT# SML1ALERT# SUSWARN#_R I2C_1_SDA I2C_0_SCL I2C_0_SDA I2C_1_SCL ODD_PWR ODD_DA# TS_GPIO_CPU ODD_DA# NMI_DBG#_CPU EC_PME#_R EC_FB_CLAMP_TGL_REQ# PCH_GPIO58 USB_OC2# USB_OC0# USB_OC1# SATA_LED# SERIRQ PCH_GPIO87 PCH_GPIO9 USB32_P0_PWREN_R# NMI_DBG#_CPU EC_SCI# <25> EC_KBRST# <25,7> SERIRQ <25,27> LAN_PWR_EN <22> WL_OFF# <10,31> EC_PME# <22,25> HDA_SPKR <23> EC_LID_OUT# <25> DEVSLP1 <8> DGPU_PWR_EN <25,37,54,8> DGPU_HOLD_RST# <35,8> SMBALERT# <7> SML1ALERT# <7> SUSWARN#_R <8> MPHY_PWREN <6> PCH_GPIO33 <7> ODD_PWR <29> ODD_DA# <29> TS_GPIO_CPU <19> NMI_DBG#_CPU <25> +1.05VS_VCCST <11,4,6> +3VS <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8> +3V_PCH <10,11,12,24,36,4,6,7> +3V_DSW_P <12,8> USB_OC2# <10> USB_OC0# <10> USB_OC1# <10> SATA_LED# <32,6> DGPU_PWROK <36,8> +3VS +3V_PCH +1.05VS_VCCST +3V_PCH +3VS +3VS +3V_DSW_P +3VS +3V_PCH +3VS +1.05VS_VCCST +3VS +3V_PCH +3V_DSW_P +3VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GPIO,UART,I2C Custom 9 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GPIO,UART,I2C Custom 9 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GPIO,UART,I2C Custom 9 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P RC261 10K_0402_5% @ RC261 10K_0402_5% @ 1 2 RPH21 10K_0804_8P4R_5% RPH21 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC263 10K_0402_5% @ RC263 10K_0402_5% @ 1 2 RC242 1K_0402_5% RC242 1K_0402_5% 1 2 RPH25 10K_0804_8P4R_5% RPH25 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RPH24 10K_0804_8P4R_5% RPH24 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 T148 PAD T148 PAD RPH10 10K_0804_8P4R_5% RPH10 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC108 0_0201_5% @ RC108 0_0201_5% @ 1 2 RPH28 10K_0804_8P4R_5% @ RPH28 10K_0804_8P4R_5% @ 1 8 2 7 3 6 4 5 T150 PAD T150 PAD RPH23 10K_0804_8P4R_5% RPH23 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC135 10K_0402_5% @ RC135 10K_0402_5% @ 1 2 RC117 0_0201_5% @ RC117 0_0201_5% @ 1 2 RC129 0_0402_5% short@ RC129 0_0402_5% short@ 1 2 RPH18 1K_0804_8P4R_5% @ RPH18 1K_0804_8P4R_5% @ 1 8 2 7 3 6 4 5 RC265 10K_0402_5% DIS@ RC265 10K_0402_5% DIS@ 1 2 RC124 0_0201_5% short@ RC124 0_0201_5% short@ 1 2 T149 PAD T149 PAD RC131 49.9_0402_1% RC131 49.9_0402_1% 1 2 RPH26 10K_0804_8P4R_5% RPH26 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 T158 PAD T158 PAD BDW_ULT_DDR3L(Interleaved) SERIAL IO GPIO MISC CPU/ 10 OF 19 UCPU1J BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) SERIAL IO GPIO MISC CPU/ 10 OF 19 UCPU1J BDW-ULT-DDR3L-IL_BGA1168 RSVD AB21 RSVD AF20 SERIRQ T4 LAN_PHY_PWR_CTRL/GPIO12 AM7 GPIO58 AL4 GPIO44 AK4 BMBUSY/GPIO76 P1 GPIO8 AU2 GPIO15 AD6 GPIO17 T3 GPIO16 Y1 GPIO59 AT5 GPIO48 U4 GPIO47 AB6 GPIO49 Y3 GPIO50 P3 HSIOPC/GPIO71 Y2 GPIO13 AT3 GPIO25 AM4 GPIO14 AH4 GPIO46 AG3 GPIO10 AM2 GPIO9 AM3 DEVSLP0/GPIO33 P2 SDIO_POWER_EN/GPIO70 C4 DEVSLP1/GPIO38 L2 SPKR/GPIO81 V2 DEVSLP2/GPIO39 N5 THRMTRIP D60 RCIN/GPIO82 V4 GSPI0_CS/GPIO83 R6 GSPI0_MISO/GPIO85 N6 GSPI0_CLK/GPIO84 L6 GSPI0_MOSI/GPIO86 L8 GSPI1_CS/GPIO87 R7 GSPI1_CLK/GPIO88 L5 GSPI_MOSI/GPIO90 K2 GSPI1_MISO/GPIO89 N7 UART0_RXD/GPIO91 J1 UART0_RTS/GPIO93 J2 UART0_TXD/GPIO92 K3 UART0_CTS/GPIO94 G1 UART1_TXD/GPIO1 G2 UART1_RXD/GPIO0 K4 I2C0_SCL/GPIO5 F3 I2C1_SDA/GPIO6 G4 I2C1_SCL/GPIO7 F1 SDIO_CMD/GPIO65 F4 SDIO_CLK/GPIO64 E3 SDIO_D0/GPIO66 D3 SDIO_D3/GPIO69 E2 SDIO_D2/GPIO68 C3 SDIO_D1/GPIO67 E4 GPIO28 AD7 GPIO57 AP1 GPIO56 AG6 GPIO45 AG5 GPIO24 AD5 GPIO27 AN5 GPIO26 AN3 UART1_RST/GPIO2 J3 I2C0_SDA/GPIO4 F2 UART1_CTS/GPIO3 J4 PCH_OPI_RCOMP AW15 RC119 0_0201_5% @ RC119 0_0201_5% @ 1 2 RC264 10K_0402_5% @ RC264 10K_0402_5% @ 1 2 RK11 10K_0402_5% RK11 10K_0402_5% 1 2 RPH14 10K_0804_8P4R_5% RPH14 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC277 10K_0402_5% RC277 10K_0402_5% 1 2 RC262 10K_0402_5% UMA@ RC262 10K_0402_5% UMA@ 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Layout notes DG V0.9 USBRBIAS Trace width=50ohm and spacing=15mil Max length=500mil L USB2.0 ( on small BD ) USB2.0/USB3.0 Camera WLAN/BT USB2.0 USB2.0/USB3.0 LAN Touch screen Card reader <Page12> Layout notes DG V0.9 PCIE_RCOMP Width=12mil,spacing=12mil Max length=500mil L DGPU WL_OFF# PCIE_PTX_DRX_N3 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_P3 PCH_PCIE_RCOMP USBRBIAS USB1_PWR_EN USB_OC2# USB1_PWR_EN PCIE_PTX_DRX_N5_L0 PCIE_PTX_DRX_N5_L1 PCIE_PTX_DRX_P5_L1 PCIE_PTX_DRX_P5_L0 PCIE_PTX_DRX_N5_L3 PCIE_PTX_DRX_N5_L2 PCIE_PTX_DRX_P5_L3 PCIE_PTX_DRX_P5_L2 USB_OC0# USB_OC1# USB3_RX0_P <30> USB3_RX0_N <30> USB3_TX0_P <30> USB3_TX0_N <30> USB_OC2# <9> PCIE_PRX_DTX_N3 <22> PCIE_PTX_C_DRX_P3 <22> PCIE_PTX_C_DRX_N3 <22> PCIE_PRX_DTX_P3 <22> USB20_P2 <32> USB20_N2 <32> WL_OFF# <31,9> USB20_N6 <32> USB20_P6 <32> PCIE_CTX_GRX_P0 <35> PCIE_CTX_GRX_N0 <35> PCIE_CRX_GTX_P0 <35> PCIE_CRX_GTX_N0 <35> PCIE_CTX_GRX_P2 <35> PCIE_CTX_GRX_N2 <35> PCIE_CTX_GRX_P3 <35> PCIE_CTX_GRX_N3 <35> PCIE_CRX_GTX_P2 <35> PCIE_CRX_GTX_N2 <35> PCIE_CRX_GTX_P3 <35> PCIE_CRX_GTX_N3 <35> PCIE_CRX_GTX_P1 <35> PCIE_CTX_GRX_N1 <35> PCIE_CTX_GRX_P1 <35> PCIE_CRX_GTX_N1 <35> USB20_N5 <19> USB20_P5 <19> USB20_P0 <30> USB20_N0 <30> USB20_P1 <30> USB20_N1 <30> USB20_P3 <31> USB20_N3 <31> USB20_P4 <19> USB20_N4 <19> +3V_PCH <11,12,24,36,4,6,7,9> USB_OC0# <9> USB_OC1# <9> +3V_PCH +1.05VS_VCCUSB3PLL +3V_PCH Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PCIE,USB C 10 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PCIE,USB C 10 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PCIE,USB C 10 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P C4 .1U_0402_16V7K DIS@ C4 .1U_0402_16V7K DIS@ 1 2 C10 .1U_0402_16V7K DIS@ C10 .1U_0402_16V7K DIS@ 1 2 C5 .1U_0402_16V7K DIS@ C5 .1U_0402_16V7K DIS@ 1 2 C6 .1U_0402_16V7K DIS@ C6 .1U_0402_16V7K DIS@ 1 2 CC15 0.1U_0402_16V7K CC15 0.1U_0402_16V7K 1 2 C3 .1U_0402_16V7K DIS@ C3 .1U_0402_16V7K DIS@ 1 2 C7 .1U_0402_16V7K DIS@ C7 .1U_0402_16V7K DIS@ 1 2 RPH29 10K_0804_8P4R_5% RPH29 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 C8 .1U_0402_16V7K DIS@ C8 .1U_0402_16V7K DIS@ 1 2 RC111 22.6_0402_1% RC111 22.6_0402_1% 1 2 BDW_ULT_DDR3L(Interleaved) PCIE USB 11 OF 19 UCPU1K BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) PCIE USB 11 OF 19 UCPU1K BDW-ULT-DDR3L-IL_BGA1168 RSVD AM10 RSVD AN10 USB2P1 AT7 USB2P0 AM8 PERN3 G11 PETN5_L0 C23 USBRBIAS AJ10 USBRBIAS AJ11 PETN5_L1 B23 PETP5_L1 A23 USB2N7 AR13 USB2P7 AP13 USB2N6 AP11 USB2P5 AN13 USB2N5 AM13 USB2P6 AN11 USB2P4 AL15 USB2N4 AM15 USB2P3 AT10 USB2N3 AR10 USB2P2 AP8 USB2N2 AR8 USB2N1 AR7 USB2N0 AN8 PETP4 A29 PERP4 G13 PERN5_L3 E6 PERP5_L3 F6 PETN5_L2 B21 PERP5_L2 G10 PERN5_L2 H10 OC0/GPIO40 AL3 OC1/GPIO41 AT1 OC2/GPIO42 AH2 OC3/GPIO43 AV3 PETN3 C29 PERP3 F11 PERN5_L1 F8 PETN5_L3 B22 PETP5_L3 A21 PERP5_L1 E8 PETN4 B29 PETP5_L0 C22 PERP5_L0 E10 PERN5_L0 F10 PERN4 F13 PETP3 B30 PCIE_IREF B27 PCIE_RCOMP A27 RSVD E13 PETP5_L2 C21 PERP1/USB3RP3 F17 PERN1/USB3RN3 G17 RSVD E15 PETP1/USB3TP3 C31 PETN1/USB3TN3 C30 PERN2/USB3RN4 F15 PETP2/USB3TP4 A31 PETN2/USB3TN4 B31 PERP2/USB3RP4 G15 USB3RN1 G20 USB3RP1 H20 USB3TN1 C33 USB3TP1 B34 USB3RN2 E18 USB3RP2 F18 USB3TN2 B33 USB3TP2 A33 C9 .1U_0402_16V7K DIS@ C9 .1U_0402_16V7K DIS@ 1 2 RC113 3K_0402_1% RC113 3K_0402_1% 1 2 CC14 0.1U_0402_16V7K CC14 0.1U_0402_16V7K 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. <EDP_COMP power rail> VCC_SENSE SVID ALERT Layout notes DG V0.5 H_CPU_SVIDALRT# RC154 close to CPU<300mil Max length=1000~2000mil L SVID DATA Layout notes DG V0.5 VIDSOUT RC156 close to CPU<500mil Max length=1000~2000mil L <PWR VR12.6> 2500mA 600mA <PWR VR12.6> <PWR VR12.6> +VCC_CORE@10000mA <VR IV and CPU> <CPU> PV:RC223,RG124 change to 0-ohm shortpad H_CPU_SVIDALRT# VR_SVID_DAT VR_SVID_CLK CPU_PWR_DEBUG H_CPU_SVIDALRT# VR_SVID_DAT VR12.6PG_MCP VCCSENSE VR12.6PG_MCP VR_SVID_CLK <51> VR_SVID_ALRT# <51> VR_SVID_DAT <51> VR_ON <51> +1.05VS_PG <4,6> VCCSENSE <51> CPU_PWR_DEBUG <6> +VCC_CORE <34,51,52> +1.35V_VDDQ <15,16,17,34,4,49> +1.05VS_VCCST <4,6,9> +VCCIO_OUT <4,6> +VCCIOA_OUT <4> +1.05VS <12,24,25,28,34,37,50,51> VGATE <51> +VCC_CORE +1.35V_VDDQ +VCC_CORE +VCCIOA_OUT +VCC_CORE +1.35V_VDDQ +1.35V_VDDQ +1.05VS +1.05VS_VCCST +1.05VS_VCCST +1.05VS_VCCST +1.05VS_VCCST +3V_PCH +VCCIO_OUT +1.05VS +VCCIO_OUT +1.05VS_VCCST +VCC_CORE +1.35V_VDDQ +1.05VS_VCCST +VCCIO_OUT +VCCIOA_OUT +1.05VS +1.05VS_VCCST Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power Custom 11 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power Custom 11 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power Custom 11 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P CC27 10U_0603_6.3V6M @ CC27 10U_0603_6.3V6M @ 1 2 CC26 10U_0603_6.3V6M CC26 10U_0603_6.3V6M 1 2 CC72 1U_0402_6.3V6K @ CC72 1U_0402_6.3V6K @ 1 2 + CC24 330U_2.5V_M @ + CC24 330U_2.5V_M @ 1 2 RC154 75_0402_5% RC154 75_0402_5% 1 2 CC21 2.2U_0402_6.3V6M @ CC21 2.2U_0402_6.3V6M @ 1 2 CC22 2.2U_0402_6.3V6M CC22 2.2U_0402_6.3V6M 1 2 CC30 10U_0603_6.3V6M CC30 10U_0603_6.3V6M 1 2 + CC25 330U_2.5V_M @ + CC25 330U_2.5V_M @ 1 2 CC23 2.2U_0402_6.3V6M CC23 2.2U_0402_6.3V6M 1 2 RC167 10K_0402_5% @ RC167 10K_0402_5% @ 1 2 RC294 0_0402_5% @ RC294 0_0402_5% @ 1 2 CC28 10U_0603_6.3V6M CC28 10U_0603_6.3V6M 1 2 RC166 150_0402_5% RC166 150_0402_5% 1 2 CC31 10U_0603_6.3V6M @ CC31 10U_0603_6.3V6M @ 1 2 CC20 2.2U_0402_6.3V6M CC20 2.2U_0402_6.3V6M 1 2 RC155 43_0402_1% RC155 43_0402_1% 1 2 RC156 110_0402_1% RC156 110_0402_1% 1 2 RC288 10K_0402_5% @ RC288 10K_0402_5% @ 1 2 CC71 22U_0805_6.3V6M CC71 22U_0805_6.3V6M 1 2 BDW_ULT_DDR3L(Interleaved) HSW ULT POWER 12 OF 19 UCPU1L BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) HSW ULT POWER 12 OF 19 UCPU1L BDW-ULT-DDR3L-IL_BGA1168 VCCIO_OUT A59 VCCIOA_OUT E20 RSVD AD23 RSVD AB23 RSVD AC58 VCC F59 VDDQ AY44 VDDQ AY40 VDDQ AY35 RSVD AA59 RSVD U59 RSVD V59 RSVD AG58 RSVD AC59 RSVD AE60 RSVD AD59 VCCST AC22 VDDQ AY50 RSVD N58 VCC_SENSE E63 RSVD AA23 RSVD AE59 VCCST_PWRGD B59 VR_READY C59 VR_EN F60 VDDQ AR48 VDDQ AP43 VDDQ AN33 VDDQ AJ37 VDDQ AJ33 VDDQ AJ31 VDDQ AH26 RSVD J58 RSVD L59 VCC C24 VCC C28 VCC C32 VCC AG57 VCC W57 VCC U57 VCC M23 VCC M57 VCC P57 VCC L22 VCC K57 VCC H23 VCC J23 VCC G55 VCC G57 VCC G49 VCC G51 VCC G53 VCC G45 VCC G47 VCC G43 VCC G39 VCC G41 VCC G37 VCC G35 VCC G33 VCC G29 VCC G31 VCC G27 VCC G25 VCC G23 VCC F52 VCC F56 VCC F48 VCC F44 VCC F40 VCC F28 VCC F32 VCC F36 VCC F24 VCC E57 VCC E51 VCC E53 VCC E55 VCC E47 VCC E49 VCC E41 VCC E43 VCC E45 VCC E37 VCC E39 VCC E31 VCC E33 VCC E35 VCC E27 VCC E29 VCC C56 VCC E23 VCC E25 VCC C48 VCC C52 VCC C36 VCC C40 VCC C44 VCC K23 VCC AD57 VCC AB57 VCCST AE23 VCCST AE22 VIDSOUT L63 VIDSCLK N63 VIDALERT L62 VSS P62 RSVD_TP P60 RSVD_TP P61 RSVD_TP N59 RSVD_TP N61 RSVD T59 RSVD AD60 VSS D63 PWR_DEBUG H59 RG124 0_0402_5% short@ RG124 0_0402_5% short@ 1 2 RC223 0_0805_5% short@ RC223 0_0805_5% short@ 1 2 UC8 74AUP1G07GW_TSSOP5 @ UC8 74AUP1G07GW_TSSOP5 @ GND 3 A 2 NC 1 VCC 5 Y 4 CC29 10U_0603_6.3V6M @ CC29 10U_0603_6.3V6M @ 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A LA-8661P Total 1.05VS=1838+2274=4111mA Total 1.5VS=3mA Total 1.8VS=7mA Total 3VS=0mA Total 3VALW=200+62=262mA Total 1.05V=540+109=649mA Total 3V_PCH=99mA Use +1.05V Non Deep S3 RC182-->SMT Deep S3 RC285-->SMT Deep S3 and Non Deep S3 SPI ROM power rail 1.838A 41mA 42mA 57mA 1.6A 0.658A 65mA 18mA 31mA 62mA 124mA PV:RC168,RC172,RC280,RC281,RC285,RC196,RC175,RC178 change to 0-ohm shortpad +3V_1V8_SDIO +3V_DSW_P +RTCVCC +1.05VS_VCCHSIO +1.05V_DCPSUS +1.05VS_APPLOPI +1.05V_AOSCSUS +1.05VS_AXCK_LCPLL +VCCSUSHDA +1.05VS_VCCSATA3PLL +1.05VS_VCCASW +1.05VS_APPLOPI +1.05V_DCPSUS +1.05VS_VCCUSB3PLL +1.05VS_AXCKDCB +3V_DSW_PRTCSUS +1.05VS_VCCUSB3PLL +1.05VS_VCCSATA3PLL +1.05VS_AXCKDCB +1.05VS_AXCK_LCPLL +1.05V_AOSCSUS +3V_DSW_P +V1.05S_SSCF100 +V1.05S_SSCFF +V1.05S_SSCF100 +V1.05S_SSCFF +3V_PCH <10,11,24,36,4,6,7,9> +RTCVCC <28,6,8> +1.05VS <11,24,25,28,34,37,50,51> +1.5VS <23,37,53,6> +3VS <15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +1.05V <24> +3VALW <19,22,24,25,26,28,29,32,37,48,50,53,56,7> +3V_DSW_P <8,9> +1.05VS_MODPHY <24,34> +1.05VS_VCCSATA3PLL <34,6> +1.05VS_APPLOPI <34> +1.05VS +RTCVCC +3VS +3VS +1.05VS +3V_PCH +3V_PCH +1.05VS +3VS +1.5VS +1.05VS +1.05VS +1.05VS +1.05VS +1.05VS +1.05VS +3V_PCH +1.5VS +1.05VS_MODPHY +1.05VS_MODPHY +1.05VS_MODPHY +1.05V +1.05V +1.05VS +1.05VS_AXCK_LCPLL +1.05VS_VCCUSB3PLL +1.05VS_VCCSATA3PLL +3VALW +3V_DSW_P +3V_PCH +3V_PCH +3V_PCH +RTCVCC +1.05VS +1.5VS +3VS +1.05V +1.05VS_MODPHY +3VALW +3V_DSW_P +1.05VS_VCCSATA3PLL +1.05VS_APPLOPI Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power C 12 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power C 12 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power C 12 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P RC179 2.2UH_LQM2MPN2R2NG0L_30% RC179 2.2UH_LQM2MPN2R2NG0L_30% 1 2 RC280 0_0603_5% short@ RC280 0_0603_5% short@ 1 2 CC40 0.1U_0402_16V7K CC40 0.1U_0402_16V7K 1 2 CC46 1U_0402_6.3V6K CC46 1U_0402_6.3V6K 1 2 CC76 0.1U_0402_16V7K CC76 0.1U_0402_16V7K 1 2 RC174 5.11_0402_1% RC174 5.11_0402_1% 1 2 CC69 1U_0402_6.3V6K CC69 1U_0402_6.3V6K 1 2 CC45 10U_0603_6.3V6M CC45 10U_0603_6.3V6M 1 2 CC43 1U_0402_6.3V6K CC43 1U_0402_6.3V6K 1 2 RC175 0_0805_5% short@ RC175 0_0805_5% short@ 1 2 CC68 47U_0805_6.3V6M CC68 47U_0805_6.3V6M 1 2 RC281 0_0603_5% short@ RC281 0_0603_5% short@ 1 2 RC168 0_0805_5% short@ RC168 0_0805_5% short@ 1 2 CC49 1U_0402_6.3V6K CC49 1U_0402_6.3V6K 1 2 CC42 47U_0805_6.3V6M CC42 47U_0805_6.3V6M 1 2 RC181 2.2UH_LQM2MPN2R2NG0L_30% RC181 2.2UH_LQM2MPN2R2NG0L_30% 1 2 CC61 1U_0402_6.3V6K CC61 1U_0402_6.3V6K 1 2 CC53 1U_0402_6.3V6K CC53 1U_0402_6.3V6K 1 2 CC65 1U_0402_6.3V6K CC65 1U_0402_6.3V6K 1 2 CC39 1U_0402_6.3V6K CC39 1U_0402_6.3V6K 1 2 CC62 1U_0402_6.3V6K CC62 1U_0402_6.3V6K 1 2 CC50 10U_0603_6.3V6M CC50 10U_0603_6.3V6M 1 2 CC41 1U_0402_6.3V6K CC41 1U_0402_6.3V6K 1 2 CC66 1U_0402_6.3V6K @ CC66 1U_0402_6.3V6K @ 1 2 RC182 0_0402_5% @ RC182 0_0402_5% @ 1 2 CC64 1U_0402_6.3V6K CC64 1U_0402_6.3V6K 1 2 CC34 1U_0402_6.3V6K CC34 1U_0402_6.3V6K 1 2 CC51 1U_0402_6.3V6K CC51 1U_0402_6.3V6K 1 2 CC35 47U_0805_6.3V6M CC35 47U_0805_6.3V6M 1 2 CC37 0.1U_0402_16V7K @ CC37 0.1U_0402_16V7K @ 1 2 CC52 1U_0402_6.3V6K CC52 1U_0402_6.3V6K 1 2 CC60 1U_0402_6.3V6K CC60 1U_0402_6.3V6K 1 2 RC285 0_0402_5% short@ RC285 0_0402_5% short@ 1 2 USB2 THERMAL SENSOR HSIO BDW_ULT_DDR3L(Interleaved) USB3 OPI RTC GPIO/LPC VRM HDA SERIAL IO SUS OSCILLATOR SPI LPT LP POWER CORE 13 OF 19 UCPU1M BDW-ULT-DDR3L-IL_BGA1168 USB2 THERMAL SENSOR HSIO BDW_ULT_DDR3L(Interleaved) USB3 OPI RTC GPIO/LPC VRM HDA SERIAL IO SUS OSCILLATOR SPI LPT LP POWER CORE 13 OF 19 UCPU1M BDW-ULT-DDR3L-IL_BGA1168 VCCHDA AH14 VCCTS1_5 J15 DCPSUS1 AD8 DCPSUS1 AD10 DCPSUSBYP AG20 DCPSUSBYP AG19 DCPSUS4 AB8 VCCASW AE9 VCCASW AF9 VCCASW AG8 VCCSUS3_3 AH11 VCCRTC AG10 DCPRTC AE7 VCCSPI Y8 VCCASW AG14 VCCASW AG13 VCC3_3 K16 VCC3_3 K14 VCCSDIO T9 VCCSDIO U8 DCPSUS3 J13 VCCAPLL W21 VCCHSIO K9 VCCHSIO L10 VCCHSIO M9 VCCAPLL AA21 RSVD Y20 VCCSATA3PLL B11 VCCUSB3PLL B18 VCC1_05 N8 VCC1_05 P9 VCC1_05 J11 VCC1_05 H11 VCC1_05 H15 VCC1_05 AE8 VCC1_05 AF22 VCCSUS3_3 AE21 VCCSUS3_3 AE20 RSVD V21 RSVD M20 RSVD K18 VCCCLK T21 VCCCLK R21 VCCCLK J17 VCCACLKPLL A20 VCC3_3 W9 VCC3_3 V8 VCCDSW3_3 AH10 VCCSUS3_3 AC9 RSVD AC20 VCCSUS3_3 AA9 DCPSUS2 AH13 VCC1_05 AG16 VCC1_05 AG17 VCCCLK J18 VCCCLK K19 CC67 100U_1206_6.3V6K @ CC67 100U_1206_6.3V6K @ 1 2 CC54 22U_0805_6.3V6M CC54 22U_0805_6.3V6M 1 2 CC32 1U_0402_6.3V6K CC32 1U_0402_6.3V6K 1 2 CC55 22U_0805_6.3V6M CC55 22U_0805_6.3V6M 1 2 CC48 1U_0402_6.3V6K CC48 1U_0402_6.3V6K 1 2 CC58 1U_0402_6.3V6K CC58 1U_0402_6.3V6K 1 2 CC59 22U_0805_6.3V6M CC59 22U_0805_6.3V6M 1 2 CC57 22U_0805_6.3V6M CC57 22U_0805_6.3V6M 1 2 CC36 1U_0402_6.3V6K CC36 1U_0402_6.3V6K 1 2 RC178 0_0603_5% short@ RC178 0_0603_5% short@ 1 2 CC44 0.1U_0402_16V7K @ CC44 0.1U_0402_16V7K @ 1 2 RC169 0_0402_5% short@ RC169 0_0402_5% short@ 1 2 RC180 2.2UH_LQM2MPN2R2NG0L_30% @ RC180 2.2UH_LQM2MPN2R2NG0L_30% @ 1 2 RC176 2.2UH_LQM2MPN2R2NG0L_30% RC176 2.2UH_LQM2MPN2R2NG0L_30% 1 2 RC173 0_0402_5% @ RC173 0_0402_5% @ 1 2 CC63 47U_0805_6.3V6M CC63 47U_0805_6.3V6M 1 2 RC172 0_0402_5% short@ RC172 0_0402_5% short@ 1 2 CC70 1U_0402_6.3V6K CC70 1U_0402_6.3V6K 1 2 RC171 2.2UH_LQM2MPN2R2NG0L_30% RC171 2.2UH_LQM2MPN2R2NG0L_30% 1 2 RC170 2.2UH_LQM2MPN2R2NG0L_30% RC170 2.2UH_LQM2MPN2R2NG0L_30% 1 2 CC33 1U_0402_6.3V6K CC33 1U_0402_6.3V6K 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A <PWR VR12.6> VSSSENSE <51> Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GND/VSSSEN 13 61 Saturday, January 31, 2015 2010/05/27 2011/05/11 Compal Electronics, Inc. LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GND/VSSSEN 13 61 Saturday, January 31, 2015 2010/05/27 2011/05/11 Compal Electronics, Inc. LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GND/VSSSEN 13 61 Saturday, January 31, 2015 2010/05/27 2011/05/11 Compal Electronics, Inc. LA-C701P BDW_ULT_DDR3L(Interleaved) 15 OF 19 UCPU1O BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 15 OF 19 UCPU1O BDW-ULT-DDR3L-IL_BGA1168 VSS AV16 VSS AV24 VSS AV33 VSS AV28 VSS AV20 VSS AR11 VSS AU33 VSS AU55 VSS D26 VSS D27 VSS D25 VSS D23 VSS AV55 VSS AP38 VSS AP29 VSS AP31 VSS AP39 VSS AP52 VSS AP54 VSS AP57 VSS AR15 VSS AR17 VSS AR23 VSS AR31 VSS AR33 VSS AR39 VSS AR43 VSS AR49 VSS AR5 VSS AR52 VSS AT13 VSS AT35 VSS AT37 VSS AT40 VSS AT42 VSS AT43 VSS AT46 VSS AT49 VSS AT61 VSS AT62 VSS AT63 VSS AU1 VSS AU18 VSS AU22 VSS AU30 VSS AU51 VSS AU53 VSS AU57 VSS AU59 VSS AV14 VSS AV36 VSS AV39 VSS AV41 VSS AV43 VSS AV46 VSS AV49 VSS AV51 VSS AW24 VSS AW33 VSS AW35 VSS AW37 VSS AW4 VSS AW42 VSS AW44 VSS AW47 VSS AW50 VSS AW51 VSS AW59 VSS AY11 VSS AY16 VSS AY18 VSS AY22 VSS AY24 VSS AY26 VSS AY30 VSS AY33 VSS AY4 VSS AY51 VSS AY53 VSS AY57 VSS AY59 VSS AY6 VSS B20 VSS B24 VSS B26 VSS B28 VSS B32 VSS B36 VSS B4 VSS B40 VSS B44 VSS B48 VSS B52 VSS B56 VSS B60 VSS C18 VSS C20 VSS C25 VSS C27 VSS C38 VSS C39 VSS C57 VSS D12 VSS D14 VSS D18 VSS D2 VSS D21 VSS D29 VSS D30 VSS D31 VSS AV34 VSS AV59 VSS AV8 VSS AW16 VSS AW40 VSS AW60 VSS C11 VSS C14 VSS AU28 VSS AU26 VSS AU24 VSS AU20 VSS AU16 VSS AP48 VSS AP26 VSS AP22 VSS AP23 VSS AP3 BDW_ULT_DDR3L(Interleaved) 14 OF 19 UCPU1N BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 14 OF 19 UCPU1N BDW-ULT-DDR3L-IL_BGA1168 VSS AH44 VSS AH49 VSS AH51 VSS AH38 VSS AP10 VSS AN49 VSS AN40 VSS AN23 VSS AM1 VSS AL51 VSS A28 VSS A11 VSS A14 VSS A18 VSS A24 VSS A32 VSS A36 VSS A40 VSS A44 VSS A48 VSS A52 VSS A56 VSS AA1 VSS AA58 VSS AB10 VSS AB20 VSS AB22 VSS AB7 VSS AC61 VSS AD21 VSS AD3 VSS AD63 VSS AE10 VSS AE5 VSS AE58 VSS AF11 VSS AF12 VSS AF14 VSS AF17 VSS AG1 VSS AG11 VSS AG23 VSS AG60 VSS AG62 VSS AG63 VSS AH19 VSS AH24 VSS AH28 VSS AH30 VSS AH32 VSS AH40 VSS AH42 VSS AH53 VSS AH55 VSS AH57 VSS AJ13 VSS AJ14 VSS AJ23 VSS AJ25 VSS AJ27 VSS AJ29 VSS AJ43 VSS AJ45 VSS AJ50 VSS AJ52 VSS AJ56 VSS AJ58 VSS AJ60 VSS AJ63 VSS AK23 VSS AK3 VSS AK52 VSS AL10 VSS AL13 VSS AL17 VSS AL20 VSS AL22 VSS AL23 VSS AL26 VSS AL29 VSS AL31 VSS AL33 VSS AL36 VSS AL39 VSS AL40 VSS AL45 VSS AL46 VSS AL52 VSS AL54 VSS AL57 VSS AL60 VSS AL61 VSS AM17 VSS AM23 VSS AM31 VSS AM52 VSS AN17 VSS AN31 VSS AN32 VSS AN35 VSS AN36 VSS AN39 VSS AN42 VSS AN43 VSS AN45 VSS AN46 VSS AN48 VSS AN51 VSS AN52 VSS AN60 VSS AN63 VSS AN7 VSS AP17 VSS AP20 VSS AF18 VSS AF15 VSS AJ54 VSS AJ47 VSS AJ35 VSS AJ41 VSS AJ39 VSS AH36 VSS AH34 VSS AH22 VSS AH20 VSS AH17 VSS AG61 VSS AG21 BDW_ULT_DDR3L(Interleaved) 16 OF 19 UCPU1P BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 16 OF 19 UCPU1P BDW-ULT-DDR3L-IL_BGA1168 VSS D59 VSS Y63 VSS Y59 VSS Y10 VSS V10 VSS U9 VSS U22 VSS U61 VSS U20 VSS T58 VSS T1 VSS R22 VSS R8 VSS R10 VSS P63 VSS P59 VSS N3 VSS N10 VSS M22 VSS L61 VSS L58 VSS L20 VSS L18 VSS L17 VSS L15 VSS L13 VSS K12 VSS K1 VSS J63 VSS J59 VSS J22 VSS H17 VSS F38 VSS F50 VSS AH16 VSS F42 VSS F34 VSS E17 VSS G22 VSS G6 VSS D39 VSS D38 VSS D37 VSS D35 VSS D34 VSS D43 VSS D45 VSS D46 VSS D47 VSS D5 VSS D50 VSS D51 VSS D53 VSS D54 VSS D55 VSS D57 VSS D62 VSS D8 VSS E11 VSS F46 VSS F54 VSS F58 VSS F61 VSS G18 VSS G3 VSS G5 VSS G8 VSS H13 VSS D42 VSS D41 VSS H57 VSS L7 VSS D33 VSS J10 VSS V58 VSS AH46 VSS V23 VSS_SENSE E62 VSS W22 VSS W20 VSS V7 VSS V3 VSS D49 VSS F30 VSS F26 VSS F20
5 5 4 4 3 3 2 2 1 1 D D C C B B A A CFG4 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port Display Port Presence Strap * Layout notes DG V0.9 PROC_OPI_COMP Width=12mil,spacing=12mil Max length=500mil L CFG_RCOMP PROC_OPI_COMP TD_IREF CFG4 TP_DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY61_AW61 DC_TEST_AY61_AW62 DC_TEST_AY61_AW62 DC_TEST_A61_B61 DC_TEST_AY2_AW2 TP_DC_TEST_A3_B3 DC_TEST_AY61_AW61 DC_TEST_B62_B63 DC_TEST_AY3_AW3 DC_TEST_C1_C2 MCP_RSVD_29 CFG0 CFG10 CFG11 CFG14 CFG15 CFG1 CFG2 CFG0 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG12 CFG13 CFG17 CFG19 CFG16 CFG18 CFG0 <6> CFG1 <6> CFG2 <6> CFG3 <6> CFG4 <6> CFG5 <6> CFG6 <6> CFG7 <6> CFG8 <6> CFG9 <6> CFG10 <6> CFG11 <6> CFG12 <6> CFG13 <6> CFG14 <6> CFG15 <6> CFG16 <6> CFG18 <6> CFG17 <6> CFG19 <6> Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 14 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. RSVD/CFG Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 14 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. RSVD/CFG Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 14 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. RSVD/CFG RC186 49.9_0402_1% RC186 49.9_0402_1% 1 2 RESERVED BDW_ULT_DDR3L(Interleaved) 19 OF 19 UCPU1S BDW-ULT-DDR3L-IL_BGA1168 RESERVED BDW_ULT_DDR3L(Interleaved) 19 OF 19 UCPU1S BDW-ULT-DDR3L-IL_BGA1168 CFG4 AA60 CFG5 Y62 CFG17 AA61 CFG18 U63 CFG7 Y60 CFG11 U60 RSVD_TP AU63 RSVD_TP C63 RSVD_TP C62 RSVD_TP L60 RSVD_TP B51 RSVD_TP A51 CFG10 V60 CFG9 V61 CFG8 V62 RSVD N60 RSVD Y22 RSVD W23 RSVD D58 RSVD AV62 RSVD_TP AV63 VSS N21 VSS P22 CFG19 U62 RSVD R20 RSVD P20 RSVD J20 CFG3 AA63 CFG2 AC63 CFG1 AC62 CFG16 AA62 CFG15 T60 CFG14 T61 CFG_RCOMP V63 RSVD A5 RSVD E1 RSVD D1 TD_IREF B12 RSVD H18 PROC_OPI_RCOMP AY15 CFG12 T63 CFG13 T62 CFG0 AC60 CFG6 Y61 RSVD B43 BDW_ULT_DDR3L(Interleaved) 18 OF 19 UCPU1R BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 18 OF 19 UCPU1R BDW-ULT-DDR3L-IL_BGA1168 RSVD AY14 RSVD AW14 RSVD AT2 RSVD AU44 RSVD AV44 RSVD D15 RSVD F22 RSVD H22 RSVD J21 RSVD T23 RSVD N23 RSVD R23 RSVD AU15 RSVD AU10 RSVD AM11 RSVD AL1 RSVD U10 RSVD AP7 RC191 8.2K_0402_5% RC191 8.2K_0402_5% 1 2 RC188 49.9_0402_1% RC188 49.9_0402_1% 1 2 RC187 1K_0402_1% @ RC187 1K_0402_1% @ 1 2 BDW_ULT_DDR3L(Interleaved) 17 OF 19 UCPU1Q BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 17 OF 19 UCPU1Q BDW-ULT-DDR3L-IL_BGA1168 DAISY_CHAIN_NCTF_AY2 AY2 DAISY_CHAIN_NCTF_AY60 AY60 DAISY_CHAIN_NCTF_AY61 AY61 DAISY_CHAIN_NCTF_B2 B2 DAISY_CHAIN_NCTF_A3 A3 DAISY_CHAIN_NCTF_A4 A4 DAISY_CHAIN_NCTF_A61 A61 DAISY_CHAIN_NCTF_A60 A60 DAISY_CHAIN_NCTF_AW1 AW1 DAISY_CHAIN_NCTF_AV1 AV1 DAISY_CHAIN_NCTF_A62 A62 DAISY_CHAIN_NCTF_AW2 AW2 DAISY_CHAIN_NCTF_AW3 AW3 DAISY_CHAIN_NCTF_AW61 AW61 DAISY_CHAIN_NCTF_AW63 AW63 DAISY_CHAIN_NCTF_AW62 AW62 DAISY_CHAIN_NCTF_C1 C1 DAISY_CHAIN_NCTF_B62 B62 DAISY_CHAIN_NCTF_B3 B3 DAISY_CHAIN_NCTF_AY3 AY3 DAISY_CHAIN_NCTF_AY62 AY62 DAISY_CHAIN_NCTF_B61 B61 DAISY_CHAIN_NCTF_B63 B63 DAISY_CHAIN_NCTF_C2 C2 RC185 1K_0402_1% RC185 1K_0402_1% 1 2 RC296 49.9_0402_1% @ RC296 49.9_0402_1% @ 1 2 Vinafix
5 5 4 4 3 3 2 2 1 1 D D C C B B A A DIMM_1 H:4mm Reverse SI : pop CD99 +V_VDDR_REFA_CA DDR_CKE0_DIMMA DDR_A_MA3 DDR_CS1_DIMMA# DDR_A_MA7 DDR_A_MA0 DDR_A_MA8 DDR_A_MA6 DDR_A_MA10 DDR_A_MA9 DDR_A_BS2 DDR_A_MA1 DDR_A_BS0 DDR_A_CAS# DDR_A_MA5 DDR_A_MA14 DDR_A_MA4 M_CLK_DDR0 M_CLK_DDR#0 DDR_A_MA13 DDR_A_MA11 DDR_A_MA2 DDR_A_MA12 DDR_A_MA15 DDR_A_WE# DDR_CKE1_DIMMA DDR_A_BS1 DDR_CS0_DIMMA# M_CLK_DDR#1 M_CLK_DDR1 DDR_A_RAS# M_ODT0 PCH_SMBCLK PCH_SMBDATA +V_VDDR_REFA_DQ SM_PG_CTRL M_ODT1 M_ODT3 M_ODT2 M_ODT1 M_ODT0 DDR3_DRAMRST# DDR_A_D17 DDR_A_D16 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D11 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_D27 DDR_A_D6 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D12 DDR_A_D20 DDR_A_D21 DDR_A_D30 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D43 DDR_A_D40 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D48 DDR_A_D32 DDR_A_D56 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D33 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D63 DDR_A_D36 DDR_A_D37 DDR_A_D39 DDR_A_D38 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D54 DDR_A_D55 DDR_A_D0 DDR_A_D4 DDR_A_D1 DDR_A_D14 DDR_A_D13 DDR_A_D9 DDR_A_D15 DDR_A_D18 DDR_A_D19 DDR_A_D23 DDR_A_D22 DDR_A_D24 DDR_A_D28 DDR_A_D25 DDR_A_D26 DDR_A_D31 DDR_A_D29 DDR_A_D34 DDR_A_D35 DDR_A_D41 DDR_A_D44 DDR_A_D42 DDR_A_D46 DDR_A_D45 DDR_A_D47 DDR_A_D49 DDR_A_D52 DDR_A_D5 DDR_A_D50 DDR_A_D51 DDR_A_D53 DDR_A_D57 DDR_A_D60 DDR_A_D58 DDR_A_D61 DDR_A_D59 DDR_A_D62 DDR_A_D10 DDR_A_D7 DDR_A_DQS#[0..7] <5> DDR_A_DQS[0..7] <5> DDR_A_MA[0..15] <5> DDR_A_BS2 <5> DDR_A_BS0 <5> DDR_A_WE# <5> DDR_A_CAS# <5> PCH_SMBDATA <16,18,21,6,7> DDR_A_D[0..63] <5> DDR_CKE1_DIMMA <5> PCH_SMBCLK <16,18,21,6,7> M_CLK_DDR#1 <5> M_CLK_DDR1 <5> DDR_CS0_DIMMA# <5> DDR_A_RAS# <5> DDR_A_BS1 <5> DDR_CKE0_DIMMA <5> M_CLK_DDR0 <5> M_CLK_DDR#0 <5> DDR_CS1_DIMMA# <5> DDR3_DRAMRST# <16,4> M_ODT2 <16> M_ODT3 <16> SM_PG_CTRL <4,49> +1.35V_VDDQ <11,16,17,34,4,49> +0.6V_0.675VS <16,49> +5VALW <19,24,26,29,30,32,34,37,48,49,56> +3VS <12,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +V_VDDR_REFA_CA <16,17> +V_VDDR_REFA_DQ <17> +3VS +V_VDDR_REFA_DQ +V_VDDR_REFA_CA +0.6V_0.675VS +0.6V_0.675VS +1.35V_VDDQ +1.35V_VDDQ +1.35V_VDDQ +1.35V_VDDQ +5VALW +1.35V_VDDQ +1.35V_VDDQ +0.6V_0.675VS +5VALW +3VS +V_VDDR_REFA_CA +V_VDDR_REFA_DQ Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDR3L DIMM0 C 15 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDR3L DIMM0 C 15 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDR3L DIMM0 C 15 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P CD65 1U_0402_6.3V6K CD65 1U_0402_6.3V6K 1 2 G D S QD1 BSS138_NL_SOT23-3 G D S QD1 BSS138_NL_SOT23-3 2 1 3 CD58 1U_0402_6.3V6K @ CD58 1U_0402_6.3V6K @ 1 2 CD66 1U_0402_6.3V6K CD66 1U_0402_6.3V6K 1 2 RD25 2M_0402_5% @ RD25 2M_0402_5% @ 1 2 CD9 10U_0603_6.3V6M @ CD9 10U_0603_6.3V6M @ 1 2 CD57 1U_0402_6.3V6K @ CD57 1U_0402_6.3V6K @ 1 2 CD24 10U_0603_6.3V6M CD24 10U_0603_6.3V6M 1 2 RD20 66.5_0402_1% RD20 66.5_0402_1% 1 2 CD99 0.1U_0402_16V7K ESD@ CD99 0.1U_0402_16V7K ESD@ 1 2 CD1 0.1U_0402_16V7K CD1 0.1U_0402_16V7K 1 2 CD21 0.1U_0402_16V7K CD21 0.1U_0402_16V7K 1 2 CD12 10U_0603_6.3V6M CD12 10U_0603_6.3V6M 1 2 CD63 1U_0402_6.3V6K CD63 1U_0402_6.3V6K 1 2 CD17 0.1U_0402_16V7K CD17 0.1U_0402_16V7K 1 2 CD19 0.1U_0402_16V7K CD19 0.1U_0402_16V7K 1 2 CD7 10U_0603_6.3V6M CD7 10U_0603_6.3V6M 1 2 CD3 0.1U_0402_16V7K CD3 0.1U_0402_16V7K 1 2 CD13 10U_0603_6.3V6M @ CD13 10U_0603_6.3V6M @ 1 2 RD24 66.5_0402_1% RD24 66.5_0402_1% 1 2 RD23 66.5_0402_1% RD23 66.5_0402_1% 1 2 CD56 1U_0402_6.3V6K @ CD56 1U_0402_6.3V6K @ 1 2 CD64 1U_0402_6.3V6K CD64 1U_0402_6.3V6K 1 2 CD8 10U_0603_6.3V6M CD8 10U_0603_6.3V6M 1 2 CD11 10U_0603_6.3V6M @ CD11 10U_0603_6.3V6M @ 1 2 RD21 220K_0402_5% RD21 220K_0402_5% 1 2 CD6 10U_0603_6.3V6M @ CD6 10U_0603_6.3V6M @ 1 2 RD22 66.5_0402_1% RD22 66.5_0402_1% 1 2 CD10 10U_0603_6.3V6M CD10 10U_0603_6.3V6M 1 2 JDIMM1 DEREN_40-42045-20404RHF CONN@ SP070012JA0 JDIMM1 DEREN_40-42045-20404RHF CONN@ SP070012JA0 VREF_DQ 1 VSS1 2 VSS2 3 DQ4 4 DQ0 5 DQ5 6 DQ1 7 VSS3 8 VSS4 9 DQS#0 10 DM0 11 DQS0 12 VSS5 13 VSS6 14 DQ2 15 DQ6 16 DQ3 17 DQ7 18 VSS7 19 VSS8 20 DQ8 21 DQ12 22 DQ9 23 DQ13 24 VSS9 25 VSS10 26 DQS#1 27 DM1 28 DQS1 29 RESET# 30 VSS11 31 VSS12 32 DQ10 33 DQ14 34 DQ11 35 DQ15 36 VSS13 37 VSS14 38 DQ16 39 DQ20 40 DQ17 41 DQ21 42 VSS15 43 VSS16 44 DQS#2 45 DM2 46 DQS2 47 VSS17 48 VSS18 49 DQ22 50 DQ18 51 DQ23 52 DQ19 53 VSS19 54 VSS20 55 DQ28 56 DQ24 57 DQ29 58 DQ25 59 VSS21 60 VSS22 61 DQS#3 62 DM3 63 DQS3 64 VSS23 65 VSS24 66 DQ26 67 DQ30 68 DQ27 69 DQ31 70 VSS25 71 VSS26 72 A12/BC# 83 A11 84 A9 85 A7 86 VDD5 87 VDD6 88 A8 89 A6 90 CKE0 73 CKE1 74 VDD1 75 VDD2 76 NC1 77 A15 78 BA2 79 A14 80 VDD3 81 VDD4 82 A5 91 A4 92 VDD7 93 VDD8 94 A3 95 A2 96 A1 97 A0 98 VDD9 99 VDD10 100 CK0 101 CK1 102 CK0# 103 CK1# 104 VDD11 105 VDD12 106 A10/AP 107 BA1 108 BA0 109 RAS# 110 VDD13 111 VDD14 112 WE# 113 S0# 114 CAS# 115 ODT0 116 VDD15 117 VDD16 118 A13 119 ODT1 120 S1# 121 NC2 122 VDD17 123 VDD18 124 NCTEST 125 VREF_CA 126 VSS27 127 VSS28 128 DQ32 129 DQ36 130 DQ33 131 DQ37 132 VSS29 133 VSS30 134 DQS#4 135 DM4 136 DQS4 137 VSS31 138 VSS32 139 DQ38 140 DQ34 141 DQ39 142 DQ35 143 VSS33 144 VSS34 145 DQ44 146 DQ40 147 DQ45 148 DQ41 149 VSS35 150 VSS36 151 DQS#5 152 DM5 153 DQS5 154 VSS37 155 VSS38 156 DQ42 157 DQ46 158 DQ43 159 DQ47 160 VSS39 161 VSS40 162 DQ48 163 DQ52 164 DQ49 165 DQ53 166 VSS41 167 VSS42 168 DQS#6 169 DM6 170 DQS6 171 VSS43 172 VSS44 173 DQ54 174 DQ50 175 DQ55 176 DQ51 177 VSS45 178 VSS46 179 DQ60 180 DQ56 181 DQ61 182 DQ57 183 VSS47 184 VSS48 185 DQS#7 186 DM7 187 DQS7 188 VSS49 189 VSS50 190 DQ58 191 DQ62 192 DQ59 193 DQ63 194 VSS51 195 VSS52 196 SA0 197 EVENT# 198 VDDSPD 199 SDA 200 SA1 201 SCL 202 VTT1 203 VTT2 204 G1 205 G2 206 CD55 1U_0402_6.3V6K CD55 1U_0402_6.3V6K 1 2
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
AHL50 ABL52 LA-C701P REV 1.0.pdf
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AHL50 ABL52 LA-C701P REV 1.0.pdf

  • 1. A A B B C C D D E E 1 1 2 2 3 3 4 4 Intel ULV Processor with DDRIIIL Broadwell M/B Schematics Document Compal Confidential Date : 2015/01/31 Version 0.3 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Cover Page B 1 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Cover Page B 1 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Cover Page B 1 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc.
  • 2. A A B B C C D D E E 1 1 2 2 3 3 4 4 Model Name : Broadwell File Name : AHL50 / ABL52 LA-C701P Compal Confidential Ultra Light & Thin (BDW ULT) DDR3L 1600MHz 1.35V Dual Channel DDR3L-SO-DIMM X 2 SATA 3.0 USB3.0 port USB2.0 port Camera Port 0 Port 1 USB2.0 Port 3 USB3.0 Port 0 Broadwell SPI ENE KB9022 Int.KBD Touch Pad Lid switch SPI ROM 8M Port 0 Port 1 HDMI Conn HDMI DDPB port 2.5" SATA HDD ODD Port 2 FAN LAN 8166EH 1168P BGA PCI-E WLAN(MiniPCIe slot) P31 SMBUS USB2.0 Port eDPx1 eDP to LVDS Transmitter RTD2132N LVDS panel Card reader RTS5141 Lane 5 PS2 HDA Combo Jack HDA Aduio codec ALC3227 AMD EXO-Pro M330 18W PCI-Ex4 VRAM DDR3 X4 PCI-E USB2.0 Port 3 (Reserved) Lane 7-Lane10 Lane 11 Port 3 Internal SPK 24MHz LPC 33MHz PCIe 1.0:2.5Gb/s PCIe 2.0:5Gb/s GEN1 1.5Gb/s GEN2 3Gb/s GEN3 6Gb/s 2.7Gb/s PCIe 2.0:5Gb/s PCIe 3.0:8Gb/s 297MHz PCIe 1.0:2.5Gb/s PCIe 2.0:5Gb/s 480Mb/s 5Gb/s 1MHz 480Mb/s 50MHz P41~P42 P36~P40 P18 P19 P20 P24 P22 P15~16 P29 P29 P30 P30 P34 P31 P23 P25 P7 WLAN Port 4 DDIx2 CRT Conn P21 P21 TPM P27 SLB 9665 Touch Screen Port 5 P19 P19 P26 Port 6 DP to VGA Transmitter RTD2168 P37 Thermal sensor NCT7718 eDPx1 2.7Gb/s eDP panel FHD P26 P33 On small board eDP@ eDP@ LVDS@ Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Block Diagrams Custom 2 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Block Diagrams Custom 2 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 Block Diagrams Custom 2 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. Dr-Bios.com
  • 3. A A B B C C D D E E 1 1 2 2 3 3 4 4 R=2.2K +3VALW_EC EC_SMB_CK1 EC_SMB_DA1 BAT SMBCLK SMBDATA 2N7002 R=2.2K +3V_PCH R=10K +3VS PCH_SMBCLK PCH_SMBDATA SO-DIMM 0 SO-DIMM 1 SML0CLK SML0DATA R=1K +3V_PCH 2N7002 R=2.2K +3V_PCH R=2.2K +3VS Charger SML1CLK SML1DATA EC_SMB_CK2 EC_SMB_DA2 R=100 EC_SMB_CK2 EC_SMB_DA2 CPU EC AP2 AH1 AN1 AK1 AU3 AH3 77 78 79 80 UK1:+3VALW_EC UCPU1 @ is NO SMT part (empty) PM_SLP_S5#/PM_SLP_S4# X X X X +3V_PCH VIN Power rail SUSP# X Source (CPU) X SUSP# +0.6V_0.675VS X X PM_SLP_S3# +3VALW_EC +3VALW SUSP# +5VS X SUSP# VR12.5_VR_ON X EC_ON +1.05VS +3VL +3VS PCH_PWR_EN +RTCVCC +5VALW X B+ SYSON PM_SLP_S3# +VCC_CORE PM_SLP_S3# X X +1.5VS +VL EC_ON BATT+ SUSP# X X X PM_SLP_S3# X Control (EC) EC_ON +1.35V_VDDQ RF@ : RF team request, must add. EMI@ : EMI team request, must add. ESD@ : ESD team request, must add. LVDS@ : Support LVDS panel. @EMI@,@ESD@,@RF@ : Reserve , don't pop. DIS@ : for AMD EXO <USB2.0 port> USB2.0 port DESTINATION 0 1 USB 2.0/3.0(left side) USB 2.0(right side) UMA Dis USB 2.0/3.0(left side) USB 2.0(left side) WLAN/BT 2 3 Camera 4 5 6 7 Touch screen X USB 2.0(left side) USB 2.0(right side) WLAN/BT Camera X eDP to LVDS bridge RTD2132R +3VS_RT Touch screen GCLK@ : Support GCLK GCLKUMA@ : UMA GCLKDIS@: DIS eDP@ : Support eDP panel 2N7002 +3VS_VGA R=2.2K GPU XDP Thermal Sensor for GPU Card reader Card reader DP to VGA RTD2168 +3VS_CRT USB3.0 0 <PCI-E,SATA,USB3.0> USB3.0 Dis DESTINATION Lane# 1 USB3.0 UMA HDD DESTINATION Dis SATA 0 1 Lane# UMA ODD ODD HDD Dis PCIE 0 WLAN Lane# DESTINATION UMA LAN 1 2 LAN WLAN 3 Dis PEG 0 Lane# DESTINATION UMA 1 GPU 3 2 2 PR2 PR2 RC72 RC73 QC2 RC78 RC79 QC6 VGA_SMB_CK3 VGA_SMB_DA3 DIS@ Q2416 DIS@ R327 R328 +3VS_VGA CIICSCL1 CIICSDA1 R=0 R=0 RTD2168_SMB_SCL RTD2168_SMB_SDA @ 0 ohm @ 0 ohm Touch Pad TP_SMBCLK TP_SMBDATA +3V_PCH 2N7002 R=2.2K +3VS QC7 Dis Lane# PCIE REQ UMA DESTINATION 0 1 2 3 GPU LAN LAN WLAN WLAN 4 5 PU PU PU PU X X X XTAL@ : for HSW SMT in DB phase only TP@ : TP SMBus Board ID control 15K ohm RK4 SI DB MV PV RK4 UMA 15" 0 ohm 43K ohm 27K ohm DIS 12k ohm 56k ohm 33k ohm 20k ohm SPI@ : SPI ROM request UMA@ : for UMA only 8111@ : for LAN giga 8166@ : for LAN 10/100 83 84 2N7002 Thermal Sensor for CPU EC_SMB_CK3 EC_SMB_DA3 R=10K R=2.2K +3VS_VGA +3VS Thermal Sensor CPU internal : PECI protocal PCH internal : 0x90 GPU internal : 0x82 CPU external : 0x98 GPU external : 0x98 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Notes List Custom 3 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Notes List Custom 3 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Notes List Custom 3 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. LA-C701P
  • 4. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A LA-8661P Compal Electronics, Inc. <HDMI> <eDP> DDR3 COMPENSATION SIGNALS Layout notes DG V0.5 Trace width=12~15 mil Max length=500mil L COMPENSATION PU FOR eDP <eDP> Layout notes DG V0.9 PEG_COMP Trace width=20mil and spacing=25mil Max length=100mil L <DP TO CRT> remove BKL_PWM_CPU 20141113 DB phase For XDP 20151112 DB phase : add eDP Lan1 for FHD 20141117 SI : pop CC88 SI : pop CC99 SI : pop C295 DDR3_DRAMRST# XDP_TCK XDP_TDO_CPU XDP_TRST#_CPU XDP_TMS_CPU XDP_TDI_CPU XDP_PRDY# XDP_PREQ# PROC_DETECT# XDP_TRST#_CPU XDP_OBS3_R XDP_OBS5_R XDP_OBS2_R XDP_OBS4_R XDP_OBS6_R XDP_OBS7_R DDR3_DRAMRST# XDP_TDI_CPU XDP_PREQ# SM_RCOMP2 SM_RCOMP0 SM_RCOMP1 DDR_PG_CNTL EDP_COMP EDP_COMP PROCHOT# DDR_PG_CNTL H_PROCHOT#_R H_CPUPWRGD_R SM_RCOMP1 SM_RCOMP2 SM_RCOMP0 H_CPUPWRGD_R +1.05VS_VCCST <11,6,9> +1.35V_VDDQ <11,15,16,17,34,49> +3V_PCH <10,11,12,24,36,6,7,9> +VCCIOA_OUT <11> +VCCIO_OUT <11,6> PCH_DPC_P1 <21> PCH_DPC_N1 <21> PCH_DPC_P0 <21> PCH_DPC_N0 <21> XDP_TDI_CPU <6> XDP_TDO_CPU <6> XDP_TMS_CPU <6> XDP_TRST#_CPU <6> PCH_DPB_N3 <20> PCH_DPB_P3 <20> XDP_TCK <6> +1.05VS_PG <11,6> DDR3_DRAMRST# <15,16> PCH_DPB_N0 <20> PCH_DPB_P0 <20> PCH_DPB_N2 <20> PCH_DPB_P2 <20> PCH_DPB_N1 <20> PCH_DPB_P1 <20> EDP_CPU_LANE_N0_C <18> EDP_CPU_LANE_P0_C <18> EDP_CPU_AUX#_C <18> EDP_CPU_AUX_C <18> SM_PG_CTRL <15,49> H_PECI <25> PROCHOT# <25> H_CPUPWRGD_R <6> XDP_PRDY# <6> XDP_PREQ# <6> XDP_OBS0_R <6> XDP_OBS1_R <6> EDP_CPU_LANE_N1_C <18> EDP_CPU_LANE_P1_C <18> +1.05VS_VCCST +1.35V_VDDQ +3V_PCH +VCCIOA_OUT +VCCIO_OUT +1.35V_VDDQ +1.05VS_VCCST +VCCIOA_OUT +1.35V_VDDQ +VCCIO_OUT +3V_PCH Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDI,MSIC,XDP C 4 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDI,MSIC,XDP C 4 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDI,MSIC,XDP C 4 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P BDW_ULT_DDR3L(Interleaved) EDP DDI 1 OF 19 UCPU1A BDW-ULT-DDR3L-IL_BGA1168 SA011306191 BDW_ULT_DDR3L(Interleaved) EDP DDI 1 OF 19 UCPU1A BDW-ULT-DDR3L-IL_BGA1168 SA011306191 DDI1_TXN0 C54 DDI1_TXP0 C55 DDI1_TXN1 B58 DDI1_TXP1 C58 DDI1_TXN2 B55 DDI1_TXP2 A55 DDI1_TXN3 A57 EDP_TXP0 B46 EDP_TXN0 C45 EDP_TXN1 A47 EDP_TXP1 B47 EDP_TXN2 C47 EDP_TXP2 C46 EDP_TXN3 A49 EDP_TXP3 B49 EDP_AUXP B45 EDP_AUXN A45 DDI1_TXP3 B57 DDI2_TXP1 B54 DDI2_TXP0 C50 DDI2_TXN0 C51 DDI2_TXN1 C53 DDI2_TXN2 C49 DDI2_TXP2 B50 DDI2_TXN3 A53 DDI2_TXP3 B53 EDP_RCOMP D20 EDP_DISP_UTIL A43 RC308 470_0402_5% RC308 470_0402_5% 1 2 RC19 120_0402_1% RC19 120_0402_1% 1 2 UC10 74AUP1G07GW_TSSOP5 SA00004BV00 UC10 74AUP1G07GW_TSSOP5 SA00004BV00 GND 3 A 2 NC 1 VCC 5 Y 4 RC13 51_0402_1% @ RC13 51_0402_1% @ 1 2 T51 PAD @ T51 PAD @ CC88 0.1U_0402_16V7K ESD@ CC88 0.1U_0402_16V7K ESD@ 1 2 C295 10P_0402_50V8J ESD@ C295 10P_0402_50V8J ESD@ 1 2 RC7 1K_0402_1% @ RC7 1K_0402_1% @ 1 2 RC3 24.9_0402_1% RC3 24.9_0402_1% 1 2 T57 PAD @ T57 PAD @ T55 PAD @ T55 PAD @ CC99 0.1U_0402_16V7K ESD@ CC99 0.1U_0402_16V7K ESD@ 1 2 DDR3L BDW_ULT_DDR3L(Interleaved) MISC THERMAL PWR JTAG 2 OF 19 UCPU1B BDW-ULT-DDR3L-IL_BGA1168 SA011306191 DDR3L BDW_ULT_DDR3L(Interleaved) MISC THERMAL PWR JTAG 2 OF 19 UCPU1B BDW-ULT-DDR3L-IL_BGA1168 SA011306191 BPM#4 K59 BPM#5 H63 BPM#6 K60 SM_RCOMP0 AU60 BPM#7 J61 BPM#3 H62 BPM#1 H60 BPM#2 H61 BPM#0 J60 PROC_TDO F62 PROC_TDI F63 PROC_TMS E61 PECI N62 CATERR K61 PROCPWRGD C61 PROCHOT K63 PROC_TRST E59 PROC_TCK E60 PRDY J62 PREQ K62 SM_PG_CNTL1 AV61 SM_DRAMRST AV15 SM_RCOMP2 AU61 SM_RCOMP1 AV60 PROC_DETECT D61 T54 PAD @ T54 PAD @ T56 PAD @ T56 PAD @ RC20 100_0402_1% RC20 100_0402_1% 1 2 RC6 56_0402_5% RC6 56_0402_5% 1 2 T53 PAD @ T53 PAD @ RC18 200_0402_1% RC18 200_0402_1% 1 2 T52 PAD @ T52 PAD @ RC234 10K_0402_5% RC234 10K_0402_5% 1 2 RC4 62_0402_5% RC4 62_0402_5% 1 2 RC11 10K_0402_5% RC11 10K_0402_5% 1 2 RC12 51_0402_1% @ RC12 51_0402_1% @ 1 2
  • 5. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. <DDR3L> <DDR3L> Interleaved Memory DDR_A_D63 DDR_A_D62 DDR_A_D8 DDR_A_D3 DDR_A_D4 DDR_A_D7 DDR_A_D5 DDR_A_D6 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D47 DDR_A_D46 DDR_A_D42 DDR_A_D43 DDR_A_D34 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_D35 DDR_A_D41 DDR_A_D40 DDR_A_D38 DDR_A_D36 DDR_A_D37 DDR_A_D32 DDR_A_D33 DDR_A_D61 DDR_A_D60 DDR_A_D2 DDR_A_D1 DDR_A_D0 DDR_A_D55 DDR_A_D54 DDR_A_D51 DDR_A_D48 DDR_A_D50 DDR_A_D49 DDR_A_D52 DDR_A_D53 DDR_A_D31 DDR_A_D14 DDR_A_D15 DDR_A_D25 DDR_A_D24 DDR_A_D26 DDR_A_D27 DDR_A_D30 DDR_A_D9 DDR_A_D13 DDR_A_D12 DDR_A_D10 DDR_A_D11 DDR_A_D29 DDR_A_D28 DDR_A_D19 DDR_A_D20 DDR_A_D16 DDR_A_D21 DDR_A_D17 DDR_A_D22 DDR_A_D18 DDR_A_D23 DDR_A_DQS#7 DDR_A_DQS#0 DDR_A_DQS#2 DDR_A_DQS#5 DDR_A_DQS#3 DDR_A_DQS#1 DDR_A_DQS#4 DDR_A_DQS#6 DDR_A_DQS0 DDR_A_DQS2 DDR_A_DQS1 DDR_A_DQS6 DDR_A_DQS5 DDR_A_DQS4 DDR_A_DQS3 DDR_A_DQS7 DDR_B_D33 DDR_B_D42 DDR_B_D14 DDR_B_D55 DDR_B_D43 DDR_B_D63 DDR_B_D59 DDR_B_D34 DDR_B_D24 DDR_B_D29 DDR_B_D53 DDR_B_D10 DDR_B_D13 DDR_B_D26 DDR_B_D4 DDR_B_D44 DDR_B_D57 DDR_B_D11 DDR_B_D21 DDR_B_D3 DDR_B_D46 DDR_B_D7 DDR_B_D0 DDR_B_D35 DDR_B_D30 DDR_B_D27 DDR_B_D15 DDR_B_D25 DDR_B_D23 DDR_B_D49 DDR_B_D40 DDR_B_D36 DDR_B_D48 DDR_B_D37 DDR_B_D19 DDR_B_D9 DDR_B_D47 DDR_B_D8 DDR_B_D18 DDR_B_D52 DDR_B_D62 DDR_B_D50 DDR_B_D60 DDR_B_D39 DDR_B_D56 DDR_B_D51 DDR_B_D2 DDR_B_D45 DDR_B_D6 DDR_B_D28 DDR_B_D22 DDR_B_D31 DDR_B_D61 DDR_B_D58 DDR_B_D17 DDR_B_D5 DDR_B_D41 DDR_B_D1 DDR_B_D54 DDR_B_D32 DDR_B_D38 DDR_B_D20 DDR_B_D12 DDR_B_D16 DDR_B_DQS#1 DDR_B_DQS#7 DDR_B_DQS#5 DDR_B_DQS#4 DDR_B_DQS#0 DDR_B_DQS#3 DDR_B_DQS#6 DDR_B_DQS#2 DDR_B_DQS7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS5 DDR_B_DQS4 DDR_B_DQS3 DDR_B_DQS2 DDR_B_DQS6 DDR_A_MA15 DDR_A_MA0 DDR_A_MA14 DDR_A_MA5 DDR_A_MA4 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA9 DDR_A_MA7 DDR_A_MA6 DDR_A_MA12 DDR_A_MA13 DDR_A_MA8 DDR_A_MA11 DDR_A_MA10 DDR_B_MA15 DDR_B_MA7 DDR_B_MA0 DDR_B_MA9 DDR_B_MA2 DDR_B_MA13 DDR_B_MA4 DDR_B_MA11 DDR_B_MA10 DDR_B_MA5 DDR_B_MA8 DDR_B_MA6 DDR_B_MA3 DDR_B_MA12 DDR_B_MA1 DDR_B_MA14 DDR_A_D[0..63] <15> DDR_A_DQS#[0..7] <15> DDR_A_DQS[0..7] <15> DDR_B_D[0..63] <16> DDR_B_DQS#[0..7] <16> DDR_B_DQS[0..7] <16> DDR_A_BS0 <15> DDR_A_BS1 <15> DDR_A_BS2 <15> DDR_A_RAS# <15> DDR_A_CAS# <15> DDR_A_WE# <15> DDR_A_MA[0..15] <15> DDR_CS0_DIMMA# <15> DDR_CS1_DIMMA# <15> DDR_CKE0_DIMMA <15> DDR_CKE1_DIMMA <15> M_CLK_DDR#0 <15> M_CLK_DDR0 <15> M_CLK_DDR#1 <15> M_CLK_DDR1 <15> DDR_B_MA[0..15] <16> DDR_CS0_DIMMB# <16> DDR_CS1_DIMMB# <16> DDR_CKE0_DIMMB <16> DDR_CKE1_DIMMB <16> M_CLK_DDR2 <16> M_CLK_DDR#2 <16> M_CLK_DDR#3 <16> M_CLK_DDR3 <16> DDR_B_RAS# <16> DDR_B_BS0 <16> DDR_B_BS1 <16> DDR_B_BS2 <16> DDR_B_CAS# <16> DDR_B_WE# <16> +V_SM_VREF_CNT <17> +V_DDR_REFA_R <17> +V_DDR_REFB_R <17> +V_DDR_REFA_R +V_DDR_REFB_R +V_SM_VREF_CNT +V_SM_VREF_CNT +V_DDR_REFA_R +V_DDR_REFB_R Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDRIII Custom 5 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDRIII Custom 5 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDRIII Custom 5 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P BDW_ULT_DDR3L(Interleaved) DDR CHANNEL B 4 OF 19 UCPU1D BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) DDR CHANNEL B 4 OF 19 UCPU1D BDW-ULT-DDR3L-IL_BGA1168 SB_DQ14 AR54 SB_DQSN5 AN25 SB_DQSN7 AN18 SB_DQSP4 AM28 SB_DQSP5 AM25 SB_DQSP6 AM21 SB_DQSP3 AL49 SB_DQSP7 AM18 SB_DQSP2 AL42 SB_DQSP0 AN58 SB_DQSP1 AN55 SB_DQSN6 AN21 SB_DQSN2 AL43 SB_DQSN3 AL48 SB_DQSN4 AN28 SB_DQSN1 AM55 SB_DQSN0 AM58 SB_MA14 AR46 SB_MA15 AP46 SB_MA13 AK33 SB_MA9 AU46 SB_MA10 AK36 SB_MA11 AV47 SB_MA8 AY47 SB_MA12 AU47 SB_MA4 AR45 SB_MA5 AP45 SB_MA6 AW46 SB_MA3 AR42 SB_MA7 AY46 SB_MA2 AP42 SB_MA0 AP40 SB_MA1 AR40 SB_BA2 AU49 SB_WE AK35 SB_CAS AM33 SB_BA0 AL35 SB_BA1 AM36 SB_RAS AM35 SB_CS#1 AK32 SB_ODT0 AL32 SB_CS#0 AM32 SB_CKE1 AU50 SB_CKE2 AW49 SB_CKE3 AV50 SB_CKE0 AY49 SB_CK#1 AK38 SB_CK1 AL38 SB_CK0 AN38 SB_CK#0 AM38 SB_DQ61 AM20 SB_DQ63 AP18 SB_DQ62 AR18 SB_DQ57 AR20 SB_DQ56 AN20 SB_DQ58 AK18 SB_DQ59 AL18 SB_DQ60 AK20 SB_DQ51 AM22 SB_DQ52 AN22 SB_DQ53 AP21 SB_DQ54 AK21 SB_DQ55 AK22 SB_DQ46 AK25 SB_DQ47 AL25 SB_DQ48 AR21 SB_DQ49 AR22 SB_DQ50 AL21 SB_DQ45 AM26 SB_DQ41 AR26 SB_DQ42 AR25 SB_DQ43 AP25 SB_DQ44 AK26 SB_DQ40 AN26 SB_DQ36 AR29 SB_DQ37 AN29 SB_DQ38 AR28 SB_DQ39 AP28 SB_DQ35 AK28 SB_DQ31 AK51 SB_DQ32 AM29 SB_DQ33 AK29 SB_DQ30 AM51 SB_DQ34 AL28 SB_DQ26 AM49 SB_DQ25 AK46 SB_DQ27 AK49 SB_DQ28 AM48 SB_DQ29 AK48 SB_DQ20 AK45 SB_DQ21 AK43 SB_DQ22 AM40 SB_DQ23 AM42 SB_DQ24 AM46 SB_DQ15 AN54 SB_DQ16 AK40 SB_DQ17 AK42 SB_DQ18 AM43 SB_DQ19 AM45 SB_DQ10 AM54 SB_DQ11 AK54 SB_DQ13 AK55 SB_DQ5 AK58 SB_DQ7 AN57 SB_DQ8 AP55 SB_DQ9 AR55 SB_DQ0 AP58 SB_DQ1 AR58 SB_DQ2 AM57 SB_DQ3 AK57 SB_DQ4 AL58 SB_DQ12 AL55 SB_DQ6 AR57 BDW_ULT_DDR3L(Interleaved) DDR CHANNEL A 3 OF 19 UCPU1C BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) DDR CHANNEL A 3 OF 19 UCPU1C BDW-ULT-DDR3L-IL_BGA1168 SM_VREF_DQ0 AR51 SM_VREF_DQ1 AP51 SM_VREF_CA AP49 SA_DQSP7 AW18 SA_DQSP5 AW26 SA_DQSP6 AV22 SA_DQSP2 AW57 SA_DQSP3 AW53 SA_DQSP4 AV30 SA_DQSP0 AJ62 SA_DQSP1 AN61 SA_DQSN6 AW22 SA_DQSN7 AV18 SA_DQSN4 AW30 SA_DQSN5 AV26 SA_DQSN3 AV53 SA_DQSN1 AN62 SA_DQSN2 AV57 SA_DQSN0 AJ61 SA_MA15 AU42 SA_MA13 AR35 SA_MA14 AV42 SA_MA10 AP35 SA_MA12 AU41 SA_MA11 AW41 SA_MA8 AY39 SA_MA9 AU40 SA_MA6 AV40 SA_MA7 AW39 SA_MA5 AR36 SA_MA4 AU39 SA_MA3 AP36 SA_MA2 AR38 SA_MA0 AU36 SA_MA1 AY37 SA_BA2 AY41 SA_BA1 AV35 SA_BA0 AU35 SA_WE AW34 SA_CAS AU34 SA_RAS AY34 SA_ODT0 AP32 SA_CS#0 AP33 SA_CS#1 AR32 SA_CKE3 AY43 SA_CKE0 AU43 SA_CKE1 AW43 SA_CKE2 AY42 SA_DQ15 AP60 SA_DQ63 AU17 SA_DQ62 AV17 SA_DQ61 AU19 SA_DQ60 AV19 SA_DQ59 AW17 SA_DQ58 AY17 SA_DQ57 AW19 SA_DQ56 AY19 SA_DQ55 AU21 SA_DQ54 AV21 SA_DQ53 AU23 SA_DQ52 AV23 SA_DQ51 AW21 SA_DQ50 AY21 SA_DQ49 AW23 SA_DQ48 AY23 SA_DQ47 AU25 SA_DQ46 AV25 SA_DQ45 AU27 SA_DQ44 AV27 SA_DQ43 AW25 SA_DQ42 AY25 SA_DQ41 AW27 SA_DQ40 AY27 SA_DQ39 AU29 SA_DQ38 AV29 SA_DQ37 AU31 SA_DQ36 AV31 SA_DQ35 AW29 SA_DQ34 AY29 SA_DQ33 AW31 SA_DQ32 AY31 SA_DQ31 AU52 SA_DQ30 AV52 SA_DQ29 AU54 SA_DQ26 AY52 SA_DQ27 AW52 SA_DQ24 AY54 SA_DQ23 AU56 SA_DQ22 AV56 SA_DQ21 AU58 SA_DQ20 AV58 SA_DQ19 AW56 SA_DQ18 AY56 SA_DQ17 AW58 SA_DQ16 AY58 SA_DQ14 AP61 SA_DQ13 AM60 SA_DQ12 AM61 SA_DQ11 AP62 SA_DQ10 AP63 SA_DQ9 AM62 SA_DQ8 AM63 SA_DQ7 AK60 SA_DQ6 AK61 SA_DQ5 AH60 SA_DQ3 AK62 SA_DQ2 AK63 SA_DQ1 AH62 SA_DQ0 AH63 SA_CLK#0 AU37 SA_CLK0 AV37 SA_CLK#1 AW36 SA_CLK1 AY36 SA_DQ28 AV54 SA_DQ25 AW54 SA_DQ4 AH61
  • 6. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. ME CMOS CMOS ODD 2.5" HDD 15mils 15mils 15mils RTC BAT conn H：Integrated VRM enable L：Integrated VRM disable INTVRMEN * Default Setting: Dual TCK S can Chains (also known as "Shared JTAG" in other docum ent) Topolog J1s, J2s, J3s R6,R7,R8,R9 R1d,R2,R3d, R4,R5,J1d J2d,J3d* J4d and Rs5* Resistors ufStuffed Resistors Stuffed Single TCK scan chain (also known as "Com m on JTAG" in other docum ent) - Run control oper. - ME/Sx debug Be st Use for In th is topolog y, PCH TDI- TDO and CPU TDI-TDO will be chained to form one JTAG scan chain controlled by TCK0 In this topology, the CPU JTAG chain will be controlled by TCK0 and TCK1 will control the PCH JTAG chain. Description -B oundary Scan/ Manufacturing est J1s,J2s,J3s** R2,R4,R5,R5s** R1d,r3d,J1d,J2d J3d**,J4d, R6,R7,R8,R9 R5 R3d R4 R8 RF solution Add RC367 EMI@ to isolate Audio Clock by EMI request 15mils Contact ok Contact ok <XDP> <CPU and XDP> J2S J1S XDP_TCK:XDP contact with CPU No 0ohm(RS5) S1 <CPU site> <PCH site> <PCH site> S2 <CPU site> <PCH site> <XDP> <XDP> <XDP> <XDP> <PCH site> <PCH site> <PCH site> <PCH site> <PCH site> <XDP> S3 <CPU> J4d J3D J3S R2 R6 R1d R9 R7 J2D Layout notes DG V0.9 SATA_COMP Width=12mil Max length=500mil L RC17 need to close to JCPU1 Place near JXDP1 S4 DB phase : For ESD request 20141117 WLAN HDA_SDOUT: ME Flash Descriptor Security Override Low : Disabled(Default) High : Enabled 2014-10-01: Follow skyfall/pixar Direct shorted Intel ME update DB phase : For ESD request 20141117 Layout notes RC367 place near CPU DB phase 2014-11-14 Add ME_Flash_EN DB phase : For XDP 20141117 <CPU,XDP,XDP Switch> SI：Change BOM con/ig SI : pop D23 PV:RG122 change to 0-ohm shortpad PV:RC353 change to 0-ohm shortpad PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# PCH_INTVRMEN PCH_JTAG_TMS XDP_TCK_JTAGX PCH_JTAG_TDO PCH_JTAG_TDI HDA_SYNC_R HDA_SYNC HDA_SYNC HDA_RST# HDA_BIT_CLK HDA_SDOUT HDA_BITCLK_AUDIO HDA_RST_AUDIO# HDA_RST# HDA_SYNC_R HDA_SDOUT HDA_BIT_CLK ODD_PLUG# EC_+1.05VS_PG XDP_TDO XDP_TMS XDP_TDI_SWITCH XDP_TRST# XDP_TDO_CPU XDP_TDI_CPU XDP_TRST#_CPU XDP_TMS PCH_JTAG_TMS PCH_JTAG_TDO XDP_TDI PCH_JTAG_TCK XDP_TCK_JTAGX XDP_TMS_CPU XDP_TDO XDP_TRST# PCH_JTAG_RST# XDP_TDI_SWITCH XDP_TDI_CPU XDP_TDI_SWITCH PCH_JTAG_TDO XDP_TDI_SWITCH XDP_TRST#_CPU PCH_JTAG_TCK XDP_TDO_CPU XDP_TRST#_CPU XDP_TDO XDP_TCK XDP_TCK PCH_JTAG_TDI XDP_TCK_JTAGX XDP_TDI SATA_LED# SATA_COMP ODD_PLUG# PCH_GPIO36 mSATA_DET# PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO XDP_TCK_JTAGX PCH_JTAG_RST# SM_INTRUDER# PCH_SRTCRST# PCH_RTCRST# PCH_INTVRMEN PCH_RTCX1 PCH_RTCX2 CFG9 CFG8 CFG15 CFG14 CFG17 CFG2 CFG3 CFG11 CFG10 CFG3 XDP_OBS0_R XDP_OBS1_R CFG13 CFG16 CFG12 XDP_TMS XDP_PREQ# XDP_PRDY# XDP_TDO XDP_TRST# XDP_TDI XDP_TCK H_CPUPWRGD_R H_CPUPWRGD_XDP XDP_RST#_R CFG1 CFG0 CFG19 CFG4 CFG5 CFG6 CFG7 CFG18 XDP_TCK1 XDP_TCK1 PCH_JTAG_TCK XDP_TDO_CPU XDP_TDO PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 HDA_SDOUT H_CPUPWRGD_R PCH_RTCX1_0_R HDA_SDOUT SATA_PTX_DRX_P1 <29> SATA_PRX_DTX_N1 <29> SATA_PTX_DRX_N1 <29> SATA_PRX_DTX_P1 <29> HDA_SDIN0 <23> HDA_RST_AUDIO# <23> HDA_SYNC_AUDIO <23> HDA_SDOUT_AUDIO <23> HDA_BITCLK_AUDIO <23> SATA_PTX_DRX_N0 <29> SATA_PRX_DTX_N0 <29> SATA_PTX_DRX_P0 <29> SATA_PRX_DTX_P0 <29> +3VS <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,7,8,9> +RTCVCC <12,28,8> PCH_RTCX1 <28> +RTCBATT <28> +VCCIO_OUT <11,4> +1.05VS_VCCST <11,4,9> +3V_PCH <10,11,12,24,36,4,7,9> +1.5VS <12,23,37,53> +1.05VS_VCCSATA3PLL <12,34> +3VL <25,28,32,46,47,48> MPHY_PWREN <9> XDP_TMS_CPU <4> XDP_TRST#_CPU <4> XDP_TCK <4> XDP_TDI_CPU <4> SATA_LED# <32,9> mSATA_DET# <7> ODD_PLUG# <29> SYS_PWROK <25,8> CFG0 <14> CFG1 <14> CFG2 <14> CFG3 <14> CFG6 <14> CFG7 <14> CFG4 <14> CFG5 <14> CFG10 <14> CFG11 <14> CFG8 <14> CFG9 <14> CFG12 <14> CFG13 <14> CFG17 <14> CFG16 <14> CFG19 <14> CFG18 <14> CFG14 <14> CFG15 <14> CPU_PWR_DEBUG <11> PCH_SMBDATA <15,16,18,21,7> PCH_SMBCLK <15,16,18,21,7> PBTN_OUT# <25,8> PLT_RST# <22,25,27,31,35,8> XDP_PREQ# <4> XDP_PRDY# <4> XDP_DBRESET# <7,8> XDP_OBS0_R <4> XDP_OBS1_R <4> CLK_CPU_ITP <7> CLK_CPU_ITP# <7> H_CPUPWRGD_R <4> XDP_TDO_CPU <4> PCIE_PRX_DTX_N6 <31> PCIE_PRX_DTX_P6 <31> PCIE_PTX_C_DRX_N6 <31> PCIE_PTX_C_DRX_P6 <31> ME_Flash_EN <25> +3VALW <12,19,22,24,25,26,28,29,32,37,48,50,53,56,7> EC_+1.05VS_PG <25> +1.05VS_PG <11,4> +RTCVCC +RTCVCC +RTCBATT +3VL +RTCBATT_R +RTCVCC +RTCVCC +3V_PCH +3V_PCH +3V_PCH +3V_PCH +3V_PCH +RTCBATT +3VS +RTCVCC +RTCBATT +VCCIO_OUT +1.05VS_VCCST +3V_PCH +1.5VS +1.05VS_VCCSATA3PLL +3VL +3VS +3VS +1.05VS_VCCST +1.05VS_VCCST +1.05VS_VCCSATA3PLL +VCCIO_OUT +VCCIO_OUT +VCCIO_OUT +3VALW +1.05VS_VCCST +1.5VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 RTC,SATA,HDA,JTAG Custom 6 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 RTC,SATA,HDA,JTAG Custom 6 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 RTC,SATA,HDA,JTAG Custom 6 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P RC39 3K_0402_1% RC39 3K_0402_1% 1 2 RC372 1K_0402_1% RC372 1K_0402_1% 1 2 RC217 10K_0402_5% RC217 10K_0402_5% 1 2 T156 PAD T156 PAD DC1 BAV70W 3P C/C_SOT-323 DC1 BAV70W 3P C/C_SOT-323 2 3 1 CC17 0.1U_0402_16V7K CC17 0.1U_0402_16V7K 1 2 CM29 22P_0402_50V8J @ CM29 22P_0402_50V8J @ 1 2 RC373 1K_0402_1% RC373 1K_0402_1% 1 2 RC196 0_0201_5% @ RC196 0_0201_5% @ 1 2 UC5 74CBTLV3126DS_SSOP16 @ UC5 74CBTLV3126DS_SSOP16 @ 2B 7 3A 11 2A 6 3OE 12 3B 10 4OE 15 VCC 16 1B 4 1A 3 2OE 5 1OE 2 NC 1 NC 9 GND 8 4A 14 4B 13 RG117 0_0402_5% UMA@ RG117 0_0402_5% UMA@ 1 2 D23 CK0402101V05_0402-2 ESD@ SCV00001K00 D23 CK0402101V05_0402-2 ESD@ SCV00001K00 1 2 T157 PAD T157 PAD RC16 51_0402_1% @ RC16 51_0402_1% @ 1 2 RC45 210_0402_5% @ RC45 210_0402_5% @ 1 2 RC303 100_0402_1% @ RC303 100_0402_1% @ 1 2 RC283 210_0402_5% @ RC283 210_0402_5% @ 1 2 RC353 0_0402_5% short@ RC353 0_0402_5% short@ 1 2 RP1 33_0804_8P4R_5% RP1 33_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC374 1K_0402_1% RC374 1K_0402_1% 1 2 RC218 100K_0402_5% RC218 100K_0402_5% 1 2 RC199 0_0201_5% @ RC199 0_0201_5% @ 1 2 RC195 0_0201_5% short@ RC195 0_0201_5% short@ 1 2 RC236 330K_0402_5% RC236 330K_0402_5% 1 2 T159 PAD T159 PAD RC198 0_0201_5% @ RC198 0_0201_5% @ 1 2 RC14 51_0402_1% @ RC14 51_0402_1% @ 1 2 JCMOS1 SHORT PADS JCMOS1 SHORT PADS 1 2 CC5 1U_0402_6.3V6K CC5 1U_0402_6.3V6K 1 2 RC15 51_0402_1% RC15 51_0402_1% 1 2 G D S Q32 2N7002_SOT23-3 G D S Q32 2N7002_SOT23-3 2 1 3 RC307 0_0201_5% @ RC307 0_0201_5% @ 1 2 RC46 210_0402_5% @ RC46 210_0402_5% @ 1 2 CC2 1U_0402_6.3V6K CC2 1U_0402_6.3V6K 1 2 RC302 100_0402_1% @ RC302 100_0402_1% @ 1 2 RC197 0_0201_5% @ RC197 0_0201_5% @ 1 2 RC240 10K_0402_5% @ RC240 10K_0402_5% @ 1 2 CC6 1U_0402_6.3V6K CC6 1U_0402_6.3V6K 1 2 RC201 0_0201_5% short@ RC201 0_0201_5% short@ 1 2 R511 10K_0402_5% R511 10K_0402_5% 1 2 RC32 20K_0402_5% RC32 20K_0402_5% 1 2 BDW_ULT_DDR3L(Interleaved) JTAG RTC AUDIO SATA 5 OF 19 UCPU1E BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) JTAG RTC AUDIO SATA 5 OF 19 UCPU1E BDW-ULT-DDR3L-IL_BGA1168 RSVD L11 RSVD K10 PCH_TMS AD62 PCH_TDO AE61 PCH_TDI AD61 PCH_TCK AE62 PCH_TRST AU62 HDA_DOCK_RST/I2S1_SFRM AV10 HDA_DOCK_EN/I2S1_TXD AW10 HDA_SDI1/I2S1_RXD AU12 HDA_SDO/I2S0_TXD AU11 HDA_SDI0/I2S0_RXD AY10 HDA_RST/I2S_MCLK AU8 HDA_SYNC/I2S0_SFRM AV11 HDA_BCLK/I2S0_SCLK AW8 RSVD AC4 RSVD AL11 RSVD AV2 I2S1_SCLK AY8 SATALED U3 JTAGX AE63 RTCX2 AY5 SATA_RCOMP C12 SATA_IREF A12 SATA3GP/GPIO37 AC1 SATA2GP/GPIO36 V6 SATA1GP/GPIO35 U1 SATA0GP/GPIO34 V1 SATA_TP3/PETP6_L0 D17 SATA_TN3/PETN6_L0 C17 SATA_RP3/PERP6_L0 E5 SATA_RN3/PERN6_L0 F5 SATA_TP2/PETP6_L1 C15 SATA_TN2/PETN6_L1 B14 SATA_RN2/PERN6_L1 J6 SATA_RP2/PERP6_L1 H6 SATA_TP1/PETP6_L2 B17 SATA_TN1/PETN6_L2 A17 SATA_RN1/PERN6_L2 J8 SATA_RP1/PERP6_L2 H8 SATA_TP0/PETP6_L3 A15 SATA_TN0/PETN6_L3 B15 SATA_RP0/PERP6_L3 H5 SATA_RN0/PERN6_L3 J5 RTCX1 AW5 RTCRST AU7 SRTCRST AV6 INTVRMEN AV7 INTRUDER AU6 RC38 51_0402_5% @ RC38 51_0402_5% @ 1 2 YC1 32.768KHZ Q13FC1350000500 UMA@ YC1 32.768KHZ Q13FC1350000500 UMA@ 1 2 U16 74AUP1G07GW_TSSOP5 @ U16 74AUP1G07GW_TSSOP5 @ GND 3 A 2 NC 1 VCC 5 Y 4 CC86 .1U_0402_16V7K @ CC86 .1U_0402_16V7K @ 1 2 RC356 1K_0402_5% RC356 1K_0402_5% 1 2 CC4 18P_0402_50V8J UMA@ CC4 18P_0402_50V8J UMA@ 1 2 RC35 1M_0402_5% RC35 1M_0402_5% 1 2 RC306 0_0201_5% @ RC306 0_0201_5% @ 1 2 RG122 0_0402_5% short@ RG122 0_0402_5% short@ 1 2 RC304 100_0402_1% @ RC304 100_0402_1% @ 1 2 CC3 18P_0402_50V8J UMA@ CC3 18P_0402_50V8J UMA@ 1 2 RC31 10M_0402_5% UMA@ RC31 10M_0402_5% UMA@ 1 2 RC193 0_0201_5% short@ RC193 0_0201_5% short@ 1 2 JXDP1 SAMTE_BSH-030-01-L-D-A CONN@ JXDP1 SAMTE_BSH-030-01-L-D-A CONN@ GND0 1 OBSFN_A0 3 OBSFN_A1 5 GND2 7 OBSDATA_A0 9 OBSDATA_A1 11 GND4 13 OBSDATA_A2 15 OBSDATA_A3 17 GND6 19 OBSFN_B0 21 OBSFN_B1 23 GND8 25 OBSDATA_B0 27 OBSDATA_B1 29 GND10 31 OBSDATA_B2 33 OBSDATA_B3 35 GND12 37 PWRGOOD/HOOK0 39 HOOK1 41 VCC_OBS_AB 43 HOOK2 45 HOOK3 47 GND14 49 SDA 51 SCL 53 TCK1 55 TCK0 57 GND16 59 GND1 2 OBSFN_C0 4 OBSFN_C1 6 GND3 8 OBSDATA_C0 10 OBSDATA_C1 12 GND5 14 OBSDATA_C2 16 OBSDATA_C3 18 GND7 20 OBSFN_D0 22 OBSFN_D1 24 GND9 26 OBSDATA_D0 28 OBSDATA_D1 30 GND11 32 OBSDATA_D2 34 OBSDATA_D3 36 GND13 38 ITPCLK/HOOK4 40 ITPCLK#/HOOK5 42 VCC_OBS_CD 44 RESET#/HOOK6 46 DBR#/HOOK7 48 GND15 50 TD0 52 TRST# 54 TDI 56 TMS 58 GND17 60 RC10 51_0402_1% RC10 51_0402_1% 1 2 RC194 0_0201_5% short@ RC194 0_0201_5% short@ 1 2 JME1 SHORT PADS JME1 SHORT PADS 1 2 RC301 100_0402_1% @ RC301 100_0402_1% @ 1 2 CC127 0.1U_0402_16V4Z CC127 0.1U_0402_16V4Z 1 2 JRTC1 LOTES_AAA-BAT-054-K01 CONN@ JRTC1 LOTES_AAA-BAT-054-K01 CONN@ + 1 - 2 RC41 210_0402_5% @ RC41 210_0402_5% @ 1 2 RC310 0_0402_5% @ RC310 0_0402_5% @ 1 2 RC367 33_0402_5% EMI@ RC367 33_0402_5% EMI@ 1 2 CC128 2.2U_0402_6.3V6M CC128 2.2U_0402_6.3V6M 1 2 CM28 22P_0402_50V8J @ CM28 22P_0402_50V8J @ 1 2 RC34 20K_0402_5% RC34 20K_0402_5% 1 2 CC16 0.1U_0402_16V7K CC16 0.1U_0402_16V7K 1 2 RC33 1K_0402_5% RC33 1K_0402_5% 1 2 RC37 0_0201_5% @ RC37 0_0201_5% @ 1 2 RC200 0_0201_5% short@ RC200 0_0201_5% short@ 1 2
  • 7. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. PCIE LAN WLAN GPU RF solution SPI ROM (8MByte ) EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P <EC> <XDP CLK > Layout notes RC368 place near CPU RC369 place near EC RC56 place near SPI ROM L Layout notes avoid stub trace too long L SI phase : Modify CLK request channel 20141214 CPU THERMAL SENSOR Address: 1001100xb NCT7718W (x is R/W bit) SI : add CPU thermal sensor 12/23 SI：Change BOM con/ig SI : add net name EC_SPI_CLK_R. PV phase : Add pull-up at PCIECLKREQ1# 20150125 SML1CLK SMBCLK CPU_XTAL24_OUT CPU_XTAL24_IN PCH_SPI_SI PCH_SPI_CS0# LPC_AD3 PCH_SPI_CLK LPC_AD0 SMBDATA PCH_SPI_SO LPC_AD2 LPC_FRAME# LPC_AD1 SML1DATA CLK_PCI_LPC CLK_PCI_TPM PCH_SPI_CLK_R PCH_SPI_SIO2 PCH_SPI_SIO3 PCH_SPI_HOLD# PCH_SPI_WP# SMBCLK SMBDATA SML1CLK SML1DATA SML0CLK SML0DATA CPU_XTAL24_OUT TESTLOW1 TESTLOW2 TESTLOW3 TESTLOW4 +1.05VS_AXCK_LCPLL PCH_CLK_BIASREF CLK_CPU_ITP# CLK_CPU_ITP CLK_PCI_TPM CLK_PCI1 CLK_PCI_LPC CLK_PCI0 USB_CR_PWREN SMBALERT# SML0CLK SML0DATA SML1CLK SMBDATA SMBCLK SML1ALERT# SML1DATA PCH_SPI_CLK_R PCH_SPI_CLK_R EC_SPI_CLK_R PCH_SPI_CS0#_R PCH_SPI_SO_R PCH_SPI_SI_R PCH_SPI_WP# PCH_SPI_SIO2 PCH_SPI_HOLD# PCH_SPI_SIO3 PCH_SPI_CS0# PCH_SPI_CS0#_R PCH_SPI_SO PCH_SPI_SO_R PCH_SPI_SI_R PCH_SPI_SI PCH_SPI_CLK PCH_SPI_CS0#_R LAN_CLKREQ# PCIECLKREQ0# SMBDATA SMBCLK CPU_XTAL24_IN_R PCH_GPIO33 WLAN_CLKREQ# PCIECLKREQ3# PCH_SPI_SI_R PCH_SPI_CLK_R PCH_SPI_HOLD# PCH_SPI_WP# PCH_SPI_CS0#_R PCH_SPI_SO_R PCIECLKREQ0# PCIECLKREQ3# GPU_CLKREQ# CPU_THERM# H_THERMDA H_THERMDC EC_SMB_CK2 EC_SMB_DA2 ALERT_L PCIECLKREQ1# PCIECLKREQ1# EC_SMB_CK2 <18,21,25,36> PCH_SMBCLK <15,16,18,21,6> PCH_SMBDATA <15,16,18,21,6> CLK_PCIE_LAN <22> CLK_PCIE_LAN# <22> CLK_PCIE_WLAN# <31> CLK_PCIE_WLAN <31> LPC_AD3 <25,27> LPC_AD0 <25,27> LPC_FRAME# <25,27> LPC_AD2 <25,27> LPC_AD1 <25,27> EC_SMB_DA2 <18,21,25,36> CLK_PCIE_GPU# <35> CLK_PCIE_GPU <35> MSATA_DET# <6> EC_KBRST# <25,9> XDP_DBRESET# <6,8> +3VS <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,8,9> +3V_PCH <10,11,12,24,36,4,6,9> +1.05VS_AXCK_LCPLL <12> CLK_PCI_TPM <27> CLK_PCI_LPC <25> CPU_XTAL24_IN <28> SMBALERT# <9> SML1ALERT# <9> USB_CR_PWREN <8> EC_SPI_CS0# <25> EC_SPI_SO <25> EC_SPI_SI <25> EC_SPI_CLK <25> CLK_CPU_ITP <6> CLK_CPU_ITP# <6> TP_SMBDATA <26> TP_SMBCLK <26> PCH_GPIO33 <9> LAN_CLKREQ# <22> WLAN_CLKREQ# <31> GPU_CLKREQ# <36> +3VS +3VS +3VS +3VS +3VS +3VS +3V_PCH +1.05VS_AXCK_LCPLL +3V_PCH +3V_PCH +3V_PCH +3V_PCH +3VALW +3V_PCH +3V_PCH +3VS +3VS +3VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 CLK,SPI,SMB,LPC C 7 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 CLK,SPI,SMB,LPC C 7 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 CLK,SPI,SMB,LPC C 7 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P CC10 18P_0402_50V8J UMA@ CC10 18P_0402_50V8J UMA@ 1 2 RC96 33K_0402_5% RC96 33K_0402_5% 1 2 RC73 1K_0402_5% RC73 1K_0402_5% 1 2 YC2 24MHZ 12PF 5YEA24000122IF40Q3 UMA@ YC2 24MHZ 12PF 5YEA24000122IF40Q3 UMA@ GND 2 3 3 1 1 GND 4 RC56 0_0402_5% RC56 0_0402_5% 1 2 RPH20 15_0804_8P4R_5% RPH20 15_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC119 2200P_0402_50V7K CC119 2200P_0402_50V7K 1 2 UC2 W25Q64FVSSIQ_SO8 UC2 W25Q64FVSSIQ_SO8 CLK 6 GND 4 DI(IO0) 5 DO(IO1) 2 /WP(IO2) 3 VCC 8 /HOLD(IO3) 7 /CS 1 RPH12 10K_0804_8P4R_5% RPH12 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC120 0.1U_0402_16V4Z CC120 0.1U_0402_16V4Z 1 2 RC125 10K_0402_5% @ RC125 10K_0402_5% @ 1 2 QC7B 2N7002DWH_SOT363-6 TP@ QC7B 2N7002DWH_SOT363-6 TP@ 3 4 5 RC368 0_0402_5% EMI@ RC368 0_0402_5% EMI@ 1 2 RC78 10K_0402_5% RC78 10K_0402_5% 1 2 UC3 NCT7718W_MSOP8 UC3 NCT7718W_MSOP8 ALERT# 6 T_CRIT# 4 GND 5 D+ 2 D- 3 SCL 8 SDA 7 VDD 1 RPH11 10K_0804_8P4R_5% RPH11 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CM33 22P_0402_50V8J @RF@ CM33 22P_0402_50V8J @RF@ 1 2 RC376 10K_0402_5% RC376 10K_0402_5% 1 2 RPH22 10K_0804_8P4R_5% RPH22 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC369 0_0402_5% EMI@ RC369 0_0402_5% EMI@ 1 2 QC2B 2N7002DWH_SOT363-6 QC2B 2N7002DWH_SOT363-6 3 4 5 RC81 10K_0402_5% TP@ RC81 10K_0402_5% TP@ 1 2 RC79 10K_0402_5% RC79 10K_0402_5% 1 2 RC48 1M_0402_5% UMA@ RC48 1M_0402_5% UMA@ 1 2 RC62 22_0402_5% EMI@ RC62 22_0402_5% EMI@ 1 2 RC80 3.3K_0402_5% @ RC80 3.3K_0402_5% @ 1 2 CC9 18P_0402_50V8J UMA@ CC9 18P_0402_50V8J UMA@ 1 2 RC82 10K_0402_5% TP@ RC82 10K_0402_5% TP@ 1 2 RC52 3K_0402_1% RC52 3K_0402_1% 1 2 QC2A 2N7002DWH_SOT363-6 QC2A 2N7002DWH_SOT363-6 6 1 2 RP2 2.2K_0804_8P4R_5% RP2 2.2K_0804_8P4R_5% 1 8 2 7 3 6 4 5 QC6B 2N7002DWH_SOT363-6 QC6B 2N7002DWH_SOT363-6 3 4 5 RG120 0_0402_5% UMA@ RG120 0_0402_5% UMA@ 1 2 QC6A 2N7002DWH_SOT363-6 QC6A 2N7002DWH_SOT363-6 6 1 2 QC7A 2N7002DWH_SOT363-6 TP@ QC7A 2N7002DWH_SOT363-6 TP@ 6 1 2 RC61 22_0402_5% EMI@ RC61 22_0402_5% EMI@ 1 2 RC85 3.3K_0402_5% RC85 3.3K_0402_5% 1 2 RC97 33K_0402_5% RC97 33K_0402_5% 1 2 BDW_ULT_DDR3L(Interleaved) LPC SMBUS C-LINK SPI 7 OF 19 UCPU1G BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) LPC SMBUS C-LINK SPI 7 OF 19 UCPU1G BDW-ULT-DDR3L-IL_BGA1168 CL_RST AF4 CL_DATA AD2 CL_CLK AF2 SML1CLK/GPIO75 AU3 SML1DATA/GPIO74 AH3 SML1ALERT/PCHHOT/GPIO73 AU4 SML0DATA AK1 SML0CLK AN1 SMBDATA AH1 SML0ALERT/GPIO60 AL2 SMBCLK AP2 SMBALERT/GPIO11 AN2 SPI_IO3 AF1 SPI_IO2 Y6 SPI_MISO AA4 SPI_MOSI AA2 SPI_CS2 AC2 SPI_CS1 Y4 SPI_CLK AA3 SPI_CS0 Y7 LFRAME AV12 LAD3 AW11 LAD2 AY12 LAD1 AW12 LAD0 AU14 C4965 0.1U_0402_16V4Z C4965 0.1U_0402_16V4Z 1 2 CM31 22P_0402_50V8J @RF@ CM31 22P_0402_50V8J @RF@ 1 2 RC84 3.3K_0402_5% RC84 3.3K_0402_5% 1 2 CM30 22P_0402_50V8J @RF@ CM30 22P_0402_50V8J @RF@ 1 2 CLOCK SIGNALS BDW_ULT_DDR3L(Interleaved) 6 OF 19 UCPU1F BDW-ULT-DDR3L-IL_BGA1168 CLOCK SIGNALS BDW_ULT_DDR3L(Interleaved) 6 OF 19 UCPU1F BDW-ULT-DDR3L-IL_BGA1168 CLKOUT_PCIE_N1 B41 CLKOUT_PCIE_P1 A41 PCIECLKRQ1/GPIO19 Y5 PCIECLKRQ0/GPIO18 U2 CLKOUT_PCIE_P0 C42 CLKOUT_ITPXDP B35 CLKOUT_LPC_0 AN15 CLKOUT_LPC_1 AP15 PCIECLKRQ4/GPIO22 U5 CLKOUT_PCIE_P4 B39 CLKOUT_PCIE_N4 A39 PCIECLKRQ3/GPIO21 N1 CLKOUT_PCIE_N0 C43 XTAL24_OUT B25 XTAL24_IN A25 PCIECLKRQ5/GPIO23 T2 CLKOUT_PCIE_P5 A37 CLKOUT_PCIE_N5 B37 CLKOUT_PCIE_P3 C37 CLKOUT_PCIE_N3 B38 PCIECLKRQ2/GPIO20 AD1 CLKOUT_PCIE_N2 C41 CLKOUT_PCIE_P2 B42 DIFFCLK_BIASREF C26 RSVD K21 RSVD M21 TESTLOW_C35 C35 TESTLOW_C34 C34 TESTLOW_AK8 AK8 TESTLOW_AL8 AL8 CLKOUT_ITPXDP_P A35 RC72 1K_0402_5% RC72 1K_0402_5% 1 2 RPH19 15_0804_8P4R_5% RPH19 15_0804_8P4R_5% 1 8 2 7 3 6 4 5
  • 8. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. <HDMI> <HDMI> <eDP HPD> L:Disable DSWODVREN - On Die DSW VR Enable * Deep S3 Deep S3 RC93-->SMT Non Deep S3 RC91-->SMT Deep S3 RC286-->SMT Non Deep S3 RC286-->@ H:Enable <CPU> DP TO CRT HPD ( RTD2168) DP TO CRT ( RTD2168) Displayport Port C Enable pin RC102 pull high +3VS DB phase : For ESD request 20141117 SI: pop D25 PV:RC300 change to 0-ohm shortpad PV:RC114,RC115,RC116,RC118,RC121,RC122 change to 0-ohm shortpad SUSACK#_R PM_PWROK_R PBTN_OUT#_R PM_BATLOW# PCH_PCIE_WAKE# PCH_RSMRST# SUSWARN#_R DSWODVREN SUS_STAT# PLT_RST#_PCH SYS_PWROK BKL_PWM_CPU_R ENBKL_CPU ENVDD_CPU_R DGPU_PWR_EN_CPU DGPU_HOLD_RST#_CPU PCH_HP_DET PCH_GPIO80 ENVDD_CPU PCH_SLP_WLAN# PCH_DPWROK_R DGPU_PWROK_CPU DSWODVREN PCH_MC_WAKE# DEVSLP1 DSWODVREN PM_SLP_S3# PM_SLP_S0#_R PM_SLP_S0#_R PCH_RSMRST# PLT_RST#_PCH PCH_DPWROK_R SYS_PWROK PM_CLKRUN# PCH_HP_DET PCH_MIC_DET USB_CR_PWREN ACIN_R ACIN_R PCH_GPIO80 PCH_PWROK AOAC_PME#_R PCH_PWROK PM_BATLOW# PCH_SLP_WLAN# SUSCLK SYS_PWROK SUSACK# PM_PWROK_R SYS_RESET# PCH_MC_WAKE# AOAC_PME# APWROK_R SUSACK# <25> ACIN <25,36,47> PBTN_OUT# <25,6> PCH_RSMRST# <25> PCH_SUSWARN# <25> PM_SLP_S5# <25> PM_SLP_SUS# <25> PM_SLP_S3# <25> PM_SLP_S4# <25> PCH_DDPB_CLK <20> PCH_DDPB_DAT <20> PCH_DDPB_HPD <20> ENVDD_CPU <19> ENBKL <25> BKL_PWM_CPU <18,19> EDP_HPD <18> PCH_DPWROK <25> PCH_PWROK <25> PLT_RST# <22,25,27,31,35,6> PCH_PCIE_WAKE# <31> PM_CLKRUN# <25> AOAC_PME# <25> SYS_PWROK <25,6> SUSWARN#_R <9> USB_CR_PWREN <7> DDI2_AUX_DP <21> DDI2_AUX_DN <21> DDI2_HPD <21> DEVSLP1 <9> SPOK <48> XDP_DBRESET# <6,7> +3V_PCH <10,11,12,24,36,4,6,7,9> +3VS <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,9> +RTCVCC <12,28,6> +3V_DSW_P <12,9> SUSCLK <31> DGPU_PWR_EN <25,37,54,9> DGPU_HOLD_RST# <35,9> DGPU_PWROK <36,9> +3VS +3VS +RTCVCC +3V_DSW_P +3VS +3V_DSW_P +3VS +3V_PCH +3VS +RTCVCC +3V_DSW_P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PM,GPIO,DDI C 8 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PM,GPIO,DDI C 8 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PM,GPIO,DDI C 8 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P RC122 0_0402_5% short@ RC122 0_0402_5% short@ 1 2 RC371 0_0201_5% short@ RC371 0_0201_5% short@ 1 2 RC93 0_0201_5% short@ RC93 0_0201_5% short@ 1 2 RC305 0_0402_5% @ RC305 0_0402_5% @ 1 2 RC106 10K_0402_5% RC106 10K_0402_5% 1 2 RC91 0_0201_5% @ RC91 0_0201_5% @ 1 2 T147 PAD @ T147 PAD @ RC104 0_0201_5% short@ RC104 0_0201_5% short@ 1 2 T143 PAD @ T143 PAD @ RC107 2.2K_0402_5% @ RC107 2.2K_0402_5% @ 1 2 RC101 10K_0402_5% RC101 10K_0402_5% 1 2 RC254 330K_0402_5% RC254 330K_0402_5% 1 2 UC9 SN74AHC1G08DCKR_SC70-5 @ UC9 SN74AHC1G08DCKR_SC70-5 @ IN1 1 IN2 2 G 3 O 4 P 5 BDW_ULT_DDR3L(Interleaved) eDP SIDEBAND PCIE DISPLAY 9 OF 19 UCPU1I BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) eDP SIDEBAND PCIE DISPLAY 9 OF 19 UCPU1I BDW-ULT-DDR3L-IL_BGA1168 DDPC_AUXN B6 DDPC_AUXP A6 DDPB_AUXP B5 EDP_BKLEN A9 GPIO53 L4 GPIO51 R5 GPIO54 L3 GPIO52 L1 GPIO55 U7 PME AD4 PIRQD/GPIO80 N2 PIRQC/GPIO79 N4 DDPB_CTRLCLK B9 DDPB_CTRLDATA C9 DDPC_CTRLCLK D9 DDPC_CTRLDATA D11 DDPB_HPD C8 EDP_HPD D6 DDPC_HPD A8 DDPB_AUXN C5 EDP_VDDEN C6 EDP_BKLCTL B8 PIRQA/GPIO77 U6 PIRQB/GPIO78 P4 D24 CK0402101V05_0402-2 @ESD@ D24 CK0402101V05_0402-2 @ESD@ 1 2 RC269 0_0201_5% @ RC269 0_0201_5% @ 1 2 RC102 2.2K_0402_5% RC102 2.2K_0402_5% 1 2 RC120 100K_0402_5% RC120 100K_0402_5% 1 2 D25 CK0402101V05_0402-2 ESD@ SCV00001K00 D25 CK0402101V05_0402-2 ESD@ SCV00001K00 1 2 RC115 0_0402_5% short@ RC115 0_0402_5% short@ 1 2 T145PAD @ T145PAD @ RC100 0_0201_5% short@ RC100 0_0201_5% short@ 1 2 RC286 0_0201_5% short@ RC286 0_0201_5% short@ 1 2 RC110 8.2K_0402_5% RC110 8.2K_0402_5% 1 2 RC116 0_0402_5% short@ RC116 0_0402_5% short@ 1 2 DC3 CH751H-40PT_SOD323-2 DC3 CH751H-40PT_SOD323-2 2 1 RC94 0_0201_5% short@ RC94 0_0201_5% short@ 1 2 DC2 CH751H-40PT_SOD323-2 DC2 CH751H-40PT_SOD323-2 2 1 RC121 0_0402_5% short@ RC121 0_0402_5% short@ 1 2 RPH15 10K_0804_8P4R_5% RPH15 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC109 10K_0402_5% RC109 10K_0402_5% 1 2 RC112 100K_0402_5% RC112 100K_0402_5% 1 2 C592 0.047U_0402_16V7K ESD@ C592 0.047U_0402_16V7K ESD@ 1 2 RC98 1K_0402_5% RC98 1K_0402_5% 1 2 T142 PAD @ T142 PAD @ RC268 0_0201_5% short@ RC268 0_0201_5% short@ 1 2 RC316 0_0201_5% short@ RC316 0_0201_5% short@ 1 2 RC118 0_0402_5% short@ RC118 0_0402_5% short@ 1 2 T154 PAD @ T154 PAD @ BDW_ULT_DDR3L(Interleaved) SYSTEM POWER MANAGEMENT 8 OF 19 UCPU1H BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) SYSTEM POWER MANAGEMENT 8 OF 19 UCPU1H BDW-ULT-DDR3L-IL_BGA1168 SLP_A AL5 SLP_SUS AP4 SLP_LAN AJ7 SLP_S3 AT4 SLP_S5/GPIO63 AP5 SLP_S4 AJ6 SUSCLK/GPIO62 AE6 CLKRUN/GPIO32 V5 SUS_STAT/GPIO61 AG4 WAKE AJ5 DSWVRMEN AW7 DPWROK AV5 SLP_WLAN/GPIO29 AM5 SLP_S0 AF3 SUSWARN/SUSPWRDNACK/GPIO30 AV4 PWRBTN AL7 BATLOW/GPIO72 AN4 ACPRESENT/GPIO31 AJ8 RSMRST AW6 PCH_PWROK AY7 SUSACK AK2 PLTRST AG7 APWROK AB5 SYS_PWROK AG2 SYS_RESET AC3 DC4 CH751H-40PT_SOD323-2 DC4 CH751H-40PT_SOD323-2 2 1 RC103 0_0201_5% short@ RC103 0_0201_5% short@ 1 2 T83 PAD T83 PAD RC255 330K_0402_5% @ RC255 330K_0402_5% @ 1 2 RC300 0_0402_5% short@ RC300 0_0402_5% short@ 1 2 RC114 0_0402_5% short@ RC114 0_0402_5% short@ 1 2 RPH27 10K_0804_8P4R_5% RPH27 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 C127 0.1U_0402_10V6K @ESD@ C127 0.1U_0402_10V6K @ESD@ 1 2 RC99 0_0201_5% short@ RC99 0_0201_5% short@ 1 2 T144 PAD @ T144 PAD @
  • 9. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Dummy GPIO27 * PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable 0 SPI * Boot BIOS Location PCH_GPIO86 Boot BIOS Strap Layout notes DG V0.9 PCH_OPIRCOMP Width=12mil,spacing=12mil Max length=500mil L <SI> PRH14.4 change from +3V_PCH to +3VS for S3 leakage <PV>PRH14 change to RPH23. PRH15 change to RPH24. PRH16 change to RPH25. PV:RC124 change to 0-ohm shortpad I2C_1_SDA EC_KBRST# PCH_OPIRCOMP EC_SCI# H_THERMTRIP#_C SERIRQ EC_LID_OUT# PCH_AUDIO_PWREN I2C_1_SCL PCH_GPIO85 NGFF_WIFI_3.3_PWREN SATA1_PWREN USB32_P0_PWREN_R# USB_CAM_PWREN PCH_GPIO9 WWAN_PWREN PCH_GPIO33 BT_ON EC_FB_CLAMP_TGL_REQ# DEVSLP1 H_THEMTRIP# LPDDR3_ID1 DGPU_PRSNT# LPDDR3_ID1 LPDDR3_ID2 DGPU_PRSNT# LPDDR3_ID2 MSATA_SSD_PWREN LAN_PWR_EN PCH_GPIO58 EC_PME# WL_OFF# UART_WAKE# PCH_LAN_WAKE# PCH_LAN_RST# PCH_CR_WAKE# PCH_CR_RST# HDA_SPKR TOUCH_PANEL_PWREN NGFF_WIFI_3.3_PWREN WWAN_PWREN MSATA_SSD_PWREN TOUCH_PANEL_PWREN PCH_CR_RST# PCH_CR_WAKE# PCH_LAN_RST# PCH_LAN_WAKE# SATA1_PWREN PCH_AUDIO_PWREN EC_LID_OUT# UART_WAKE# BT_ON USB_CAM_PWREN LAN_PWR_EN I2C_0_SDA I2C_0_SCL EC_SCI# SMBALERT# SML1ALERT# SUSWARN#_R I2C_1_SDA I2C_0_SCL I2C_0_SDA I2C_1_SCL ODD_PWR ODD_DA# TS_GPIO_CPU ODD_DA# NMI_DBG#_CPU EC_PME#_R EC_FB_CLAMP_TGL_REQ# PCH_GPIO58 USB_OC2# USB_OC0# USB_OC1# SATA_LED# SERIRQ PCH_GPIO87 PCH_GPIO9 USB32_P0_PWREN_R# NMI_DBG#_CPU EC_SCI# <25> EC_KBRST# <25,7> SERIRQ <25,27> LAN_PWR_EN <22> WL_OFF# <10,31> EC_PME# <22,25> HDA_SPKR <23> EC_LID_OUT# <25> DEVSLP1 <8> DGPU_PWR_EN <25,37,54,8> DGPU_HOLD_RST# <35,8> SMBALERT# <7> SML1ALERT# <7> SUSWARN#_R <8> MPHY_PWREN <6> PCH_GPIO33 <7> ODD_PWR <29> ODD_DA# <29> TS_GPIO_CPU <19> NMI_DBG#_CPU <25> +1.05VS_VCCST <11,4,6> +3VS <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8> +3V_PCH <10,11,12,24,36,4,6,7> +3V_DSW_P <12,8> USB_OC2# <10> USB_OC0# <10> USB_OC1# <10> SATA_LED# <32,6> DGPU_PWROK <36,8> +3VS +3V_PCH +1.05VS_VCCST +3V_PCH +3VS +3VS +3V_DSW_P +3VS +3V_PCH +3VS +1.05VS_VCCST +3VS +3V_PCH +3V_DSW_P +3VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GPIO,UART,I2C Custom 9 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GPIO,UART,I2C Custom 9 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GPIO,UART,I2C Custom 9 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P RC261 10K_0402_5% @ RC261 10K_0402_5% @ 1 2 RPH21 10K_0804_8P4R_5% RPH21 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC263 10K_0402_5% @ RC263 10K_0402_5% @ 1 2 RC242 1K_0402_5% RC242 1K_0402_5% 1 2 RPH25 10K_0804_8P4R_5% RPH25 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RPH24 10K_0804_8P4R_5% RPH24 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 T148 PAD T148 PAD RPH10 10K_0804_8P4R_5% RPH10 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC108 0_0201_5% @ RC108 0_0201_5% @ 1 2 RPH28 10K_0804_8P4R_5% @ RPH28 10K_0804_8P4R_5% @ 1 8 2 7 3 6 4 5 T150 PAD T150 PAD RPH23 10K_0804_8P4R_5% RPH23 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC135 10K_0402_5% @ RC135 10K_0402_5% @ 1 2 RC117 0_0201_5% @ RC117 0_0201_5% @ 1 2 RC129 0_0402_5% short@ RC129 0_0402_5% short@ 1 2 RPH18 1K_0804_8P4R_5% @ RPH18 1K_0804_8P4R_5% @ 1 8 2 7 3 6 4 5 RC265 10K_0402_5% DIS@ RC265 10K_0402_5% DIS@ 1 2 RC124 0_0201_5% short@ RC124 0_0201_5% short@ 1 2 T149 PAD T149 PAD RC131 49.9_0402_1% RC131 49.9_0402_1% 1 2 RPH26 10K_0804_8P4R_5% RPH26 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 T158 PAD T158 PAD BDW_ULT_DDR3L(Interleaved) SERIAL IO GPIO MISC CPU/ 10 OF 19 UCPU1J BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) SERIAL IO GPIO MISC CPU/ 10 OF 19 UCPU1J BDW-ULT-DDR3L-IL_BGA1168 RSVD AB21 RSVD AF20 SERIRQ T4 LAN_PHY_PWR_CTRL/GPIO12 AM7 GPIO58 AL4 GPIO44 AK4 BMBUSY/GPIO76 P1 GPIO8 AU2 GPIO15 AD6 GPIO17 T3 GPIO16 Y1 GPIO59 AT5 GPIO48 U4 GPIO47 AB6 GPIO49 Y3 GPIO50 P3 HSIOPC/GPIO71 Y2 GPIO13 AT3 GPIO25 AM4 GPIO14 AH4 GPIO46 AG3 GPIO10 AM2 GPIO9 AM3 DEVSLP0/GPIO33 P2 SDIO_POWER_EN/GPIO70 C4 DEVSLP1/GPIO38 L2 SPKR/GPIO81 V2 DEVSLP2/GPIO39 N5 THRMTRIP D60 RCIN/GPIO82 V4 GSPI0_CS/GPIO83 R6 GSPI0_MISO/GPIO85 N6 GSPI0_CLK/GPIO84 L6 GSPI0_MOSI/GPIO86 L8 GSPI1_CS/GPIO87 R7 GSPI1_CLK/GPIO88 L5 GSPI_MOSI/GPIO90 K2 GSPI1_MISO/GPIO89 N7 UART0_RXD/GPIO91 J1 UART0_RTS/GPIO93 J2 UART0_TXD/GPIO92 K3 UART0_CTS/GPIO94 G1 UART1_TXD/GPIO1 G2 UART1_RXD/GPIO0 K4 I2C0_SCL/GPIO5 F3 I2C1_SDA/GPIO6 G4 I2C1_SCL/GPIO7 F1 SDIO_CMD/GPIO65 F4 SDIO_CLK/GPIO64 E3 SDIO_D0/GPIO66 D3 SDIO_D3/GPIO69 E2 SDIO_D2/GPIO68 C3 SDIO_D1/GPIO67 E4 GPIO28 AD7 GPIO57 AP1 GPIO56 AG6 GPIO45 AG5 GPIO24 AD5 GPIO27 AN5 GPIO26 AN3 UART1_RST/GPIO2 J3 I2C0_SDA/GPIO4 F2 UART1_CTS/GPIO3 J4 PCH_OPI_RCOMP AW15 RC119 0_0201_5% @ RC119 0_0201_5% @ 1 2 RC264 10K_0402_5% @ RC264 10K_0402_5% @ 1 2 RK11 10K_0402_5% RK11 10K_0402_5% 1 2 RPH14 10K_0804_8P4R_5% RPH14 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC277 10K_0402_5% RC277 10K_0402_5% 1 2 RC262 10K_0402_5% UMA@ RC262 10K_0402_5% UMA@ 1 2
  • 10. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Layout notes DG V0.9 USBRBIAS Trace width=50ohm and spacing=15mil Max length=500mil L USB2.0 ( on small BD ) USB2.0/USB3.0 Camera WLAN/BT USB2.0 USB2.0/USB3.0 LAN Touch screen Card reader <Page12> Layout notes DG V0.9 PCIE_RCOMP Width=12mil,spacing=12mil Max length=500mil L DGPU WL_OFF# PCIE_PTX_DRX_N3 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_P3 PCH_PCIE_RCOMP USBRBIAS USB1_PWR_EN USB_OC2# USB1_PWR_EN PCIE_PTX_DRX_N5_L0 PCIE_PTX_DRX_N5_L1 PCIE_PTX_DRX_P5_L1 PCIE_PTX_DRX_P5_L0 PCIE_PTX_DRX_N5_L3 PCIE_PTX_DRX_N5_L2 PCIE_PTX_DRX_P5_L3 PCIE_PTX_DRX_P5_L2 USB_OC0# USB_OC1# USB3_RX0_P <30> USB3_RX0_N <30> USB3_TX0_P <30> USB3_TX0_N <30> USB_OC2# <9> PCIE_PRX_DTX_N3 <22> PCIE_PTX_C_DRX_P3 <22> PCIE_PTX_C_DRX_N3 <22> PCIE_PRX_DTX_P3 <22> USB20_P2 <32> USB20_N2 <32> WL_OFF# <31,9> USB20_N6 <32> USB20_P6 <32> PCIE_CTX_GRX_P0 <35> PCIE_CTX_GRX_N0 <35> PCIE_CRX_GTX_P0 <35> PCIE_CRX_GTX_N0 <35> PCIE_CTX_GRX_P2 <35> PCIE_CTX_GRX_N2 <35> PCIE_CTX_GRX_P3 <35> PCIE_CTX_GRX_N3 <35> PCIE_CRX_GTX_P2 <35> PCIE_CRX_GTX_N2 <35> PCIE_CRX_GTX_P3 <35> PCIE_CRX_GTX_N3 <35> PCIE_CRX_GTX_P1 <35> PCIE_CTX_GRX_N1 <35> PCIE_CTX_GRX_P1 <35> PCIE_CRX_GTX_N1 <35> USB20_N5 <19> USB20_P5 <19> USB20_P0 <30> USB20_N0 <30> USB20_P1 <30> USB20_N1 <30> USB20_P3 <31> USB20_N3 <31> USB20_P4 <19> USB20_N4 <19> +3V_PCH <11,12,24,36,4,6,7,9> USB_OC0# <9> USB_OC1# <9> +3V_PCH +1.05VS_VCCUSB3PLL +3V_PCH Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PCIE,USB C 10 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PCIE,USB C 10 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 PCIE,USB C 10 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P C4 .1U_0402_16V7K DIS@ C4 .1U_0402_16V7K DIS@ 1 2 C10 .1U_0402_16V7K DIS@ C10 .1U_0402_16V7K DIS@ 1 2 C5 .1U_0402_16V7K DIS@ C5 .1U_0402_16V7K DIS@ 1 2 C6 .1U_0402_16V7K DIS@ C6 .1U_0402_16V7K DIS@ 1 2 CC15 0.1U_0402_16V7K CC15 0.1U_0402_16V7K 1 2 C3 .1U_0402_16V7K DIS@ C3 .1U_0402_16V7K DIS@ 1 2 C7 .1U_0402_16V7K DIS@ C7 .1U_0402_16V7K DIS@ 1 2 RPH29 10K_0804_8P4R_5% RPH29 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 C8 .1U_0402_16V7K DIS@ C8 .1U_0402_16V7K DIS@ 1 2 RC111 22.6_0402_1% RC111 22.6_0402_1% 1 2 BDW_ULT_DDR3L(Interleaved) PCIE USB 11 OF 19 UCPU1K BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) PCIE USB 11 OF 19 UCPU1K BDW-ULT-DDR3L-IL_BGA1168 RSVD AM10 RSVD AN10 USB2P1 AT7 USB2P0 AM8 PERN3 G11 PETN5_L0 C23 USBRBIAS AJ10 USBRBIAS AJ11 PETN5_L1 B23 PETP5_L1 A23 USB2N7 AR13 USB2P7 AP13 USB2N6 AP11 USB2P5 AN13 USB2N5 AM13 USB2P6 AN11 USB2P4 AL15 USB2N4 AM15 USB2P3 AT10 USB2N3 AR10 USB2P2 AP8 USB2N2 AR8 USB2N1 AR7 USB2N0 AN8 PETP4 A29 PERP4 G13 PERN5_L3 E6 PERP5_L3 F6 PETN5_L2 B21 PERP5_L2 G10 PERN5_L2 H10 OC0/GPIO40 AL3 OC1/GPIO41 AT1 OC2/GPIO42 AH2 OC3/GPIO43 AV3 PETN3 C29 PERP3 F11 PERN5_L1 F8 PETN5_L3 B22 PETP5_L3 A21 PERP5_L1 E8 PETN4 B29 PETP5_L0 C22 PERP5_L0 E10 PERN5_L0 F10 PERN4 F13 PETP3 B30 PCIE_IREF B27 PCIE_RCOMP A27 RSVD E13 PETP5_L2 C21 PERP1/USB3RP3 F17 PERN1/USB3RN3 G17 RSVD E15 PETP1/USB3TP3 C31 PETN1/USB3TN3 C30 PERN2/USB3RN4 F15 PETP2/USB3TP4 A31 PETN2/USB3TN4 B31 PERP2/USB3RP4 G15 USB3RN1 G20 USB3RP1 H20 USB3TN1 C33 USB3TP1 B34 USB3RN2 E18 USB3RP2 F18 USB3TN2 B33 USB3TP2 A33 C9 .1U_0402_16V7K DIS@ C9 .1U_0402_16V7K DIS@ 1 2 RC113 3K_0402_1% RC113 3K_0402_1% 1 2 CC14 0.1U_0402_16V7K CC14 0.1U_0402_16V7K 1 2
  • 11. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Compal Electronics, Inc. <EDP_COMP power rail> VCC_SENSE SVID ALERT Layout notes DG V0.5 H_CPU_SVIDALRT# RC154 close to CPU<300mil Max length=1000~2000mil L SVID DATA Layout notes DG V0.5 VIDSOUT RC156 close to CPU<500mil Max length=1000~2000mil L <PWR VR12.6> 2500mA 600mA <PWR VR12.6> <PWR VR12.6> +VCC_CORE@10000mA <VR IV and CPU> <CPU> PV:RC223,RG124 change to 0-ohm shortpad H_CPU_SVIDALRT# VR_SVID_DAT VR_SVID_CLK CPU_PWR_DEBUG H_CPU_SVIDALRT# VR_SVID_DAT VR12.6PG_MCP VCCSENSE VR12.6PG_MCP VR_SVID_CLK <51> VR_SVID_ALRT# <51> VR_SVID_DAT <51> VR_ON <51> +1.05VS_PG <4,6> VCCSENSE <51> CPU_PWR_DEBUG <6> +VCC_CORE <34,51,52> +1.35V_VDDQ <15,16,17,34,4,49> +1.05VS_VCCST <4,6,9> +VCCIO_OUT <4,6> +VCCIOA_OUT <4> +1.05VS <12,24,25,28,34,37,50,51> VGATE <51> +VCC_CORE +1.35V_VDDQ +VCC_CORE +VCCIOA_OUT +VCC_CORE +1.35V_VDDQ +1.35V_VDDQ +1.05VS +1.05VS_VCCST +1.05VS_VCCST +1.05VS_VCCST +1.05VS_VCCST +3V_PCH +VCCIO_OUT +1.05VS +VCCIO_OUT +1.05VS_VCCST +VCC_CORE +1.35V_VDDQ +1.05VS_VCCST +VCCIO_OUT +VCCIOA_OUT +1.05VS +1.05VS_VCCST Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power Custom 11 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power Custom 11 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power Custom 11 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P CC27 10U_0603_6.3V6M @ CC27 10U_0603_6.3V6M @ 1 2 CC26 10U_0603_6.3V6M CC26 10U_0603_6.3V6M 1 2 CC72 1U_0402_6.3V6K @ CC72 1U_0402_6.3V6K @ 1 2 + CC24 330U_2.5V_M @ + CC24 330U_2.5V_M @ 1 2 RC154 75_0402_5% RC154 75_0402_5% 1 2 CC21 2.2U_0402_6.3V6M @ CC21 2.2U_0402_6.3V6M @ 1 2 CC22 2.2U_0402_6.3V6M CC22 2.2U_0402_6.3V6M 1 2 CC30 10U_0603_6.3V6M CC30 10U_0603_6.3V6M 1 2 + CC25 330U_2.5V_M @ + CC25 330U_2.5V_M @ 1 2 CC23 2.2U_0402_6.3V6M CC23 2.2U_0402_6.3V6M 1 2 RC167 10K_0402_5% @ RC167 10K_0402_5% @ 1 2 RC294 0_0402_5% @ RC294 0_0402_5% @ 1 2 CC28 10U_0603_6.3V6M CC28 10U_0603_6.3V6M 1 2 RC166 150_0402_5% RC166 150_0402_5% 1 2 CC31 10U_0603_6.3V6M @ CC31 10U_0603_6.3V6M @ 1 2 CC20 2.2U_0402_6.3V6M CC20 2.2U_0402_6.3V6M 1 2 RC155 43_0402_1% RC155 43_0402_1% 1 2 RC156 110_0402_1% RC156 110_0402_1% 1 2 RC288 10K_0402_5% @ RC288 10K_0402_5% @ 1 2 CC71 22U_0805_6.3V6M CC71 22U_0805_6.3V6M 1 2 BDW_ULT_DDR3L(Interleaved) HSW ULT POWER 12 OF 19 UCPU1L BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) HSW ULT POWER 12 OF 19 UCPU1L BDW-ULT-DDR3L-IL_BGA1168 VCCIO_OUT A59 VCCIOA_OUT E20 RSVD AD23 RSVD AB23 RSVD AC58 VCC F59 VDDQ AY44 VDDQ AY40 VDDQ AY35 RSVD AA59 RSVD U59 RSVD V59 RSVD AG58 RSVD AC59 RSVD AE60 RSVD AD59 VCCST AC22 VDDQ AY50 RSVD N58 VCC_SENSE E63 RSVD AA23 RSVD AE59 VCCST_PWRGD B59 VR_READY C59 VR_EN F60 VDDQ AR48 VDDQ AP43 VDDQ AN33 VDDQ AJ37 VDDQ AJ33 VDDQ AJ31 VDDQ AH26 RSVD J58 RSVD L59 VCC C24 VCC C28 VCC C32 VCC AG57 VCC W57 VCC U57 VCC M23 VCC M57 VCC P57 VCC L22 VCC K57 VCC H23 VCC J23 VCC G55 VCC G57 VCC G49 VCC G51 VCC G53 VCC G45 VCC G47 VCC G43 VCC G39 VCC G41 VCC G37 VCC G35 VCC G33 VCC G29 VCC G31 VCC G27 VCC G25 VCC G23 VCC F52 VCC F56 VCC F48 VCC F44 VCC F40 VCC F28 VCC F32 VCC F36 VCC F24 VCC E57 VCC E51 VCC E53 VCC E55 VCC E47 VCC E49 VCC E41 VCC E43 VCC E45 VCC E37 VCC E39 VCC E31 VCC E33 VCC E35 VCC E27 VCC E29 VCC C56 VCC E23 VCC E25 VCC C48 VCC C52 VCC C36 VCC C40 VCC C44 VCC K23 VCC AD57 VCC AB57 VCCST AE23 VCCST AE22 VIDSOUT L63 VIDSCLK N63 VIDALERT L62 VSS P62 RSVD_TP P60 RSVD_TP P61 RSVD_TP N59 RSVD_TP N61 RSVD T59 RSVD AD60 VSS D63 PWR_DEBUG H59 RG124 0_0402_5% short@ RG124 0_0402_5% short@ 1 2 RC223 0_0805_5% short@ RC223 0_0805_5% short@ 1 2 UC8 74AUP1G07GW_TSSOP5 @ UC8 74AUP1G07GW_TSSOP5 @ GND 3 A 2 NC 1 VCC 5 Y 4 CC29 10U_0603_6.3V6M @ CC29 10U_0603_6.3V6M @ 1 2
  • 12. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A LA-8661P Total 1.05VS=1838+2274=4111mA Total 1.5VS=3mA Total 1.8VS=7mA Total 3VS=0mA Total 3VALW=200+62=262mA Total 1.05V=540+109=649mA Total 3V_PCH=99mA Use +1.05V Non Deep S3 RC182-->SMT Deep S3 RC285-->SMT Deep S3 and Non Deep S3 SPI ROM power rail 1.838A 41mA 42mA 57mA 1.6A 0.658A 65mA 18mA 31mA 62mA 124mA PV:RC168,RC172,RC280,RC281,RC285,RC196,RC175,RC178 change to 0-ohm shortpad +3V_1V8_SDIO +3V_DSW_P +RTCVCC +1.05VS_VCCHSIO +1.05V_DCPSUS +1.05VS_APPLOPI +1.05V_AOSCSUS +1.05VS_AXCK_LCPLL +VCCSUSHDA +1.05VS_VCCSATA3PLL +1.05VS_VCCASW +1.05VS_APPLOPI +1.05V_DCPSUS +1.05VS_VCCUSB3PLL +1.05VS_AXCKDCB +3V_DSW_PRTCSUS +1.05VS_VCCUSB3PLL +1.05VS_VCCSATA3PLL +1.05VS_AXCKDCB +1.05VS_AXCK_LCPLL +1.05V_AOSCSUS +3V_DSW_P +V1.05S_SSCF100 +V1.05S_SSCFF +V1.05S_SSCF100 +V1.05S_SSCFF +3V_PCH <10,11,24,36,4,6,7,9> +RTCVCC <28,6,8> +1.05VS <11,24,25,28,34,37,50,51> +1.5VS <23,37,53,6> +3VS <15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +1.05V <24> +3VALW <19,22,24,25,26,28,29,32,37,48,50,53,56,7> +3V_DSW_P <8,9> +1.05VS_MODPHY <24,34> +1.05VS_VCCSATA3PLL <34,6> +1.05VS_APPLOPI <34> +1.05VS +RTCVCC +3VS +3VS +1.05VS +3V_PCH +3V_PCH +1.05VS +3VS +1.5VS +1.05VS +1.05VS +1.05VS +1.05VS +1.05VS +1.05VS +3V_PCH +1.5VS +1.05VS_MODPHY +1.05VS_MODPHY +1.05VS_MODPHY +1.05V +1.05V +1.05VS +1.05VS_AXCK_LCPLL +1.05VS_VCCUSB3PLL +1.05VS_VCCSATA3PLL +3VALW +3V_DSW_P +3V_PCH +3V_PCH +3V_PCH +RTCVCC +1.05VS +1.5VS +3VS +1.05V +1.05VS_MODPHY +3VALW +3V_DSW_P +1.05VS_VCCSATA3PLL +1.05VS_APPLOPI Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power C 12 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power C 12 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 Power C 12 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P RC179 2.2UH_LQM2MPN2R2NG0L_30% RC179 2.2UH_LQM2MPN2R2NG0L_30% 1 2 RC280 0_0603_5% short@ RC280 0_0603_5% short@ 1 2 CC40 0.1U_0402_16V7K CC40 0.1U_0402_16V7K 1 2 CC46 1U_0402_6.3V6K CC46 1U_0402_6.3V6K 1 2 CC76 0.1U_0402_16V7K CC76 0.1U_0402_16V7K 1 2 RC174 5.11_0402_1% RC174 5.11_0402_1% 1 2 CC69 1U_0402_6.3V6K CC69 1U_0402_6.3V6K 1 2 CC45 10U_0603_6.3V6M CC45 10U_0603_6.3V6M 1 2 CC43 1U_0402_6.3V6K CC43 1U_0402_6.3V6K 1 2 RC175 0_0805_5% short@ RC175 0_0805_5% short@ 1 2 CC68 47U_0805_6.3V6M CC68 47U_0805_6.3V6M 1 2 RC281 0_0603_5% short@ RC281 0_0603_5% short@ 1 2 RC168 0_0805_5% short@ RC168 0_0805_5% short@ 1 2 CC49 1U_0402_6.3V6K CC49 1U_0402_6.3V6K 1 2 CC42 47U_0805_6.3V6M CC42 47U_0805_6.3V6M 1 2 RC181 2.2UH_LQM2MPN2R2NG0L_30% RC181 2.2UH_LQM2MPN2R2NG0L_30% 1 2 CC61 1U_0402_6.3V6K CC61 1U_0402_6.3V6K 1 2 CC53 1U_0402_6.3V6K CC53 1U_0402_6.3V6K 1 2 CC65 1U_0402_6.3V6K CC65 1U_0402_6.3V6K 1 2 CC39 1U_0402_6.3V6K CC39 1U_0402_6.3V6K 1 2 CC62 1U_0402_6.3V6K CC62 1U_0402_6.3V6K 1 2 CC50 10U_0603_6.3V6M CC50 10U_0603_6.3V6M 1 2 CC41 1U_0402_6.3V6K CC41 1U_0402_6.3V6K 1 2 CC66 1U_0402_6.3V6K @ CC66 1U_0402_6.3V6K @ 1 2 RC182 0_0402_5% @ RC182 0_0402_5% @ 1 2 CC64 1U_0402_6.3V6K CC64 1U_0402_6.3V6K 1 2 CC34 1U_0402_6.3V6K CC34 1U_0402_6.3V6K 1 2 CC51 1U_0402_6.3V6K CC51 1U_0402_6.3V6K 1 2 CC35 47U_0805_6.3V6M CC35 47U_0805_6.3V6M 1 2 CC37 0.1U_0402_16V7K @ CC37 0.1U_0402_16V7K @ 1 2 CC52 1U_0402_6.3V6K CC52 1U_0402_6.3V6K 1 2 CC60 1U_0402_6.3V6K CC60 1U_0402_6.3V6K 1 2 RC285 0_0402_5% short@ RC285 0_0402_5% short@ 1 2 USB2 THERMAL SENSOR HSIO BDW_ULT_DDR3L(Interleaved) USB3 OPI RTC GPIO/LPC VRM HDA SERIAL IO SUS OSCILLATOR SPI LPT LP POWER CORE 13 OF 19 UCPU1M BDW-ULT-DDR3L-IL_BGA1168 USB2 THERMAL SENSOR HSIO BDW_ULT_DDR3L(Interleaved) USB3 OPI RTC GPIO/LPC VRM HDA SERIAL IO SUS OSCILLATOR SPI LPT LP POWER CORE 13 OF 19 UCPU1M BDW-ULT-DDR3L-IL_BGA1168 VCCHDA AH14 VCCTS1_5 J15 DCPSUS1 AD8 DCPSUS1 AD10 DCPSUSBYP AG20 DCPSUSBYP AG19 DCPSUS4 AB8 VCCASW AE9 VCCASW AF9 VCCASW AG8 VCCSUS3_3 AH11 VCCRTC AG10 DCPRTC AE7 VCCSPI Y8 VCCASW AG14 VCCASW AG13 VCC3_3 K16 VCC3_3 K14 VCCSDIO T9 VCCSDIO U8 DCPSUS3 J13 VCCAPLL W21 VCCHSIO K9 VCCHSIO L10 VCCHSIO M9 VCCAPLL AA21 RSVD Y20 VCCSATA3PLL B11 VCCUSB3PLL B18 VCC1_05 N8 VCC1_05 P9 VCC1_05 J11 VCC1_05 H11 VCC1_05 H15 VCC1_05 AE8 VCC1_05 AF22 VCCSUS3_3 AE21 VCCSUS3_3 AE20 RSVD V21 RSVD M20 RSVD K18 VCCCLK T21 VCCCLK R21 VCCCLK J17 VCCACLKPLL A20 VCC3_3 W9 VCC3_3 V8 VCCDSW3_3 AH10 VCCSUS3_3 AC9 RSVD AC20 VCCSUS3_3 AA9 DCPSUS2 AH13 VCC1_05 AG16 VCC1_05 AG17 VCCCLK J18 VCCCLK K19 CC67 100U_1206_6.3V6K @ CC67 100U_1206_6.3V6K @ 1 2 CC54 22U_0805_6.3V6M CC54 22U_0805_6.3V6M 1 2 CC32 1U_0402_6.3V6K CC32 1U_0402_6.3V6K 1 2 CC55 22U_0805_6.3V6M CC55 22U_0805_6.3V6M 1 2 CC48 1U_0402_6.3V6K CC48 1U_0402_6.3V6K 1 2 CC58 1U_0402_6.3V6K CC58 1U_0402_6.3V6K 1 2 CC59 22U_0805_6.3V6M CC59 22U_0805_6.3V6M 1 2 CC57 22U_0805_6.3V6M CC57 22U_0805_6.3V6M 1 2 CC36 1U_0402_6.3V6K CC36 1U_0402_6.3V6K 1 2 RC178 0_0603_5% short@ RC178 0_0603_5% short@ 1 2 CC44 0.1U_0402_16V7K @ CC44 0.1U_0402_16V7K @ 1 2 RC169 0_0402_5% short@ RC169 0_0402_5% short@ 1 2 RC180 2.2UH_LQM2MPN2R2NG0L_30% @ RC180 2.2UH_LQM2MPN2R2NG0L_30% @ 1 2 RC176 2.2UH_LQM2MPN2R2NG0L_30% RC176 2.2UH_LQM2MPN2R2NG0L_30% 1 2 RC173 0_0402_5% @ RC173 0_0402_5% @ 1 2 CC63 47U_0805_6.3V6M CC63 47U_0805_6.3V6M 1 2 RC172 0_0402_5% short@ RC172 0_0402_5% short@ 1 2 CC70 1U_0402_6.3V6K CC70 1U_0402_6.3V6K 1 2 RC171 2.2UH_LQM2MPN2R2NG0L_30% RC171 2.2UH_LQM2MPN2R2NG0L_30% 1 2 RC170 2.2UH_LQM2MPN2R2NG0L_30% RC170 2.2UH_LQM2MPN2R2NG0L_30% 1 2 CC33 1U_0402_6.3V6K CC33 1U_0402_6.3V6K 1 2
  • 13. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A <PWR VR12.6> VSSSENSE <51> Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GND/VSSSEN 13 61 Saturday, January 31, 2015 2010/05/27 2011/05/11 Compal Electronics, Inc. LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GND/VSSSEN 13 61 Saturday, January 31, 2015 2010/05/27 2011/05/11 Compal Electronics, Inc. LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 GND/VSSSEN 13 61 Saturday, January 31, 2015 2010/05/27 2011/05/11 Compal Electronics, Inc. LA-C701P BDW_ULT_DDR3L(Interleaved) 15 OF 19 UCPU1O BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 15 OF 19 UCPU1O BDW-ULT-DDR3L-IL_BGA1168 VSS AV16 VSS AV24 VSS AV33 VSS AV28 VSS AV20 VSS AR11 VSS AU33 VSS AU55 VSS D26 VSS D27 VSS D25 VSS D23 VSS AV55 VSS AP38 VSS AP29 VSS AP31 VSS AP39 VSS AP52 VSS AP54 VSS AP57 VSS AR15 VSS AR17 VSS AR23 VSS AR31 VSS AR33 VSS AR39 VSS AR43 VSS AR49 VSS AR5 VSS AR52 VSS AT13 VSS AT35 VSS AT37 VSS AT40 VSS AT42 VSS AT43 VSS AT46 VSS AT49 VSS AT61 VSS AT62 VSS AT63 VSS AU1 VSS AU18 VSS AU22 VSS AU30 VSS AU51 VSS AU53 VSS AU57 VSS AU59 VSS AV14 VSS AV36 VSS AV39 VSS AV41 VSS AV43 VSS AV46 VSS AV49 VSS AV51 VSS AW24 VSS AW33 VSS AW35 VSS AW37 VSS AW4 VSS AW42 VSS AW44 VSS AW47 VSS AW50 VSS AW51 VSS AW59 VSS AY11 VSS AY16 VSS AY18 VSS AY22 VSS AY24 VSS AY26 VSS AY30 VSS AY33 VSS AY4 VSS AY51 VSS AY53 VSS AY57 VSS AY59 VSS AY6 VSS B20 VSS B24 VSS B26 VSS B28 VSS B32 VSS B36 VSS B4 VSS B40 VSS B44 VSS B48 VSS B52 VSS B56 VSS B60 VSS C18 VSS C20 VSS C25 VSS C27 VSS C38 VSS C39 VSS C57 VSS D12 VSS D14 VSS D18 VSS D2 VSS D21 VSS D29 VSS D30 VSS D31 VSS AV34 VSS AV59 VSS AV8 VSS AW16 VSS AW40 VSS AW60 VSS C11 VSS C14 VSS AU28 VSS AU26 VSS AU24 VSS AU20 VSS AU16 VSS AP48 VSS AP26 VSS AP22 VSS AP23 VSS AP3 BDW_ULT_DDR3L(Interleaved) 14 OF 19 UCPU1N BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 14 OF 19 UCPU1N BDW-ULT-DDR3L-IL_BGA1168 VSS AH44 VSS AH49 VSS AH51 VSS AH38 VSS AP10 VSS AN49 VSS AN40 VSS AN23 VSS AM1 VSS AL51 VSS A28 VSS A11 VSS A14 VSS A18 VSS A24 VSS A32 VSS A36 VSS A40 VSS A44 VSS A48 VSS A52 VSS A56 VSS AA1 VSS AA58 VSS AB10 VSS AB20 VSS AB22 VSS AB7 VSS AC61 VSS AD21 VSS AD3 VSS AD63 VSS AE10 VSS AE5 VSS AE58 VSS AF11 VSS AF12 VSS AF14 VSS AF17 VSS AG1 VSS AG11 VSS AG23 VSS AG60 VSS AG62 VSS AG63 VSS AH19 VSS AH24 VSS AH28 VSS AH30 VSS AH32 VSS AH40 VSS AH42 VSS AH53 VSS AH55 VSS AH57 VSS AJ13 VSS AJ14 VSS AJ23 VSS AJ25 VSS AJ27 VSS AJ29 VSS AJ43 VSS AJ45 VSS AJ50 VSS AJ52 VSS AJ56 VSS AJ58 VSS AJ60 VSS AJ63 VSS AK23 VSS AK3 VSS AK52 VSS AL10 VSS AL13 VSS AL17 VSS AL20 VSS AL22 VSS AL23 VSS AL26 VSS AL29 VSS AL31 VSS AL33 VSS AL36 VSS AL39 VSS AL40 VSS AL45 VSS AL46 VSS AL52 VSS AL54 VSS AL57 VSS AL60 VSS AL61 VSS AM17 VSS AM23 VSS AM31 VSS AM52 VSS AN17 VSS AN31 VSS AN32 VSS AN35 VSS AN36 VSS AN39 VSS AN42 VSS AN43 VSS AN45 VSS AN46 VSS AN48 VSS AN51 VSS AN52 VSS AN60 VSS AN63 VSS AN7 VSS AP17 VSS AP20 VSS AF18 VSS AF15 VSS AJ54 VSS AJ47 VSS AJ35 VSS AJ41 VSS AJ39 VSS AH36 VSS AH34 VSS AH22 VSS AH20 VSS AH17 VSS AG61 VSS AG21 BDW_ULT_DDR3L(Interleaved) 16 OF 19 UCPU1P BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 16 OF 19 UCPU1P BDW-ULT-DDR3L-IL_BGA1168 VSS D59 VSS Y63 VSS Y59 VSS Y10 VSS V10 VSS U9 VSS U22 VSS U61 VSS U20 VSS T58 VSS T1 VSS R22 VSS R8 VSS R10 VSS P63 VSS P59 VSS N3 VSS N10 VSS M22 VSS L61 VSS L58 VSS L20 VSS L18 VSS L17 VSS L15 VSS L13 VSS K12 VSS K1 VSS J63 VSS J59 VSS J22 VSS H17 VSS F38 VSS F50 VSS AH16 VSS F42 VSS F34 VSS E17 VSS G22 VSS G6 VSS D39 VSS D38 VSS D37 VSS D35 VSS D34 VSS D43 VSS D45 VSS D46 VSS D47 VSS D5 VSS D50 VSS D51 VSS D53 VSS D54 VSS D55 VSS D57 VSS D62 VSS D8 VSS E11 VSS F46 VSS F54 VSS F58 VSS F61 VSS G18 VSS G3 VSS G5 VSS G8 VSS H13 VSS D42 VSS D41 VSS H57 VSS L7 VSS D33 VSS J10 VSS V58 VSS AH46 VSS V23 VSS_SENSE E62 VSS W22 VSS W20 VSS V7 VSS V3 VSS D49 VSS F30 VSS F26 VSS F20
  • 14. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A CFG4 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port Display Port Presence Strap * Layout notes DG V0.9 PROC_OPI_COMP Width=12mil,spacing=12mil Max length=500mil L CFG_RCOMP PROC_OPI_COMP TD_IREF CFG4 TP_DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY61_AW61 DC_TEST_AY61_AW62 DC_TEST_AY61_AW62 DC_TEST_A61_B61 DC_TEST_AY2_AW2 TP_DC_TEST_A3_B3 DC_TEST_AY61_AW61 DC_TEST_B62_B63 DC_TEST_AY3_AW3 DC_TEST_C1_C2 MCP_RSVD_29 CFG0 CFG10 CFG11 CFG14 CFG15 CFG1 CFG2 CFG0 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG12 CFG13 CFG17 CFG19 CFG16 CFG18 CFG0 <6> CFG1 <6> CFG2 <6> CFG3 <6> CFG4 <6> CFG5 <6> CFG6 <6> CFG7 <6> CFG8 <6> CFG9 <6> CFG10 <6> CFG11 <6> CFG12 <6> CFG13 <6> CFG14 <6> CFG15 <6> CFG16 <6> CFG18 <6> CFG17 <6> CFG19 <6> Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 14 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. RSVD/CFG Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 14 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. RSVD/CFG Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-C701P 0.1 14 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 Compal Electronics, Inc. RSVD/CFG RC186 49.9_0402_1% RC186 49.9_0402_1% 1 2 RESERVED BDW_ULT_DDR3L(Interleaved) 19 OF 19 UCPU1S BDW-ULT-DDR3L-IL_BGA1168 RESERVED BDW_ULT_DDR3L(Interleaved) 19 OF 19 UCPU1S BDW-ULT-DDR3L-IL_BGA1168 CFG4 AA60 CFG5 Y62 CFG17 AA61 CFG18 U63 CFG7 Y60 CFG11 U60 RSVD_TP AU63 RSVD_TP C63 RSVD_TP C62 RSVD_TP L60 RSVD_TP B51 RSVD_TP A51 CFG10 V60 CFG9 V61 CFG8 V62 RSVD N60 RSVD Y22 RSVD W23 RSVD D58 RSVD AV62 RSVD_TP AV63 VSS N21 VSS P22 CFG19 U62 RSVD R20 RSVD P20 RSVD J20 CFG3 AA63 CFG2 AC63 CFG1 AC62 CFG16 AA62 CFG15 T60 CFG14 T61 CFG_RCOMP V63 RSVD A5 RSVD E1 RSVD D1 TD_IREF B12 RSVD H18 PROC_OPI_RCOMP AY15 CFG12 T63 CFG13 T62 CFG0 AC60 CFG6 Y61 RSVD B43 BDW_ULT_DDR3L(Interleaved) 18 OF 19 UCPU1R BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 18 OF 19 UCPU1R BDW-ULT-DDR3L-IL_BGA1168 RSVD AY14 RSVD AW14 RSVD AT2 RSVD AU44 RSVD AV44 RSVD D15 RSVD F22 RSVD H22 RSVD J21 RSVD T23 RSVD N23 RSVD R23 RSVD AU15 RSVD AU10 RSVD AM11 RSVD AL1 RSVD U10 RSVD AP7 RC191 8.2K_0402_5% RC191 8.2K_0402_5% 1 2 RC188 49.9_0402_1% RC188 49.9_0402_1% 1 2 RC187 1K_0402_1% @ RC187 1K_0402_1% @ 1 2 BDW_ULT_DDR3L(Interleaved) 17 OF 19 UCPU1Q BDW-ULT-DDR3L-IL_BGA1168 BDW_ULT_DDR3L(Interleaved) 17 OF 19 UCPU1Q BDW-ULT-DDR3L-IL_BGA1168 DAISY_CHAIN_NCTF_AY2 AY2 DAISY_CHAIN_NCTF_AY60 AY60 DAISY_CHAIN_NCTF_AY61 AY61 DAISY_CHAIN_NCTF_B2 B2 DAISY_CHAIN_NCTF_A3 A3 DAISY_CHAIN_NCTF_A4 A4 DAISY_CHAIN_NCTF_A61 A61 DAISY_CHAIN_NCTF_A60 A60 DAISY_CHAIN_NCTF_AW1 AW1 DAISY_CHAIN_NCTF_AV1 AV1 DAISY_CHAIN_NCTF_A62 A62 DAISY_CHAIN_NCTF_AW2 AW2 DAISY_CHAIN_NCTF_AW3 AW3 DAISY_CHAIN_NCTF_AW61 AW61 DAISY_CHAIN_NCTF_AW63 AW63 DAISY_CHAIN_NCTF_AW62 AW62 DAISY_CHAIN_NCTF_C1 C1 DAISY_CHAIN_NCTF_B62 B62 DAISY_CHAIN_NCTF_B3 B3 DAISY_CHAIN_NCTF_AY3 AY3 DAISY_CHAIN_NCTF_AY62 AY62 DAISY_CHAIN_NCTF_B61 B61 DAISY_CHAIN_NCTF_B63 B63 DAISY_CHAIN_NCTF_C2 C2 RC185 1K_0402_1% RC185 1K_0402_1% 1 2 RC296 49.9_0402_1% @ RC296 49.9_0402_1% @ 1 2 Vinafix
  • 15. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DIMM_1 H:4mm Reverse SI : pop CD99 +V_VDDR_REFA_CA DDR_CKE0_DIMMA DDR_A_MA3 DDR_CS1_DIMMA# DDR_A_MA7 DDR_A_MA0 DDR_A_MA8 DDR_A_MA6 DDR_A_MA10 DDR_A_MA9 DDR_A_BS2 DDR_A_MA1 DDR_A_BS0 DDR_A_CAS# DDR_A_MA5 DDR_A_MA14 DDR_A_MA4 M_CLK_DDR0 M_CLK_DDR#0 DDR_A_MA13 DDR_A_MA11 DDR_A_MA2 DDR_A_MA12 DDR_A_MA15 DDR_A_WE# DDR_CKE1_DIMMA DDR_A_BS1 DDR_CS0_DIMMA# M_CLK_DDR#1 M_CLK_DDR1 DDR_A_RAS# M_ODT0 PCH_SMBCLK PCH_SMBDATA +V_VDDR_REFA_DQ SM_PG_CTRL M_ODT1 M_ODT3 M_ODT2 M_ODT1 M_ODT0 DDR3_DRAMRST# DDR_A_D17 DDR_A_D16 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D11 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_D27 DDR_A_D6 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D12 DDR_A_D20 DDR_A_D21 DDR_A_D30 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D43 DDR_A_D40 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D48 DDR_A_D32 DDR_A_D56 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D33 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D63 DDR_A_D36 DDR_A_D37 DDR_A_D39 DDR_A_D38 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D54 DDR_A_D55 DDR_A_D0 DDR_A_D4 DDR_A_D1 DDR_A_D14 DDR_A_D13 DDR_A_D9 DDR_A_D15 DDR_A_D18 DDR_A_D19 DDR_A_D23 DDR_A_D22 DDR_A_D24 DDR_A_D28 DDR_A_D25 DDR_A_D26 DDR_A_D31 DDR_A_D29 DDR_A_D34 DDR_A_D35 DDR_A_D41 DDR_A_D44 DDR_A_D42 DDR_A_D46 DDR_A_D45 DDR_A_D47 DDR_A_D49 DDR_A_D52 DDR_A_D5 DDR_A_D50 DDR_A_D51 DDR_A_D53 DDR_A_D57 DDR_A_D60 DDR_A_D58 DDR_A_D61 DDR_A_D59 DDR_A_D62 DDR_A_D10 DDR_A_D7 DDR_A_DQS#[0..7] <5> DDR_A_DQS[0..7] <5> DDR_A_MA[0..15] <5> DDR_A_BS2 <5> DDR_A_BS0 <5> DDR_A_WE# <5> DDR_A_CAS# <5> PCH_SMBDATA <16,18,21,6,7> DDR_A_D[0..63] <5> DDR_CKE1_DIMMA <5> PCH_SMBCLK <16,18,21,6,7> M_CLK_DDR#1 <5> M_CLK_DDR1 <5> DDR_CS0_DIMMA# <5> DDR_A_RAS# <5> DDR_A_BS1 <5> DDR_CKE0_DIMMA <5> M_CLK_DDR0 <5> M_CLK_DDR#0 <5> DDR_CS1_DIMMA# <5> DDR3_DRAMRST# <16,4> M_ODT2 <16> M_ODT3 <16> SM_PG_CTRL <4,49> +1.35V_VDDQ <11,16,17,34,4,49> +0.6V_0.675VS <16,49> +5VALW <19,24,26,29,30,32,34,37,48,49,56> +3VS <12,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +V_VDDR_REFA_CA <16,17> +V_VDDR_REFA_DQ <17> +3VS +V_VDDR_REFA_DQ +V_VDDR_REFA_CA +0.6V_0.675VS +0.6V_0.675VS +1.35V_VDDQ +1.35V_VDDQ +1.35V_VDDQ +1.35V_VDDQ +5VALW +1.35V_VDDQ +1.35V_VDDQ +0.6V_0.675VS +5VALW +3VS +V_VDDR_REFA_CA +V_VDDR_REFA_DQ Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDR3L DIMM0 C 15 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDR3L DIMM0 C 15 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date 0.1 DDR3L DIMM0 C 15 61 Saturday, January 31, 2015 2011/06/29 2011/06/29 LA-C701P CD65 1U_0402_6.3V6K CD65 1U_0402_6.3V6K 1 2 G D S QD1 BSS138_NL_SOT23-3 G D S QD1 BSS138_NL_SOT23-3 2 1 3 CD58 1U_0402_6.3V6K @ CD58 1U_0402_6.3V6K @ 1 2 CD66 1U_0402_6.3V6K CD66 1U_0402_6.3V6K 1 2 RD25 2M_0402_5% @ RD25 2M_0402_5% @ 1 2 CD9 10U_0603_6.3V6M @ CD9 10U_0603_6.3V6M @ 1 2 CD57 1U_0402_6.3V6K @ CD57 1U_0402_6.3V6K @ 1 2 CD24 10U_0603_6.3V6M CD24 10U_0603_6.3V6M 1 2 RD20 66.5_0402_1% RD20 66.5_0402_1% 1 2 CD99 0.1U_0402_16V7K ESD@ CD99 0.1U_0402_16V7K ESD@ 1 2 CD1 0.1U_0402_16V7K CD1 0.1U_0402_16V7K 1 2 CD21 0.1U_0402_16V7K CD21 0.1U_0402_16V7K 1 2 CD12 10U_0603_6.3V6M CD12 10U_0603_6.3V6M 1 2 CD63 1U_0402_6.3V6K CD63 1U_0402_6.3V6K 1 2 CD17 0.1U_0402_16V7K CD17 0.1U_0402_16V7K 1 2 CD19 0.1U_0402_16V7K CD19 0.1U_0402_16V7K 1 2 CD7 10U_0603_6.3V6M CD7 10U_0603_6.3V6M 1 2 CD3 0.1U_0402_16V7K CD3 0.1U_0402_16V7K 1 2 CD13 10U_0603_6.3V6M @ CD13 10U_0603_6.3V6M @ 1 2 RD24 66.5_0402_1% RD24 66.5_0402_1% 1 2 RD23 66.5_0402_1% RD23 66.5_0402_1% 1 2 CD56 1U_0402_6.3V6K @ CD56 1U_0402_6.3V6K @ 1 2 CD64 1U_0402_6.3V6K CD64 1U_0402_6.3V6K 1 2 CD8 10U_0603_6.3V6M CD8 10U_0603_6.3V6M 1 2 CD11 10U_0603_6.3V6M @ CD11 10U_0603_6.3V6M @ 1 2 RD21 220K_0402_5% RD21 220K_0402_5% 1 2 CD6 10U_0603_6.3V6M @ CD6 10U_0603_6.3V6M @ 1 2 RD22 66.5_0402_1% RD22 66.5_0402_1% 1 2 CD10 10U_0603_6.3V6M CD10 10U_0603_6.3V6M 1 2 JDIMM1 DEREN_40-42045-20404RHF CONN@ SP070012JA0 JDIMM1 DEREN_40-42045-20404RHF CONN@ SP070012JA0 VREF_DQ 1 VSS1 2 VSS2 3 DQ4 4 DQ0 5 DQ5 6 DQ1 7 VSS3 8 VSS4 9 DQS#0 10 DM0 11 DQS0 12 VSS5 13 VSS6 14 DQ2 15 DQ6 16 DQ3 17 DQ7 18 VSS7 19 VSS8 20 DQ8 21 DQ12 22 DQ9 23 DQ13 24 VSS9 25 VSS10 26 DQS#1 27 DM1 28 DQS1 29 RESET# 30 VSS11 31 VSS12 32 DQ10 33 DQ14 34 DQ11 35 DQ15 36 VSS13 37 VSS14 38 DQ16 39 DQ20 40 DQ17 41 DQ21 42 VSS15 43 VSS16 44 DQS#2 45 DM2 46 DQS2 47 VSS17 48 VSS18 49 DQ22 50 DQ18 51 DQ23 52 DQ19 53 VSS19 54 VSS20 55 DQ28 56 DQ24 57 DQ29 58 DQ25 59 VSS21 60 VSS22 61 DQS#3 62 DM3 63 DQS3 64 VSS23 65 VSS24 66 DQ26 67 DQ30 68 DQ27 69 DQ31 70 VSS25 71 VSS26 72 A12/BC# 83 A11 84 A9 85 A7 86 VDD5 87 VDD6 88 A8 89 A6 90 CKE0 73 CKE1 74 VDD1 75 VDD2 76 NC1 77 A15 78 BA2 79 A14 80 VDD3 81 VDD4 82 A5 91 A4 92 VDD7 93 VDD8 94 A3 95 A2 96 A1 97 A0 98 VDD9 99 VDD10 100 CK0 101 CK1 102 CK0# 103 CK1# 104 VDD11 105 VDD12 106 A10/AP 107 BA1 108 BA0 109 RAS# 110 VDD13 111 VDD14 112 WE# 113 S0# 114 CAS# 115 ODT0 116 VDD15 117 VDD16 118 A13 119 ODT1 120 S1# 121 NC2 122 VDD17 123 VDD18 124 NCTEST 125 VREF_CA 126 VSS27 127 VSS28 128 DQ32 129 DQ36 130 DQ33 131 DQ37 132 VSS29 133 VSS30 134 DQS#4 135 DM4 136 DQS4 137 VSS31 138 VSS32 139 DQ38 140 DQ34 141 DQ39 142 DQ35 143 VSS33 144 VSS34 145 DQ44 146 DQ40 147 DQ45 148 DQ41 149 VSS35 150 VSS36 151 DQS#5 152 DM5 153 DQS5 154 VSS37 155 VSS38 156 DQ42 157 DQ46 158 DQ43 159 DQ47 160 VSS39 161 VSS40 162 DQ48 163 DQ52 164 DQ49 165 DQ53 166 VSS41 167 VSS42 168 DQS#6 169 DM6 170 DQS6 171 VSS43 172 VSS44 173 DQ54 174 DQ50 175 DQ55 176 DQ51 177 VSS45 178 VSS46 179 DQ60 180 DQ56 181 DQ61 182 DQ57 183 VSS47 184 VSS48 185 DQS#7 186 DM7 187 DQS7 188 VSS49 189 VSS50 190 DQ58 191 DQ62 192 DQ59 193 DQ63 194 VSS51 195 VSS52 196 SA0 197 EVENT# 198 VDDSPD 199 SDA 200 SA1 201 SCL 202 VTT1 203 VTT2 204 G1 205 G2 206 CD55 1U_0402_6.3V6K CD55 1U_0402_6.3V6K 1 2