Acer Aspire E1-531_571 V3-531_571 Compal LA-7912P Q5WV1_Q5WS1 Rev0.2 schematic (1).pdf

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Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
Custom
1
Friday, January 06, 2012
2011/06/02 2012/06/02
Compal Electronics, Inc.
Title
Date: Sheet of
Custom
1
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
1
2011/06/02 2012/06/02
Intel Sandy/Ivy Bridge Processor with DDRIII + Panther Point PCH
Q5WV1 M/B Schematics Document
REV:0.2
Compal Confidential
2011-12-24
Nvidia N13P GS/GL
Model Name :Q5WV1/Q5WS1
File Name : LA-7912P
Compal Confidential
Compal Project Name :
SCHEMATIC,MB A7912
4019ID B
60
ZZZ2
X76344BOL01
1G@
ZZZ2
X76344BOL01
1G@
Part Number Description
DA60000SV00 PCB 0N4 LA-7912P REV0 M/B
MB PCB
Part Number Description
DA60000SV00 PCB 0N4 LA-7912P REV0 M/B
MB PCB
ZZZ3
X76344BOL02
2G@
ZZZ3
X76344BOL02
2G@

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USB port 10
USB port 13
USB port 11
100MHz
33MHz
100MHz
LS-7911P
100MHz
1GB/s x4
DMI x4
100MHz
FDI x8
page 41
port 3 port 1
Sub-board
page 39
page 13
SPI
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
RTC CKT.
page 13
3.3V 24MHz
LAN(GbE) &
Card Reader
BCM57785
page 35,36
MINI Card x1
CMOS Camera
WLAN
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
Dual Channel
2.7GT/s
Power On/Off CKT.
Touch Pad
LPC BUS
page 41
Processor
Int.KBD
page 40
BANK 0, 1, 2, 3
USB 2.0 conn x2
ALC271X/281X
DC/DC Interface CKT.
Sandy/Ivy Bridge
3.3V 48MHz
RJ45
page 39
Fan Control
Power Circuit DC/DC
page 40
204pin DDRIII-SO-DIMM X2
page 43,44
Intel
BIOS ROM
1.5V DDRIII 1066/1333
page 40
HDA Codec
Memory BUS(DDRIII)
PCH
HD Audio
page 42
page 4~10
Panther Point-M
page 11,12
page 40
ENE KB930/KB9012
page 36
page 37
page 38
page 38 page 31
rPGA989
Intel
Bluetooth
Conn
port 2
SATA CDROM
Conn. page 34
SPI ROM x1
page 41
page 46~59
USBx14
page 13~21
port 0
page 34
SATA HDD
Conn.
USB 2.0/B 2Port
USB Port0,1
Int. Speaker Phone Jack x 2
USB port 0,1 on
USB/B
989pin BGA
PCI-E 2.0x16 5GT/s PER LANE
100MHz
133MHz
LVDS Conn.
page 31
CRT Conn.
page 32
Nvidia
N13P GS/GL
page22~30
PEG(DIS)
page 33
HDMI Conn.
CRT(UMA/OPTIMUS)
LVDS(UMA/OPTIMUS)
TMDS(UMA/OPTIMUS)
USB 3.0 conn x1
Fresco FL1009
with USB3.0 Conn.
page 45
port 5
Card Reader
Conn. page 35,36
LS-7912P
page 41
PWR/B
port 1
MSATA(WWAN)
page 34
USB port 8
port 2
eDP
page31
SCHEMATIC,MB A7912
4019ID
60
B
WWW.AliSaler.Com

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USB 2.0 USB 1.1 Port
3 External
USB Port
Camera
USB/B (Right Side)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
EHCI1
EHCI2
USB Port Table
1101 0010b
ON OFF OFF
Board ID / SKU ID Table for AD channel
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator
+RTCVCC RTC power
+1.5VS
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
+3VS
+5VALW
+3VALW +3VALW always on power rail
+VSB +VSBP to +VSB always on power rail for sequence control ON ON*
ON
ON
ON
ON
BOARD ID Table
EC SM Bus1 address
Device
OFF
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
+1.5V to +1.5VS switched power rail
+CPU_CORE
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Vcc 3.3V +/- 5%
100K +/- 5%
Ra/Rc/Re
Board ID Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID V typ
AD_BID VAD_BID max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7 NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
PCH SM Bus address
Device
Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)
Address
Address Address
Voltage Rails
VIN
B+
+1.05VS_VTT
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON
ON
ON ON*
OFF
OFF
0.2
BTO Option Table
BTO Item BOM Structure
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
ON ON*
ON OFF OFF
+3VALW_PCH
+3V_LAN
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
+3VALW to +3V_LAN power rail for LAN
ON ON
ON ON
S1
+5VALW_PCH
S3 S5
ON
ON
ON ON
OFF
N/A N/A N/A
N/A
N/A
N/A
Power Plane Description
EC SM Bus2 address
Device
Smart Battery
OFF
OFF
+1.5VP to +1.5V power rail for DDRIII ON ON OFF
0.3
0001 011X b
ON*
OFF
DIS@
Dis with OPTIMUS
Blue Tooth BT@
Mini Card 1(WLAN)
+1.5V
+1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH
ON OFF OFF
+VGA_CORE
ON OFF OFF
Core voltage for GPU
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
+3VALW_EC +3VALW always to KBC ON ON ON*
ON*
+3VALW to +3VS power rail
+5VALWP to +5VALW power rail
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
+5VS +5VALW to +5VS switched power rail OFF
ON OFF
ON*
UMAO@
BT & USB30 & USB20 Config
BT SKU:BT@
UMA Only
DIS USB30 SKU:DUSB@
OPTMIUS SKU:DIS@
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF
Internal USB 3.0 PUSB@
N13P-GS:GS@
N13P-GL:GL@
0.4
internal USB SKU: PUSB@
eDP SKU: EDP@
LVDS SKU: LVDS@
EC 930 SKU: 930@ EC 9012 SKU: 9012@
PCH HM65: HM65@ PCH HM76: HM76@
Win8: WIN8@
N13P-GF108_ES4:GF108@
GS@
N13P-GS
N13P-GL GL@
Unpop
VRAM
CONN@
Connector
@
X76@
Win8
Audio ALC281X
271X@
Win8@
Audio ALC271X
281X@
PCH HM65 HM65@
PCH HM76 HM76@
BlueTooth
USB/B (Right Side)
USB3.0 colay USB2.0 Conn
eDP eDP@
SCHEMATIC,MB A7912
4019ID
60
B

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EDP_COMP
PEG_COMP
PEG_GTX_C_HRX_N0 PEG_GTX_HRX_N0
PEG_GTX_HRX_P0
PEG_GTX_C_HRX_P0
PEG_GTX_HRX_P1
PEG_GTX_C_HRX_P1
PEG_GTX_HRX_P2
PEG_GTX_C_HRX_P2
PEG_GTX_HRX_P3
PEG_GTX_C_HRX_P3
PEG_GTX_HRX_P4
PEG_GTX_C_HRX_P4
PEG_GTX_HRX_P5
PEG_GTX_C_HRX_P5
PEG_GTX_HRX_P6
PEG_GTX_C_HRX_P6
PEG_GTX_HRX_P7
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P8 PEG_GTX_HRX_P8
PEG_GTX_HRX_P15
PEG_GTX_C_HRX_P15
PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0
PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0
EDP_HPD#
DMI_CTX_PRX_P0
<15>
DMI_CRX_PTX_P0
<15>
DMI_CTX_PRX_N1
<15>
DMI_CRX_PTX_N1
<15>
DMI_CTX_PRX_P3
<15>
DMI_CRX_PTX_P3
<15>
DMI_CTX_PRX_P2
<15>
DMI_CTX_PRX_N0
<15>
DMI_CRX_PTX_N3
<15>
DMI_CRX_PTX_P2
<15>
DMI_CTX_PRX_N3
<15>
DMI_CTX_PRX_P1
<15>
DMI_CRX_PTX_N0
<15>
DMI_CRX_PTX_N2
<15>
DMI_CRX_PTX_P1
<15>
DMI_CTX_PRX_N2
<15>
FDI_CTX_PRX_N0
<15>
FDI_CTX_PRX_N1
<15>
FDI_CTX_PRX_N2
<15>
FDI_CTX_PRX_N3
<15>
FDI_CTX_PRX_N4
<15>
FDI_CTX_PRX_N5
<15>
FDI_CTX_PRX_N6
<15>
FDI_CTX_PRX_N7
<15>
FDI_CTX_PRX_P0
<15>
FDI_CTX_PRX_P1
<15>
FDI_CTX_PRX_P2
<15>
FDI_CTX_PRX_P3
<15>
FDI_CTX_PRX_P4
<15>
FDI_CTX_PRX_P5
<15>
FDI_CTX_PRX_P6
<15>
FDI_CTX_PRX_P7
<15>
FDI_FSYNC0
<15>
FDI_FSYNC1
<15>
FDI_INT
<15>
FDI_LSYNC0
<15>
FDI_LSYNC1
<15>
PEG_GTX_HRX_N[0..15] <22>
PEG_HTX_C_GRX_P[0..15] <22>
PEG_HTX_C_GRX_N[0..15] <22>
PEG_GTX_HRX_P[0..15] <22>
EDP_HPD#
<31>
EDP_AUXP
<31>
EDP_AUXN
<31>
EDP_TXP0
<31>
EDP_TXP1
<31>
EDP_TXN0
<31>
EDP_TXN1
<31>
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
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Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
eDP_COMPIO and ICOMPO signals should
be shorted near balls,
Trace Width for EDP_COMPIO=4mils,
EDP_ICOMPO=12mils,
and both length less than 500 mils...
should not be left floating
,even if disable eDP function...
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,
max length = 500 mils,trace width=4mils
PEG_ICOMPO signals should be routed with - max
length = 500 mils,trace width=12mils
spacing =15mils
Add eDP circuit
SCHEMATIC,MB A7912
4019ID
60
B
C47 0.22U_0402_10V6K
GSGL@
C47 0.22U_0402_10V6K
GSGL@
1 2
C52 0.22U_0402_10V6K
GSGL@
C52 0.22U_0402_10V6K
GSGL@
1 2
C528 0.22U_0402_10V6K
GSGL@
C528 0.22U_0402_10V6K
GSGL@
1 2
C552 0.22U_0402_10V6K
DIS@
C552 0.22U_0402_10V6K
DIS@
1 2
C106 0.22U_0402_10V6K
DIS@
C106 0.22U_0402_10V6K
DIS@
1 2
C49 0.22U_0402_10V6K
GSGL@
C49 0.22U_0402_10V6K
GSGL@
1 2
C556 0.22U_0402_10V6K
DIS@
C556 0.22U_0402_10V6K
DIS@
1 2
C100 0.22U_0402_10V6K
DIS@
C100 0.22U_0402_10V6K
DIS@
1 2
C66 0.22U_0402_10V6K
GSGL@
C66 0.22U_0402_10V6K
GSGL@
1 2
C51 0.22U_0402_10V6K
GSGL@
C51 0.22U_0402_10V6K
GSGL@
1 2
R809
1K_0402_5%
EDP@
R809
1K_0402_5%
EDP@
1
2
C93 0.22U_0402_10V6K
DIS@
C93 0.22U_0402_10V6K
DIS@
1 2
C533 0.22U_0402_10V6K
GSGL@
C533 0.22U_0402_10V6K
GSGL@
1 2
C56 0.22U_0402_10V6K
GSGL@
C56 0.22U_0402_10V6K
GSGL@
1 2
C92 0.22U_0402_10V6K
DIS@
C92 0.22U_0402_10V6K
DIS@
1 2
C547 0.22U_0402_10V6K
DIS@
C547 0.22U_0402_10V6K
DIS@
1 2
C520 0.22U_0402_10V6K
GSGL@
C520 0.22U_0402_10V6K
GSGL@
1 2
C86 0.22U_0402_10V6K
GSGL@
C86 0.22U_0402_10V6K
GSGL@
1 2
C551 0.22U_0402_10V6K
DIS@
C551 0.22U_0402_10V6K
DIS@
1 2
C557 0.22U_0402_10V6K
DIS@
C557 0.22U_0402_10V6K
DIS@
1 2
C515 0.22U_0402_10V6K
GSGL@
C515 0.22U_0402_10V6K
GSGL@
1 2
C75 0.22U_0402_10V6K
GSGL@
C75 0.22U_0402_10V6K
GSGL@
1 2
C129 0.22U_0402_10V6K
DIS@
C129 0.22U_0402_10V6K
DIS@
1 2
C553 0.22U_0402_10V6K
DIS@
C553 0.22U_0402_10V6K
DIS@
1 2
C548 0.22U_0402_10V6K
DIS@
C548 0.22U_0402_10V6K
DIS@
1 2
C541 0.22U_0402_10V6K
GSGL@
C541 0.22U_0402_10V6K
GSGL@
1 2
PCI
EXPRESS*
-
GRAPHICS
DMI
Intel(R)
FDI
eDP
JCPU1A
TYCO_2013620-2_IVY BRIDGE
CONN@
PCI
EXPRESS*
-
GRAPHICS
DMI
Intel(R)
FDI
eDP
JCPU1A
CONN@
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21
DMI_TX[2]
F20
FDI0_TX#[0]
A21
FDI0_TX#[1]
H19
FDI0_TX#[2]
E19
FDI0_TX#[3]
F18
FDI1_TX#[0]
B21
FDI1_TX#[1]
C20
FDI1_TX#[2]
D18
FDI1_TX#[3]
E17
FDI0_TX[0]
A22
FDI0_TX[1]
G19
FDI0_TX[2]
E20
FDI0_TX[3]
G18
FDI1_TX[0]
B20
FDI1_TX[1]
C19
FDI1_TX[2]
D19
FDI1_TX[3]
F17
FDI0_FSYNC
J18
FDI1_FSYNC
J17
FDI_INT
H20
FDI0_LSYNC
J19
FDI1_LSYNC
H17
PEG_ICOMPI J22
PEG_ICOMPO J21
PEG_RCOMPO H22
PEG_RX#[0] K33
PEG_RX#[1] M35
PEG_RX#[2] L34
PEG_RX#[3] J35
PEG_RX#[4] J32
PEG_RX#[5] H34
PEG_RX#[6] H31
PEG_RX#[7] G33
PEG_RX#[8] G30
PEG_RX#[9] F35
PEG_RX#[10] E34
PEG_RX#[11] E32
PEG_RX#[12] D33
PEG_RX#[13] D31
PEG_RX#[14] B33
PEG_RX#[15] C32
PEG_RX[0] J33
PEG_RX[1] L35
PEG_RX[2] K34
PEG_RX[3] H35
PEG_RX[4] H32
PEG_RX[5] G34
PEG_RX[6] G31
PEG_RX[7] F33
PEG_RX[8] F30
PEG_RX[9] E35
PEG_RX[10] E33
PEG_RX[11] F32
PEG_RX[12] D34
PEG_RX[13] E31
PEG_RX[14] C33
PEG_RX[15] B32
PEG_TX#[0] M29
PEG_TX#[1] M32
PEG_TX#[2] M31
PEG_TX#[3] L32
PEG_TX#[4] L29
PEG_TX#[5] K31
PEG_TX#[6] K28
PEG_TX#[7] J30
PEG_TX#[8] J28
PEG_TX#[9] H29
PEG_TX#[10] G27
PEG_TX#[11] E29
PEG_TX#[12] F27
PEG_TX#[13] D28
PEG_TX#[14] F26
PEG_TX#[15] E25
PEG_TX[0] M28
PEG_TX[1] M33
PEG_TX[2] M30
PEG_TX[3] L31
PEG_TX[4] L28
PEG_TX[5] K30
PEG_TX[6] K27
PEG_TX[7] J29
PEG_TX[8] J27
PEG_TX[9] H28
PEG_TX[10] G28
PEG_TX[11] E28
PEG_TX[12] F28
PEG_TX[13] D27
PEG_TX[14] E26
PEG_TX[15] D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_COMPIO
A18
eDP_HPD#
B16
eDP_ICOMPO
A17
C113 0.22U_0402_10V6K
DIS@
C113 0.22U_0402_10V6K
DIS@
1 2
R145
24.9_0402_1%
R145
24.9_0402_1%
1
2
R517
24.9_0402_1%
R517
24.9_0402_1%
1
2
C144 0.22U_0402_10V6K
DIS@
C144 0.22U_0402_10V6K
DIS@
1 2
C71 0.22U_0402_10V6K
GSGL@
C71 0.22U_0402_10V6K
GSGL@
1 2
C60 0.22U_0402_10V6K
GSGL@
C60 0.22U_0402_10V6K
GSGL@
1 2
C538 0.22U_0402_10V6K
GSGL@
C538 0.22U_0402_10V6K
GSGL@
1 2
C545 0.22U_0402_10V6K
GSGL@
C545 0.22U_0402_10V6K
GSGL@
1 2
C555 0.22U_0402_10V6K
DIS@
C555 0.22U_0402_10V6K
DIS@
1 2
C529 0.22U_0402_10V6K
GSGL@
C529 0.22U_0402_10V6K
GSGL@
1 2
C89 0.22U_0402_10V6K
DIS@
C89 0.22U_0402_10V6K
DIS@
1 2
C50 0.22U_0402_10V6K
GSGL@
C50 0.22U_0402_10V6K
GSGL@
1 2
C82 0.22U_0402_10V6K
GSGL@
C82 0.22U_0402_10V6K
GSGL@
1 2
C558 0.22U_0402_10V6K
DIS@
C558 0.22U_0402_10V6K
DIS@
1 2
C554 0.22U_0402_10V6K
DIS@
C554 0.22U_0402_10V6K
DIS@
1 2
C543 0.22U_0402_10V6K
GSGL@
C543 0.22U_0402_10V6K
GSGL@
1 2
C561 0.22U_0402_10V6K
DIS@
C561 0.22U_0402_10V6K
DIS@
1 2
C544 0.22U_0402_10V6K
GSGL@
C544 0.22U_0402_10V6K
GSGL@
1 2
C135 0.22U_0402_10V6K
DIS@
C135 0.22U_0402_10V6K
DIS@
1 2
C138 0.22U_0402_10V6K
DIS@
C138 0.22U_0402_10V6K
DIS@
1 2
C53 0.22U_0402_10V6K
GSGL@
C53 0.22U_0402_10V6K
GSGL@
1 2
C550 0.22U_0402_10V6K
DIS@
C550 0.22U_0402_10V6K
DIS@
1 2
C105 0.22U_0402_10V6K
DIS@
C105 0.22U_0402_10V6K
DIS@
1 2
C119 0.22U_0402_10V6K
DIS@
C119 0.22U_0402_10V6K
DIS@
1 2
C536 0.22U_0402_10V6K
GSGL@
C536 0.22U_0402_10V6K
GSGL@
1 2
C546 0.22U_0402_10V6K
DIS@
C546 0.22U_0402_10V6K
DIS@
1 2
C117 0.22U_0402_10V6K
DIS@
C117 0.22U_0402_10V6K
DIS@
1 2
C516 0.22U_0402_10V6K
GSGL@
C516 0.22U_0402_10V6K
GSGL@
1 2
C81 0.22U_0402_10V6K
GSGL@
C81 0.22U_0402_10V6K
GSGL@
1 2
C560 0.22U_0402_10V6K
DIS@
C560 0.22U_0402_10V6K
DIS@
1 2
C111 0.22U_0402_10V6K
DIS@
C111 0.22U_0402_10V6K
DIS@
1 2
C102 0.22U_0402_10V6K
DIS@
C102 0.22U_0402_10V6K
DIS@
1 2
C46 0.22U_0402_10V6K
GSGL@
C46 0.22U_0402_10V6K
GSGL@
1 2
C539 0.22U_0402_10V6K
GSGL@
C539 0.22U_0402_10V6K
GSGL@
1 2
C549 0.22U_0402_10V6K
DIS@
C549 0.22U_0402_10V6K
DIS@
1 2
C559 0.22U_0402_10V6K
DIS@
C559 0.22U_0402_10V6K
DIS@
1 2
C125 0.22U_0402_10V6K
DIS@
C125 0.22U_0402_10V6K
DIS@
1 2
C540 0.22U_0402_10V6K
GSGL@
C540 0.22U_0402_10V6K
GSGL@
1 2
C68 0.22U_0402_10V6K
GSGL@
C68 0.22U_0402_10V6K
GSGL@
1 2
C534 0.22U_0402_10V6K
GSGL@
C534 0.22U_0402_10V6K
GSGL@
1 2
C542 0.22U_0402_10V6K
GSGL@
C542 0.22U_0402_10V6K
GSGL@
1 2
WWW.AliSaler.Com

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_CATERR#
CLK_CPU_DMI#
CLK_CPU_DMI
H_THRMTRIP#
H_PROCHOT#_R
H_PM_SYNC
PM_DRAM_PWRGD_R
BUF_CPU_RST#
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
SM_DRAMRST#
H_PECI
H_PROCHOT#
BUFO_CPU_RST#
PLT_RST#
H_CPUPWRGD
XDP_DBRESET#
TCK
TMS
TRST#
TDI
TDO
CLK_CPU_DPLL
CLK_CPU_DPLL# CLK_CPU_DPLL
CLK_CPU_DPLL#
PM_DRAM_PWRGD_R
PM_SYS_PWRGD_BUF
BUF_CPU_RST#
BUF_CPU_RST#
H_PECI
<18,40>
H_SNB_IVB#
<17>
H_PM_SYNC
<15>
H_THRMTRIP#
<18>
H_CPUPWRGD
<18>
H_PROCHOT#
<40,46>
SM_DRAMRST# <6>
CLK_CPU_DMI# <14>
CLK_CPU_DMI <14>
PLT_RST#
<17>
XDP_DBRESET# <15>
CLK_CPU_DPLL <14>
CLK_CPU_DPLL# <14>
PM_DRAM_PWRGD
<15>
SYS_PWROK
<15>
+1.05VS_VTT
+3VS
+1.05VS_VTT
+3VS
+1.05VS_VTT
+3VALW
+1.5VS
Title
Date: Sheet of
Custom
5
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
5
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
5
2011/06/02 2012/06/02
DDR3 Compensation Signals
Processor Pullups
SNB_IVB# had changed the name to
PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH
SM_DRAMPWROK:DRAM power ok
UNCOREPWRGOOD:非CORE外的電OK
Buffered reset to CPU
RESET#:都ok後請CPU做reset
For LVDS
If use External Graphic or
use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
For eDP
R04 modify
SCHEMATIC,MB A7912
4019ID
60
B
R40
1K_0402_5%
R40
1K_0402_5%
1
2
T70
PAD @
T70
PAD @
R91 62_0402_5%
R91 62_0402_5%
1
2
T68
PAD @
T68
PAD @
R84 10K_0402_5%
R84 10K_0402_5%
1
2
T6 PAD
@
T6 PAD
@
T66
PAD @
T66
PAD @
U11
74AHC1G09GW_TSSOP5
U11
74AHC1G09GW_TSSOP5
B
1
A
2
G
3
O 4
P
5
R204 130_0402_5%
R204 130_0402_5%
1 2
R231 140_0402_1%
R231 140_0402_1%
1
2
R87
43_0402_1%
R87
43_0402_1%
1 2
R518 1K_0402_5%
LVDS@
R518 1K_0402_5%
LVDS@ 1
2
R92
56_0402_5%
R92
56_0402_5%
1 2
C162
0.1U_0402_16V4Z
C162
0.1U_0402_16V4Z
1
2
U7
SN74LVC1G07DCKR_SC70-5
U7
SN74LVC1G07DCKR_SC70-5
NC
1
A
2
G
3
Y 4
P
5
R571 200_0402_1%
R571 200_0402_1%
1
2
C307
0.1U_0402_16V4Z
C307
0.1U_0402_16V4Z
1
2
CLOCKS
MISC
THERMAL
PWR
MANAGEMENT
DDR3
MISC
JTAG
&
BPM
JCPU1B
CONN@
CLOCKS
MISC
THERMAL
PWR
MANAGEMENT
DDR3
MISC
JTAG
&
BPM
JCPU1B
CONN@
SM_RCOMP[1] A5
SM_RCOMP[2] A4
SM_DRAMRST# R8
SM_RCOMP[0] AK1
BCLK# A27
BCLK A28
DPLL_REF_CLK# A15
DPLL_REF_CLK A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY# AP29
PREQ# AP27
TCK AR26
TMS AR27
TRST# AP30
TDI AR28
TDO AP26
DBR# AL35
BPM#[0] AT28
BPM#[1] AR29
BPM#[2] AR30
BPM#[3] AT30
BPM#[4] AP32
BPM#[5] AR31
BPM#[6] AT31
BPM#[7] AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R516 1K_0402_5%
LVDS@
R516 1K_0402_5%
LVDS@ 1
2
R566 25.5_0402_1%
R566 25.5_0402_1%
1
2
T69
PAD @
T69
PAD @
T67
PAD @
T67
PAD @
R205
200_0402_1%
R205
200_0402_1%
1
2
R203
39_0402_1%
@
R203
39_0402_1%
@
1
2
R90
75_0402_1%
R90
75_0402_1%
1
2
C?
0.1U_0402_16V4Z
C?
0.1U_0402_16V4Z
1
2
R88
0_0402_5%
@
R88
0_0402_5%
@
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D63
DDR_A_D62
DDR_A_D8
DDR_A_D3
DDR_A_D4
DDR_A_D7
DDR_A_D5
DDR_A_D6
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D47
DDR_A_D46
DDR_A_D42
DDR_A_D43
DDR_A_D34
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_D38
DDR_A_D36
DDR_A_D37
DDR_A_D32
DDR_A_D33
DDR_A_D61
DDR_A_D60
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_D55
DDR_A_D54
DDR_A_D51
DDR_A_D48
DDR_A_D50
DDR_A_D49
DDR_A_D52
DDR_A_D53
DDR_A_D31
DDR_A_D14
DDR_A_D15
DDR_A_D25
DDR_A_D24
DDR_A_D26
DDR_A_D27
DDR_A_D30
DDR_A_D9
DDR_A_D13
DDR_A_D12
DDR_A_D10
DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_D19
DDR_A_D20
DDR_A_D16
DDR_A_D21
DDR_A_D17
DDR_A_D22
DDR_A_D18
DDR_A_D23
DDR_A_MA15
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS1
DDR_A_DQS6
DDR_A_DQS5
DDR_A_DQS4
DDR_A_DQS3
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS#0
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#3
DDR_A_DQS#1
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_MA0
DDR_A_MA14
DDR_A_MA5
DDR_A_MA4
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA9
DDR_A_MA7
DDR_A_MA6
DDR_A_MA12
DDR_A_MA13
DDR_A_MA8
DDR_A_MA11
DDR_A_MA10
DDR_B_D33
DDR_B_D14
DDR_B_D42
DDR_B_D59
DDR_B_D63
DDR_B_D43
DDR_B_D55
DDR_B_D53
DDR_B_D29
DDR_B_D24
DDR_B_D34
DDR_B_D4
DDR_B_D26
DDR_B_D13
DDR_B_D10
DDR_B_D21
DDR_B_D11
DDR_B_D57
DDR_B_D44
DDR_B_D0
DDR_B_D7
DDR_B_D46
DDR_B_D3
DDR_B_D15
DDR_B_D27
DDR_B_D30
DDR_B_D35
DDR_B_D40
DDR_B_D49
DDR_B_D23
DDR_B_D25
DDR_B_D19
DDR_B_D37
DDR_B_D48
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D47
DDR_B_D9
DDR_B_D60
DDR_B_D50
DDR_B_D62
DDR_B_D52
DDR_B_D2
DDR_B_D51
DDR_B_D56
DDR_B_D39
DDR_B_D22
DDR_B_D28
DDR_B_D6
DDR_B_D45
DDR_B_D17
DDR_B_D58
DDR_B_D61
DDR_B_D31
DDR_B_D54
DDR_B_D1
DDR_B_D41
DDR_B_D5
DDR_B_D12
DDR_B_D20
DDR_B_D38
DDR_B_D32
DDR_B_D16
DDR_B_MA15
DDR_B_DQS#1
DDR_B_DQS#7
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS#0
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS6
DDR_B_MA0
DDR_B_MA9
DDR_B_MA7
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_B_MA11
DDR_B_MA3
DDR_B_MA5
DDR_B_MA6
DDR_B_MA10
DDR_B_MA8
DDR_B_MA1
DDR_B_MA12
DDR_B_MA14
DIMM_DRAMRST#_R
SM_DRAMRST#
DDR_A_D[0..63]
<11>
DDR_A_BS0
<11>
DDR_A_BS1
<11>
DDR_A_BS2
<11>
DDR_A_WE#
<11>
DDR_A_RAS#
<11>
DDR_A_CAS#
<11>
SA_CLK_DDR0 <11>
SA_CLK_DDR#0 <11>
DDRA_CKE0_DIMMA <11>
SA_CLK_DDR1 <11>
SA_CLK_DDR#1 <11>
DDRA_CKE1_DIMMA <11>
DDRA_CS0_DIMMA# <11>
DDRA_CS1_DIMMA# <11>
SA_ODT0 <11>
SA_ODT1 <11>
DDR_A_DQS#[0..7] <11>
DDR_A_DQS[0..7] <11>
DDR_B_BS0
<12>
DDR_B_BS1
<12>
DDR_B_BS2
<12>
DDR_B_D[0..63]
<12>
DDR_B_WE#
<12>
DDR_B_RAS#
<12>
DDR_B_CAS#
<12>
DDRB_CS1_DIMMB# <12>
DDR_B_DQS[0..7] <12>
DDR_B_DQS#[0..7] <12>
SB_CLK_DDR0 <12>
SB_CLK_DDR#0 <12>
DDRB_CKE0_DIMMB <12>
SB_CLK_DDR1 <12>
DDRB_CS0_DIMMB# <12>
SB_ODT1 <12>
SB_ODT0 <12>
DDRB_CKE1_DIMMB <12>
SB_CLK_DDR#1 <12>
DDR_A_MA[0..15] <11> DDR_B_MA[0..15] <12>
DIMM_DRAMRST# <11,12>
SM_DRAMRST#
<5>
RST_GATE
<11,12,14>
+1.5V
Title
Date: Sheet of
Custom
6
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
6
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
6
2011/06/02 2012/06/02
CPU通知DIMM做reset
S0
RST_GATE hgih ,MOS ON
SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH
Dimm not reset
S3
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
S4,5
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# low
Dimm reset
Follow CRB1.0
R02 modify for ESD
SCHEMATIC,MB A7912
4019ID
60
B
R155
1K_0402_5%
R155
1K_0402_5%
1 2
R217
1K_0402_5%
R217
1K_0402_5%
1
2
C2065
0.1U_0402_16V4Z
C2065
0.1U_0402_16V4Z
1
2
DDR
SYSTEM
MEMORY
A
JCPU1C
CONN@
DDR
SYSTEM
MEMORY
A
JCPU1C
CONN@
SA_BS[0]
AE10
SA_BS[1]
AF10
SA_BS[2]
V6
SA_CAS#
AE8
SA_RAS#
AD9
SA_WE#
AF9
SA_CLK[0] AB6
SA_CLK[1] AA5
SA_CLK#[0] AA6
SA_CLK#[1] AB5
SA_CKE[0] V9
SA_CKE[1] V10
SA_CS#[0] AK3
SA_CS#[1] AL3
SA_ODT[0] AH3
SA_ODT[1] AG3
SA_DQS[0] D4
SA_DQS#[0] C4
SA_DQS[1] F6
SA_DQS#[1] G6
SA_DQS[2] K3
SA_DQS#[2] J3
SA_DQS[3] N6
SA_DQS#[3] M6
SA_DQS[4] AL5
SA_DQS#[4] AL6
SA_DQS[5] AM9
SA_DQS#[5] AM8
SA_DQS[6] AR11
SA_DQS#[6] AR12
SA_DQS[7] AM14
SA_DQS#[7] AM15
SA_MA[0] AD10
SA_MA[1] W1
SA_MA[2] W2
SA_MA[3] W7
SA_MA[4] V3
SA_MA[5] V2
SA_MA[6] W3
SA_MA[7] W6
SA_MA[8] V1
SA_MA[9] W5
SA_MA[10] AD8
SA_MA[11] V4
SA_MA[12] W4
SA_MA[13] AF8
SA_MA[14] V5
SA_MA[15] V7
SA_DQ[0]
C5
SA_DQ[1]
D5
SA_DQ[2]
D3
SA_DQ[3]
D2
SA_DQ[4]
D6
SA_DQ[5]
C6
SA_DQ[6]
C2
SA_DQ[7]
C3
SA_DQ[8]
F10
SA_DQ[9]
F8
SA_DQ[10]
G10
SA_DQ[11]
G9
SA_DQ[12]
F9
SA_DQ[13]
F7
SA_DQ[14]
G8
SA_DQ[15]
G7
SA_DQ[16]
K4
SA_DQ[17]
K5
SA_DQ[18]
K1
SA_DQ[19]
J1
SA_DQ[20]
J5
SA_DQ[21]
J4
SA_DQ[22]
J2
SA_DQ[23]
K2
SA_DQ[24]
M8
SA_DQ[25]
N10
SA_DQ[26]
N8
SA_DQ[27]
N7
SA_DQ[28]
M10
SA_DQ[29]
M9
SA_DQ[30]
N9
SA_DQ[31]
M7
SA_DQ[32]
AG6
SA_DQ[33]
AG5
SA_DQ[34]
AK6
SA_DQ[35]
AK5
SA_DQ[36]
AH5
SA_DQ[37]
AH6
SA_DQ[38]
AJ5
SA_DQ[39]
AJ6
SA_DQ[40]
AJ8
SA_DQ[41]
AK8
SA_DQ[42]
AJ9
SA_DQ[43]
AK9
SA_DQ[44]
AH8
SA_DQ[45]
AH9
SA_DQ[46]
AL9
SA_DQ[47]
AL8
SA_DQ[48]
AP11
SA_DQ[49]
AN11
SA_DQ[50]
AL12
SA_DQ[51]
AM12
SA_DQ[52]
AM11
SA_DQ[53]
AL11
SA_DQ[54]
AP12
SA_DQ[55]
AN12
SA_DQ[56]
AJ14
SA_DQ[57]
AH14
SA_DQ[58]
AL15
SA_DQ[59]
AK15
SA_DQ[60]
AL14
SA_DQ[61]
AK14
SA_DQ[62]
AJ15
SA_DQ[63]
AH15
RSVD_TP[1] AB4
RSVD_TP[2] AA4
RSVD_TP[4] AB3
RSVD_TP[5] AA3
RSVD_TP[3] W9
RSVD_TP[6] W10
RSVD_TP[7] AG1
RSVD_TP[8] AH1
RSVD_TP[9] AG2
RSVD_TP[10] AH2
G
D
S
Q12
S TR SSM3K7002F 1N SC59-3
G
D
S
Q12
2
1
3
R186
4.99K_0402_1%
R186
4.99K_0402_1%
1
2
DDR
SYSTEM
MEMORY
B
JCPU1D
CONN@
DDR
SYSTEM
MEMORY
B
JCPU1D
CONN@
SB_BS[0]
AA9
SB_BS[1]
AA7
SB_BS[2]
R6
SB_CAS#
AA10
SB_RAS#
AB8
SB_WE#
AB9
SB_CLK[0] AE2
SB_CLK[1] AE1
SB_CLK#[0] AD2
SB_CLK#[1] AD1
SB_CKE[0] R9
SB_CKE[1] R10
SB_ODT[0] AE4
SB_ODT[1] AD4
SB_DQS[4] AN6
SB_DQS#[4] AN5
SB_DQS[5] AP8
SB_DQS#[5] AP9
SB_DQS[6] AK11
SB_DQS#[6] AK12
SB_DQS[7] AP14
SB_DQS#[7] AP15
SB_DQS[0] C7
SB_DQS#[0] D7
SB_DQS[1] G3
SB_DQS#[1] F3
SB_DQS[2] J6
SB_DQS#[2] K6
SB_DQS[3] M3
SB_DQS#[3] N3
SB_MA[0] AA8
SB_MA[1] T7
SB_MA[2] R7
SB_MA[3] T6
SB_MA[4] T2
SB_MA[5] T4
SB_MA[6] T3
SB_MA[7] R2
SB_MA[8] T5
SB_MA[9] R3
SB_MA[10] AB7
SB_MA[11] R1
SB_MA[12] T1
SB_MA[13] AB10
SB_MA[14] R5
SB_MA[15] R4
SB_DQ[0]
C9
SB_DQ[1]
A7
SB_DQ[2]
D10
SB_DQ[3]
C8
SB_DQ[4]
A9
SB_DQ[5]
A8
SB_DQ[6]
D9
SB_DQ[7]
D8
SB_DQ[8]
G4
SB_DQ[9]
F4
SB_DQ[10]
F1
SB_DQ[11]
G1
SB_DQ[12]
G5
SB_DQ[13]
F5
SB_DQ[14]
F2
SB_DQ[15]
G2
SB_DQ[16]
J7
SB_DQ[17]
J8
SB_DQ[18]
K10
SB_DQ[19]
K9
SB_DQ[20]
J9
SB_DQ[21]
J10
SB_DQ[22]
K8
SB_DQ[23]
K7
SB_DQ[24]
M5
SB_DQ[25]
N4
SB_DQ[26]
N2
SB_DQ[27]
N1
SB_DQ[28]
M4
SB_DQ[29]
N5
SB_DQ[30]
M2
SB_DQ[31]
M1
SB_DQ[32]
AM5
SB_DQ[33]
AM6
SB_DQ[34]
AR3
SB_DQ[35]
AP3
SB_DQ[36]
AN3
SB_DQ[37]
AN2
SB_DQ[38]
AN1
SB_DQ[39]
AP2
SB_DQ[40]
AP5
SB_DQ[41]
AN9
SB_DQ[42]
AT5
SB_DQ[43]
AT6
SB_DQ[44]
AP6
SB_DQ[45]
AN8
SB_DQ[46]
AR6
SB_DQ[47]
AR5
SB_DQ[48]
AR9
SB_DQ[49]
AJ11
SB_DQ[50]
AT8
SB_DQ[51]
AT9
SB_DQ[52]
AH11
SB_DQ[53]
AR8
SB_DQ[54]
AJ12
SB_DQ[55]
AH12
SB_DQ[56]
AT11
SB_DQ[57]
AN14
SB_DQ[58]
AR14
SB_DQ[59]
AT14
SB_DQ[60]
AT12
SB_DQ[61]
AN15
SB_DQ[62]
AR15
SB_DQ[63]
AT15
RSVD_TP[11] AB2
RSVD_TP[12] AA2
RSVD_TP[13] T9
RSVD_TP[14] AA1
RSVD_TP[15] AB1
RSVD_TP[16] T10
SB_CS#[0] AD3
SB_CS#[1] AE3
RSVD_TP[17] AD6
RSVD_TP[18] AE6
RSVD_TP[19] AD5
RSVD_TP[20] AE5
C293
0.047U_0402_16V7K
C293
0.047U_0402_16V7K
1
2
R184
0_0402_5%
@R184
0_0402_5%
@
1 2
WWW.AliSaler.Com

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VSSAXG_VAL_SENSE
CFG4
CFG6
CFG5
CFG2
CFG7
VCC_VAL_SENSE
CFG2
CFG0
CFG4
CFG5
CFG6
CFG7
VAXG_VAL_SENSE
VSS_VAL_SENSE
+CPU_CORE +VGFX_CORE
Title
Date: Sheet of
Custom
7
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
7
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
7
2011/06/02 2012/06/02
AH27 change to VCC_DIE_SENSE
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
PCIE Port Bifurcation Straps
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
1: (Default) PEG Train immediately following xxRESETB
de assertion
CFG4
Display Port Presence Strap
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG Straps for Processor
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
*
*
*
AH26
Sandy Ivy
VSS_DIE_SENSE
GND
RSVD54 and RSVD55 had changed to
BCLK_ITP and BCLK_ITP#
SCHEMATIC,MB A7912
4019ID
60
B
T74
PAD
@ T74
PAD
@
R810
49.9_0402_1%
@
R810
49.9_0402_1%
@
1
2
R813
49.9_0402_1%
@
R813
49.9_0402_1%
@
1
2
R108
1K_0402_5%
@
R108
1K_0402_5%
@
1
2
R107
1K_0402_5%
GM@
R107
1K_0402_5%
GM@
1
2
R812
49.9_0402_1%
@
R812
49.9_0402_1%
@
1
2
R811
49.9_0402_1%
@
R811
49.9_0402_1%
@
1
2
RESERVED
CFG
JCPU1E
CONN@
RESERVED
CFG
JCPU1E
CONN@
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34 AM33
RSVD35 AJ27
RSVD38 J16
RSVD_NCTF2 AT34
RSVD39 H16
RSVD40 G16
RSVD_NCTF1 AR35
RSVD_NCTF3 AT33
RSVD_NCTF5 AR34
RSVD_NCTF11 AT2
RSVD_NCTF12 AT1
RSVD_NCTF13 AR1
RSVD_NCTF6 B34
RSVD_NCTF7 A33
RSVD_NCTF8 A34
RSVD_NCTF9 B35
RSVD_NCTF10 C35
RSVD51 AJ32
RSVD52 AK32
RSVD27
J15
RSVD16
C30
RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30
RSVD19
B29
RSVD22
A30
RSVD21
B31
RSVD23
C29
RSVD37 T8
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G25
RSVD13
G24
RSVD14
E23
RSVD32 W8
RSVD33 AT26
RSVD_NCTF4 AP35
RSVD10
F23
RSVD5
AJ26
VAXG_VAL_SENSE
AJ31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ33
VSS_VAL_SENSE
AH33
KEY B1
VCC_DIE_SENSE AH27
BCLK_ITP AN35
BCLK_ITP# AM35
VSS_DIE_SENSE AH26
RSVD31 AK2
RSVD30 AE7
RSVD29 AG7
RSVD28 L7
RSVD24
J20
RSVD25
B18
R102
1K_0402_5%
@
R102
1K_0402_5%
@
1
2
R109
1K_0402_5%
EDP@
R109
1K_0402_5%
EDP@
1
2
T8 PAD
@
T8 PAD
@
R112
1K_0402_5%
R112
1K_0402_5%
1
2
T7
PAD
@ T7
PAD
@

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VSSIO_SENSE
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
VSSSENSE_R
VCCSENSE_R
H_CPU_SVIDDAT
VCCIO_SENSE <50>
VCCSENSE <52>
VSSSENSE <52>
VR_SVID_ALRT# <52>
VR_SVID_CLK <52>
VR_SVID_DAT <52>
VSSIO_SENSE <50>
+1.05VS_VTT
+1.05VS_VTT
+CPU_CORE
+1.05VS_VTT
+CPU_CORE
+1.05VS_VTT
Title
Date: Sheet of
Custom
8
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
8
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
8
2011/06/02 2012/06/02
8.5A
QC 53A
DC 53A
SV type CPU
Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.
Place the PU
resistors close to CPU
VSSIO_SENSE
change to
VSS_SENSE_VCCIO
SCHEMATIC,MB A7912
4019ID
60
B
R163
10_0402_5%
R163
10_0402_5%
1
2
R445
100_0402_1%
R445
100_0402_1%
1
2
R448
43_0402_1%
R448
43_0402_1%
1 2
R447
75_0402_5%
R447
75_0402_5%
1
2
R910 10_0402_5%
R910 10_0402_5%
1 2
R446 0_0402_5%
R446 0_0402_5%
1 2
R449 0_0402_5%
R449 0_0402_5%
1 2
POWER
CORE
SUPPLY
PEG
AND
DDR
SENSE
LINES
SVID
JCPU1F
TYCO_2013620-2_IVY BRIDGE CONN@
POWER
CORE
SUPPLY
PEG
AND
DDR
SENSE
LINES
SVID
JCPU1F
TYCO_2013620-2_IVY BRIDGE CONN@
VCC_SENSE AJ35
VSS_SENSE AJ34
VIDALERT# AJ29
VIDSCLK AJ30
VIDSOUT AJ28
VSS_SENSE_VCCIO A10
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VCCIO1 AH13
VCCIO12 J11
VCCIO18 G12
VCCIO19 F14
VCCIO20 F13
VCCIO21 F12
VCCIO22 F11
VCCIO23 E14
VCCIO24 E12
VCCIO2 AH10
VCCIO3 AG10
VCCIO4 AC10
VCCIO5 Y10
VCCIO6 U10
VCCIO7 P10
VCCIO8 L10
VCCIO9 J14
VCCIO10 J13
VCCIO11 J12
VCCIO13 H14
VCCIO14 H12
VCCIO15 H11
VCCIO16 G14
VCCIO17 G13
VCCIO25 E11
VCCIO32 C12
VCCIO33 C11
VCCIO34 B14
VCCIO35 B12
VCCIO36 A14
VCCIO37 A13
VCCIO38 A12
VCCIO39 A11
VCCIO26 D14
VCCIO27 D13
VCCIO28 D12
VCCIO29 D11
VCCIO30 C14
VCCIO31 C13
VCCIO_SENSE B10
VCCIO40 J23
R443 0_0402_5%
R443 0_0402_5%
1 2
R444 0_0402_5%
R444 0_0402_5%
1 2
R450
130_0402_1%
R450
130_0402_1%
1
2
R442
100_0402_1%
R442
100_0402_1%
1
2
WWW.AliSaler.Com

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SB_DIMM_VREFDQ
VCCIO_SEL
+V_SM_VREF
H_VCCSA_VID0
H_VCCSA_VID1
SA_DIMM_VREFDQ
+VCCSA_SENSE
+VCCSA
+VCCPLL
VCCIO_SEL
VCC_AXG_SENSE <52>
VSS_AXG_SENSE <52>
+VCCSA_SENSE <51>
H_VCCSA_VID1 <51>
H_VCCSA_VID0 <51>
SA_DIMM_VREFDQ <11>
SB_DIMM_VREFDQ <12>
+VGFX_CORE
+1.5VS
+1.5VS
+VGFX_CORE
+VCCSA
+1.8VS
+3VALW
Title
Date: Sheet of
Custom
9
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
9
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
9
2011/06/02 2012/06/02
5A
QC 46A
DC 33A
+V_SM_VREF should
have 20 mil trace width
1.2A
INTEL Recommend
1*330uF,3*10uF
from CR PDDG 0.8
1
0
0
1
Sandy Ivy
V
V
V
V
X
V
Vout
0.9V
0.8V
0.725V
VCCSA
VID0 VID1
0 0
6A
1
1 V
X
0.675V
*
VCCIO_SEL For 2012 CPU support
1/NC : (Default) +1.05VS_VTT
A19
0: +1.0VS_VTT
RSVD26 had changed the name to VCCIO_SEL
Need PH +3VALW 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select
INTEL Recommend
1*330uF,1*10uF and 2*1uF(0402)
from CR PDDG 0.8
INTEL Recommend
1*330uF,6*10uF
from CR PDDG 0.8
SCHEMATIC,MB A7912
4019ID
60
B
R575
1K_0402_1%
R575
1K_0402_1%
1
2
+
C355
330U_D2_2V_Y
+
C355
330U_D2_2V_Y
1
2
C654
1U_0402_6.3V6K
C654
1U_0402_6.3V6K
1
2
C830
10U_0603_6.3V6M
C830
10U_0603_6.3V6M
1
2
C213
10U_0603_6.3V6M
C213
10U_0603_6.3V6M
1
2
R903
10_0402_5%
R903
10_0402_5%
1
2
+
C664
330U_D2_2V_Y
@
+
C664
330U_D2_2V_Y
@
1
2
C653
1U_0402_6.3V6K
C653
1U_0402_6.3V6K
1
2
R913
10K_0402_5%
@
R913
10K_0402_5%
@
1
2
C655
10U_0603_6.3V6M
C655
10U_0603_6.3V6M
1
2
C365
10U_0603_6.3V6M
C365
10U_0603_6.3V6M
1
2
R528 0_0805_5%
R528 0_0805_5%
1 2
C219
10U_0603_6.3V6M
C219
10U_0603_6.3V6M
1
2
C829
10U_0603_6.3V6M
C829
10U_0603_6.3V6M
1
2
R138
0_0402_5%
@
R138
0_0402_5%
@
1
2
C363
10U_0603_6.3V6M
C363
10U_0603_6.3V6M
1
2
C214
10U_0603_6.3V6M
C214
10U_0603_6.3V6M
1
2
R582
1K_0402_1%
R582
1K_0402_1%
1
2
C605
10U_0603_6.3V6M
C605
10U_0603_6.3V6M
1
2
POWER
GRAPHICS
DDR3
-1.5V
RAILS
SENSE
LINES
1.8V
RAIL
SA
RAIL
VREF
MISC
JCPU1G
CONN@
POWER
GRAPHICS
DDR3
-1.5V
RAILS
SENSE
LINES
1.8V
RAIL
SA
RAIL
VREF
MISC
JCPU1G
CONN@
SM_VREF AL1
VSSAXG_SENSE AK34
VAXG_SENSE AK35
VAXG1
AT24
VAXG2
AT23
VAXG3
AT21
VAXG4
AT20
VAXG5
AT18
VAXG6
AT17
VAXG7
AR24
VAXG8
AR23
VAXG9
AR21
VAXG10
AR20
VAXG11
AR18
VAXG12
AR17
VAXG13
AP24
VAXG14
AP23
VAXG15
AP21
VAXG16
AP20
VAXG17
AP18
VAXG18
AP17
VAXG19
AN24
VAXG20
AN23
VAXG21
AN21
VAXG22
AN20
VAXG23
AN18
VAXG24
AN17
VAXG25
AM24
VAXG26
AM23
VAXG27
AM21
VAXG28
AM20
VAXG29
AM18
VAXG30
AM17
VAXG31
AL24
VAXG32
AL23
VAXG33
AL21
VAXG34
AL20
VAXG35
AL18
VAXG36
AL17
VAXG37
AK24
VAXG38
AK23
VAXG39
AK21
VAXG40
AK20
VAXG41
AK18
VAXG42
AK17
VAXG43
AJ24
VAXG44
AJ23
VAXG45
AJ21
VAXG46
AJ20
VAXG47
AJ18
VAXG48
AJ17
VAXG49
AH24
VAXG50
AH23
VAXG51
AH21
VAXG52
AH20
VAXG53
AH18
VAXG54
AH17
VDDQ11 U4
VDDQ12 U1
VDDQ13 P7
VDDQ14 P4
VDDQ15 P1
VDDQ1 AF7
VDDQ2 AF4
VDDQ3 AF1
VDDQ4 AC7
VDDQ5 AC4
VDDQ6 AC1
VDDQ7 Y7
VDDQ8 Y4
VDDQ9 Y1
VDDQ10 U7
VCCPLL1
B6
VCCPLL2
A6
VCCSA1 M27
VCCSA2 M26
VCCSA3 L26
VCCSA4 J26
VCCSA5 J25
VCCSA6 J24
VCCSA7 H26
VCCSA8 H25
VCCSA_SENSE H23
VCCSA_VID[1] C24
VCCPLL3
A2
VCCSA_VID[0] C22
SA_DIMM_VREFDQ B4
SB_DIMM_VREFDQ D1
VCCIO_SEL A19
C364
10U_0603_6.3V6M
C364
10U_0603_6.3V6M
1
2
+ C221
330U_D2_2V_Y
@
+ C221
330U_D2_2V_Y
@
1
2
C341
10U_0603_6.3V6M
C341
10U_0603_6.3V6M
1
2
C362
10U_0603_6.3V6M
C362
10U_0603_6.3V6M
1
2
C361
10U_0603_6.3V6M
C361
10U_0603_6.3V6M
1
2
C831
10U_0603_6.3V6M
C831
10U_0603_6.3V6M
1
2
C688
0.1U_0402_16V4Z
C688
0.1U_0402_16V4Z
1
2
C828
10U_0603_6.3V6M
C828
10U_0603_6.3V6M
1
2
R137 0_0402_5%
@
R137 0_0402_5%
@
1 2
R904
10_0402_5%
R904
10_0402_5%
1
2
R909
10K_0402_5%
R909
10K_0402_5%
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
Custom
10
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
10
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
10
2011/06/02 2012/06/02
SCHEMATIC,MB A7912
4019ID
60
B
VSS
JCPU1I
CONN@
VSS
JCPU1I
CONN@
VSS161
T35
VSS162
T34
VSS163
T33
VSS164
T32
VSS165
T31
VSS166
T30
VSS167
T29
VSS168
T28
VSS169
T27
VSS170
T26
VSS171
P9
VSS172
P8
VSS173
P6
VSS174
P5
VSS175
P3
VSS176
P2
VSS177
N35
VSS178
N34
VSS179
N33
VSS180
N32
VSS181
N31
VSS182
N30
VSS183
N29
VSS184
N28
VSS185
N27
VSS186
N26
VSS187
M34
VSS188
L33
VSS189
L30
VSS190
L27
VSS191
L9
VSS192
L8
VSS193
L6
VSS194
L5
VSS195
L4
VSS196
L3
VSS197
L2
VSS198
L1
VSS199
K35
VSS200
K32
VSS201
K29
VSS202
K26
VSS203
J34
VSS204
J31
VSS205
H33
VSS206
H30
VSS207
H27
VSS208
H24
VSS209
H21
VSS210
H18
VSS211
H15
VSS212
H13
VSS213
H10
VSS214
H9
VSS215
H8
VSS216
H7
VSS217
H6
VSS218
H5
VSS219
H4
VSS220
H3
VSS221
H2
VSS222
H1
VSS223
G35
VSS224
G32
VSS225
G29
VSS226
G26
VSS227
G23
VSS228
G20
VSS229
G17
VSS230
G11
VSS231
F34
VSS232
F31
VSS233
F29
VSS234 F22
VSS235 F19
VSS236 E30
VSS237 E27
VSS238 E24
VSS239 E21
VSS240 E18
VSS241 E15
VSS242 E13
VSS243 E10
VSS244 E9
VSS245 E8
VSS246 E7
VSS247 E6
VSS248 E5
VSS249 E4
VSS250 E3
VSS251 E2
VSS252 E1
VSS253 D35
VSS254 D32
VSS255 D29
VSS256 D26
VSS257 D20
VSS258 D17
VSS259 C34
VSS260 C31
VSS261 C28
VSS262 C27
VSS263 C25
VSS264 C23
VSS265 C10
VSS266 C1
VSS267 B22
VSS268 B19
VSS269 B17
VSS270 B15
VSS271 B13
VSS272 B11
VSS273 B9
VSS274 B8
VSS275 B7
VSS276 B5
VSS277 B3
VSS278 B2
VSS279 A35
VSS280 A32
VSS281 A29
VSS282 A26
VSS283 A23
VSS284 A20
VSS285 A3
VSS
JCPU1H
CONN@
VSS
JCPU1H
CONN@
VSS1
AT35
VSS2
AT32
VSS3
AT29
VSS4
AT27
VSS5
AT25
VSS6
AT22
VSS7
AT19
VSS8
AT16
VSS9
AT13
VSS10
AT10
VSS11
AT7
VSS12
AT4
VSS13
AT3
VSS14
AR25
VSS15
AR22
VSS16
AR19
VSS17
AR16
VSS18
AR13
VSS19
AR10
VSS20
AR7
VSS21
AR4
VSS22
AR2
VSS23
AP34
VSS24
AP31
VSS25
AP28
VSS26
AP25
VSS27
AP22
VSS28
AP19
VSS29
AP16
VSS30
AP13
VSS31
AP10
VSS32
AP7
VSS33
AP4
VSS34
AP1
VSS35
AN30
VSS36
AN27
VSS37
AN25
VSS38
AN22
VSS39
AN19
VSS40
AN16
VSS41
AN13
VSS42
AN10
VSS43
AN7
VSS44
AN4
VSS45
AM29
VSS46
AM25
VSS47
AM22
VSS48
AM19
VSS49
AM16
VSS50
AM13
VSS51
AM10
VSS52
AM7
VSS53
AM4
VSS54
AM3
VSS55
AM2
VSS56
AM1
VSS57
AL34
VSS58
AL31
VSS59
AL28
VSS60
AL25
VSS61
AL22
VSS62
AL19
VSS63
AL16
VSS64
AL13
VSS65
AL10
VSS66
AL7
VSS67
AL4
VSS68
AL2
VSS69
AK33
VSS70
AK30
VSS71
AK27
VSS72
AK25
VSS73
AK22
VSS74
AK19
VSS75
AK16
VSS76
AK13
VSS77
AK10
VSS78
AK7
VSS79
AK4
VSS80
AJ25
VSS81 AJ22
VSS82 AJ19
VSS83 AJ16
VSS84 AJ13
VSS85 AJ10
VSS86 AJ7
VSS87 AJ4
VSS88 AJ3
VSS89 AJ2
VSS90 AJ1
VSS91 AH35
VSS92 AH34
VSS93 AH32
VSS94 AH30
VSS95 AH29
VSS96 AH28
VSS98 AH25
VSS99 AH22
VSS100 AH19
VSS101 AH16
VSS102 AH7
VSS103 AH4
VSS104 AG9
VSS105 AG8
VSS106 AG4
VSS107 AF6
VSS108 AF5
VSS109 AF3
VSS110 AF2
VSS111 AE35
VSS112 AE34
VSS113 AE33
VSS114 AE32
VSS115 AE31
VSS116 AE30
VSS117 AE29
VSS118 AE28
VSS119 AE27
VSS120 AE26
VSS121 AE9
VSS122 AD7
VSS123 AC9
VSS124 AC8
VSS125 AC6
VSS126 AC5
VSS127 AC3
VSS128 AC2
VSS129 AB35
VSS130 AB34
VSS131 AB33
VSS132 AB32
VSS133 AB31
VSS134 AB30
VSS135 AB29
VSS136 AB28
VSS137 AB27
VSS138 AB26
VSS139 Y9
VSS140 Y8
VSS141 Y6
VSS142 Y5
VSS143 Y3
VSS144 Y2
VSS145 W35
VSS146 W34
VSS147 W33
VSS148 W32
VSS149 W31
VSS150 W30
VSS151 W29
VSS152 W28
VSS153 W27
VSS154 W26
VSS155 U9
VSS156 U8
VSS157 U6
VSS158 U5
VSS159 U3
VSS160 U2
WWW.AliSaler.Com

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V_DDR_REFA
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D10
DDR_A_D11
DDR_A_D18
DDR_A_D19
DDR_A_D26
DDR_A_D27
DDR_A0_DM0
DDR_A0_DM3
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_D17
DDR_A_D9
DDR_A_D16
DDR_A_D25
DDR_A_D24
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA12
DDR_A_MA13
DDR_A0_DM5
DDR_A0_DM7
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_BS0
DDR_A_BS2
DDRA_CS1_DIMMA#
SA_CLK_DDR0
SA_CLK_DDR#0
DDRA_CKE0_DIMMA
DDR_A_CAS#
DDR_A_WE#
DDR_A_D33
DDR_A_D48
DDR_A_D36
DDR_A_D37
DDR_A_D45
DDR_A_D46
DDR_A_D52
DDR_A_D53
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_A_MA14
DDR_A0_DM4
DDR_A0_DM6
DDR_A_DQS5
DDR_A_DQS7
DDR_A_DQS#5
DDR_A_DQS#7
DDR_A_BS1
DDRA_CS0_DIMMA#
SA_CLK_DDR1
SA_CLK_DDR#1
DDRA_CKE1_DIMMA
DDR_A_RAS#
D_CK_SDATA
D_CK_SCLK
SA_ODT0
SA_ODT1
DDR_A_D63
DDR_A_MA15
+VREF_CA
DDR_A_D39
DDR_A_D54
DDR_A_D38
DDR_A_D47
DDR_A_D44
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D21
DDR_A_D28
DDR_A_D29
DDR_A0_DM1
DDR_A0_DM2
DDR_A_DQS0
DDR_A_DQS3
DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_D23
DDR_A_D31
DDR_A_D13
DDR_A_D20
DDR_A_D30
DDR_A_D14
DDR_A_D15
DDR_A_D12
DDR_A_D22
DDR_A0_DM5
DDR_A0_DM3
DDR_A0_DM7
DDR_A0_DM0
DDR_A0_DM1
DDR_A0_DM6
DDR_A0_DM4
DDR_A0_DM2
DDR3_DRAMRST#
DDRA_CS1_DIMMA#
<6>
DDR_A_CAS#
<6>
DDR_A_WE#
<6>
DDR_A_BS0
<6>
SA_CLK_DDR#0
<6>
SA_CLK_DDR0
<6>
DDR_A_BS2
<6>
DDRA_CKE0_DIMMA
<6> DDRA_CKE1_DIMMA <6>
SA_CLK_DDR1 <6>
SA_CLK_DDR#1 <6>
DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDRA_CS0_DIMMA# <6>
SA_ODT0 <6>
SA_ODT1 <6>
D_CK_SDATA <12,14,41>
D_CK_SCLK <12,14,41>
RST_GATE
<6,12,14>
SA_DIMM_VREFDQ
<9> DDR_A_D[0..63] <6>
DDR_A_DQS[0..7] <6>
DDR_A_DQS#[0..7] <6>
DDR_A_MA[0..15] <6>
+1.5V
+3VS
+0.75VS +0.75VS
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+0.75VS
+1.5V
Title
Date: Sheet of
Custom
11
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
11
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
11
2011/06/02 2012/06/02
All VREF traces should
<Address(SA1,SA0): 00>
DIMM_1 Reserve H:8mm
M3 support
Layout Note:
Place near JDIMM1.203,204
CHG C407 to oscon
Layout Note:
Place near JDIMM1
R02 modify for ESD
SCHEMATIC,MB A7912
4019ID
60
B
R267
1K_0402_5%
R267
1K_0402_5%
1
2
C385
1U_0402_6.3V6K
C385
1U_0402_6.3V6K
1
2
C408
2.2U_0603_6.3V6K
C408
2.2U_0603_6.3V6K
1
2
C2066
0.1U_0402_16V4Z
C2066
0.1U_0402_16V4Z
1
2
C383
10U_0603_6.3V6M
@
C383
10U_0603_6.3V6M
@
1
2
C414
10U_0603_6.3V6M
C414
10U_0603_6.3V6M
1
2
C413
10U_0603_6.3V6M
C413
10U_0603_6.3V6M
1
2
C372
2.2U_0603_6.3V6K
C372
2.2U_0603_6.3V6K
1
2
R302
10K_0402_5%
R302
10K_0402_5%
1
2
+
C407
330U_D2_2V_Y
@
+
C407
330U_D2_2V_Y
@
1
2
C373
0.1U_0402_16V4Z
C373
0.1U_0402_16V4Z
1
2
C395
1U_0402_6.3V6K
C395
1U_0402_6.3V6K
1
2
R133
0_0402_5%
@R133
0_0402_5%
@
1 2
C394
1U_0402_6.3V6K
C394
1U_0402_6.3V6K
1
2
C404
0.1U_0402_16V4Z
C404
0.1U_0402_16V4Z
1
2
R266
1K_0402_5%
R266
1K_0402_5%
1
2
R320
1K_0402_5%
R320
1K_0402_5%
1
2
C409
1U_0402_6.3V6K
C409
1U_0402_6.3V6K
1
2
R301
10K_0402_5%
R301
10K_0402_5%
1
2
C412
10U_0603_6.3V6M
C412
10U_0603_6.3V6M
1
2
G
D
S
Q46
S TR SSM3K7002F 1N SC59-3 @
G
D
S
Q46
2
1
3
C415
10U_0603_6.3V6M
C415
10U_0603_6.3V6M
1
2
C371
1U_0402_6.3V6K
C371
1U_0402_6.3V6K
1
2
C388
1U_0402_6.3V6K
C388
1U_0402_6.3V6K
1
2
C410
1U_0402_6.3V6K
C410
1U_0402_6.3V6K
1
2
C416
2.2U_0603_6.3V6K
C416
2.2U_0603_6.3V6K
1
2
C384
10U_0603_6.3V6M
C384
10U_0603_6.3V6M
1
2
R319
1K_0402_5%
R319
1K_0402_5%
1
2
C393
1U_0402_6.3V6K
C393
1U_0402_6.3V6K
1
2
C411
0.1U_0402_16V4Z
C411
0.1U_0402_16V4Z
1
2
JDIMM1
FOX_AS0A626-U8SN-7F
CONN@
JDIMM1
FOX_AS0A626-U8SN-7F
CONN@
VREF_DQ
1 VSS1 2
VSS2
3 DQ4 4
DQ0
5 DQ5 6
DQ1
7 VSS3 8
VSS4
9 DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C378
10U_0603_6.3V6M
C378
10U_0603_6.3V6M
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V_DDR_REFC
DDR_B0_DM5
DDR_B0_DM3
DDR_B0_DM7
DDR_B0_DM0
DDR_B0_DM1
DDR_B0_DM6
DDR_B0_DM4
DDR_B0_DM2
D_CK_SDATA
D_CK_SCLK
+VREF_CC
DDR_B0_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D1
DDR_B_D0
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B0_DM3
DDR_B_D26
DDR_B_D27
DDR_B_D5
DDR_B_DQS#0
DDR_B_D4
DDR_B_DQS0
DDR_B_D22
DDR_B_D20
DDR3_DRAMRST#
DDR_B0_DM1
DDR_B_D23
DDR_B_D21
DDR_B_DQS#3
DDR_B_D14
DDR_B0_DM2
DDR_B_DQS3
DDR_B_D7
DDR_B_D6
DDR_B_D15
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D12
DDR_B_D31
DDR_B_D13
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
SB_CLK_DDR0
SB_CLK_DDR#0
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_CS1_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B0_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B0_DM7
DDRB_CKE0_DIMMB
DDR_B_D58
DDR_B_D59
DDR_B_MA15
DDR_B_MA7
SB_ODT0
DDR_B_MA14
DDR_B_MA6
DDRB_CKE1_DIMMB
DDR_B_MA4
DDR_B_BS1
SB_ODT1
SB_CLK_DDR1
DDR_B_RAS#
SB_CLK_DDR#1
DDR_B_MA2
DDR_B_MA11
DDR_B_MA0
DDRB_CS0_DIMMB#
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
DDR_B_D52
DDR_B_D36
DDR_B_D37
DDR_B_D44
DDR_B_D54
DDR_B_D53
DDR_B_D46
DDR_B_D45
DDR_B_D38
DDR_B_D55
DDR_B_D47
DDR_B0_DM6
DDR_B_DQS#5
DDR_B0_DM4
DDR_B_D60
DDR_B_D39
DDR_B_DQS5
D_CK_SDATA <11,14,41>
D_CK_SCLK <11,14,41>
DDRB_CS1_DIMMB#
<6>
DDR_B_CAS#
<6>
DDR_B_WE#
<6>
DDR_B_BS0
<6>
SB_CLK_DDR#0
<6>
SB_CLK_DDR0
<6>
DDRB_CKE0_DIMMB
<6>
DDR_B_BS2
<6>
SB_CLK_DDR#1 <6>
DDR_B_BS1 <6>
DDR_B_RAS# <6>
DDRB_CS0_DIMMB# <6>
SB_ODT0 <6>
SB_ODT1 <6>
SB_CLK_DDR1 <6>
DDRB_CKE1_DIMMB <6>
DDR_B_D[0..63] <6>
DDR_B_DQS[0..7] <6>
DDR_B_DQS#[0..7] <6>
DDR_B_MA[0..15] <6>
RST_GATE
<6,11,14>
SB_DIMM_VREFDQ
<9>
+3VS
+0.75VS
+0.75VS
+0.75VS
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V +1.5V
+3VS
+1.5V
Title
Date: Sheet of
Custom
12
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
12
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
12
2011/06/02 2012/06/02
All VREF traces should
Layout Note:
Place near JDIMM2.203,204
Layout Note:
Place near JDIMM2
<Address(SA1,SA0): 10>
DIMM_2 Reserve H:4mm
M3 support
CHG C359 to oscon
SCHEMATIC,MB A7912
4019ID
60
B
C440
1U_0402_6.3V6K
C440
1U_0402_6.3V6K
1
2
R350
1K_0402_5%
R350
1K_0402_5%
1
2
C437
0.1U_0402_16V4Z
C437
0.1U_0402_16V4Z
1
2
C449
10U_0603_6.3V6M
C449
10U_0603_6.3V6M
1
2
C427
1U_0402_6.3V6K
C427
1U_0402_6.3V6K
1
2
C448
10U_0603_6.3V6M
C448
10U_0603_6.3V6M
1
2
R340
1K_0402_5%
R340
1K_0402_5%
1
2
G
D
S
Q47
G
D
S
Q47
2
1
3
+
C359
330U_2.5V_M
+
C359
330U_2.5V_M
1
2
C430
1U_0402_6.3V6K
C430
1U_0402_6.3V6K
1
2
R346
0_0402_5%
@R346
0_0402_5%
@
1 2
JDIMM2
FOX_AS0A626-U4RN-7F
CONN@
JDIMM2
FOX_AS0A626-U4RN-7F
CONN@
VREF_DQ
1 VSS1 2
VSS2
3 DQ4 4
DQ0
5 DQ5 6
DQ1
7 VSS3 8
VSS4
9 DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C436
2.2U_0603_6.3V6K
C436
2.2U_0603_6.3V6K
1
2
C438
2.2U_0603_6.3V6K
C438
2.2U_0603_6.3V6K
1
2
R344
10K_0402_5%
R344
10K_0402_5%
1
2
C425
10U_0603_6.3V6M
C425
10U_0603_6.3V6M
1
2
C444
1U_0402_6.3V6K
C444
1U_0402_6.3V6K
1
2
C429
1U_0402_6.3V6K
C429
1U_0402_6.3V6K
1
2
R345
10K_0402_5%
R345
10K_0402_5%
1
2
C445
1U_0402_6.3V6K
C445
1U_0402_6.3V6K
1
2
C450
10U_0603_6.3V6M
C450
10U_0603_6.3V6M
1
2
C439
1U_0402_6.3V6K
C439
1U_0402_6.3V6K
1
2
C426
10U_0603_6.3V6M
@
C426
10U_0603_6.3V6M
@
1
2
R341
1K_0402_5%
R341
1K_0402_5%
1
2
C428
1U_0402_6.3V6K
C428
1U_0402_6.3V6K
1
2
C447
10U_0603_6.3V6M
C447
10U_0603_6.3V6M
1
2
C446
0.1U_0402_16V4Z
C446
0.1U_0402_16V4Z
1
2
C451
2.2U_0603_6.3V6K
C451
2.2U_0603_6.3V6K
1
2
R351
1K_0402_5%
R351
1K_0402_5%
1
2
C424
10U_0603_6.3V6M
C424
10U_0603_6.3V6M
1
2
C435
0.1U_0402_16V4Z
C435
0.1U_0402_16V4Z
1
2
WWW.AliSaler.Com

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_RTCX1
PCH_RTCX2
PCH_RTCX1
PCH_RTCRST#
SM_INTRUDER#
PCH_INTVRMEN
SM_INTRUDER#
PCH_SPKR
PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_CS0#_1
PCH_JTAG_TCK
PCH_SATALED#
PCH_SRTCRST#
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
HDA_SYNC_PCH
HDA_RST_PCH#
HDA_SDIN0
HDA_SDOUT_PCH
PCH_RTCX2
HDA_BITCLK_PCH
LPC_AD2
LPC_FRAME#
LPC_AD0
LPC_AD3
LPC_AD1
SERIRQ
PCH_GPIO19
SATA_COMP
RBIAS_SATA3
SATA3_COMP
HDA_BITCLK_PCH
HDA_RST_PCH#
HDA_SDOUT_PCH
PCH_INTVRMEN
PCH_SPKR
HDA_SDOUT_PCH
HDA_SYNC_PCH
HDA_SYNC_PCH_R
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
SGEN#
SERIRQ
PCH_SATALED#
PCH_GPIO19
+RTCBATT_R
PCH_SPI_MISO_1
PCH_SPI_CS0#_1
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
SPI_WP1#
SPI_HOLD1#
SPI_WP1#
SPI_HOLD1#
PCH_SPI_CLK_1
SGEN#
HDA_SYNC_PCH
HDA_SYNC_PCH_R
PCH_SPI_CLK_2
PCH_SPI_CLK
PCH_SPI_CS0#_2
PCH_SPI_MOSI_2
PCH_SPI_MISO_2
SPI_HOLD2#
SPI_WP2#
PCH_SPI_CS0#_2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2
PCH_SPI_MISO_2
SPI_WP2#
SPI_HOLD2#
PCH_SPI_CLK_2
PCH_SPI_VCC
PCH_SPKR
<42>
HDA_SDIN0
<42>
SERIRQ <40>
SATA_PRX_DTX_P0 <34>
SATA_PTX_DRX_N0 <34>
SATA_PTX_DRX_P0 <34>
SATA_PRX_DTX_N0 <34>
LPC_AD0 <40>
LPC_AD1 <40>
LPC_AD2 <40>
LPC_AD3 <40>
LPC_FRAME# <40>
HDA_SYNC_AUDIO
<42>
HDA_SDOUT_AUDIO
<42>
HDA_RST_AUDIO#
<42>
HDA_BITCLK_AUDIO
<42>
PCH_SATALED# <41>
ME_EN
<40>
+RTCVCC
+RTCVCC
+1.05VS_VTT
+1.05VS_VTT
+3VS
+3VALW_PCH
+3VALW_PCH
+3VS
+CHGRTC
+RTCVCC
+RTCBATT
+3VS
+3VS
+3VS
+RTCBATT
+3VS
+3VS
+3VS
Title
Date: Sheet of
Custom
13
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
13
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
13
2011/06/02 2012/06/02
SRTCRST close RAM door
RTCRST close RAM door
HDD
H：Integrated VRM enable
L：Integrated VRM disable
INTVRMEN
*
LOW= Disable (Default)
HIGH= Enable ( No Reboot )
*
* Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
*
(INTVRMEN should always be pull high.)
ME debug mode,this signal has a weak internal PD
HDA_SDO as Capella ME override (GPIO33)
Boot BIOS GPIO19
0
1
SPI
-
GPIO51
Reserved
LPC
Boot BIOS Strap
1 1
0
*
0
1
0
ODD
20mil
20mil
This part had been re-modified
be careful,if link symbol!!
SPI ROM FOR ME (4MB)
Footprint 200mil
Rserve the 2M ROM for Win8
GPIO21
0
1
*
Switchable GPU
Non-Switchable
SGEN#
Prevent back drive issue.
MSATA
Modify R02
R02 Modify
Modify R03
Co-lay NPCE885N
R04 modify
R04 modify
Modify R04
Delete Co-lay NPCE885N
SCHEMATIC,MB A7912
4019ID
60
B
R375
1K_0402_5%
R375
1K_0402_5%
1
2
R684 33_0402_5%
R684 33_0402_5%
1 2
T75 @
PAD T75 @
PAD
R2050 33_0402_5%
WIN8@
R2050 33_0402_5%
WIN8@
1 2
C360
1U_0603_10V6K
C360
1U_0603_10V6K
1
2
T76 @
PAD T76 @
PAD
JCMOS1
SHORT
PADS
@
JCMOS1
SHORT
PADS
@
1
2
C2049
33P_0402_50V8K
@ C2049
33P_0402_50V8K
@
C682
15P_0402_50V8J
C682
15P_0402_50V8J
1
2
C686
15P_0402_50V8J
C686
15P_0402_50V8J
1
2
U42
MX25L1606EM2I-12G_SO8
WIN8@
U42
MX25L1606EM2I-12G_SO8
WIN8@
CS#
1
SO 2
WP#
3
GND
4
VCC 8
HOLD#
7
SCLK 6
SI 5
R792
1M_0402_5%
R792
1M_0402_5%
1
2
R248 20K_0402_1%
R248 20K_0402_1%
1 2
R539 1K_0402_5%
R539 1K_0402_5%
1
2
JBATT1
SUYIN_060003HA002G202ZL
CONN@
JBATT1
SUYIN_060003HA002G202ZL
CONN@
+
1
-
2
R260
37.4_0402_1%
R260
37.4_0402_1%
1 2
R703
3.3K_0402_5%
WIN8@
R703
3.3K_0402_5%
WIN8@
1 2
R704
3.3K_0402_5%
WIN8@
R704
3.3K_0402_5%
WIN8@
1 2
R259
10K_0402_5%
R259
10K_0402_5%
1
2
R241
49.9_0402_1%
R241
49.9_0402_1%
1 2
R734 33_0402_5%
WIN8@
R734 33_0402_5%
WIN8@ 1
2
R640 10K_0402_5%
R640 10K_0402_5%
1
2
R624 4.7K_0402_5%
R624 4.7K_0402_5%
1 2
R667 3.3K_0402_5%
R667 3.3K_0402_5%
1 2
R542
33_0402_5%
R542
33_0402_5%
1 2
C893
33P_0402_50V8K
@
C893
33P_0402_50V8K
@
C471
0.1U_0402_16V4Z
C471
0.1U_0402_16V4Z
1
2
R568 10M_0402_5%
R568 10M_0402_5%
1 2
R243 20K_0402_1%
R243 20K_0402_1%
1 2
R652 33_0402_5%
R652 33_0402_5%
1 2
T77 @
PAD T77 @
PAD
R294 1K_0402_5%
@
R294 1K_0402_5%
@
1 2
R544
33_0402_5%
R544
33_0402_5%
1 2
Y3
32.768KHZ_12.5PF_9H03200019
Y3
32.768KHZ_12.5PF_9H03200019
1 2
R2048
22_0402_5%
@ R2048
22_0402_5%
@1 2
R674
51_0402_5%
@R674
51_0402_5%
@
1
2
R557
0_0402_5%
R557
0_0402_5%
1
2
R733 33_0402_5%
WIN8@
R733 33_0402_5%
WIN8@ 1
2
R625
750_0402_1%
R625
750_0402_1%
1 2
R585 330K_0402_5%
R585 330K_0402_5%
1 2
R556
1K_0402_5%
@
R556
1K_0402_5%
@ 1
2
R567 1M_0402_5%
R567 1M_0402_5%
1 2
R540
0_0402_5%
@
R540
0_0402_5%
@
1 2
RTC
IHDA
SATA
LPC
SPI
JTAG
SATA
6G
U33A
COUGARPOINT_FCBGA989~D
SA00004EEY0
HM65@
RTC
IHDA
SATA
LPC
SPI
JTAG
SATA
6G
U33A
SA00004EEY0
HM65@
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED# P3
FWH0 / LAD0 C38
FWH1 / LAD1 A38
FWH2 / LAD2 B37
FWH3 / LAD3 C37
LDRQ1# / GPIO23 K36
FWH4 / LFRAME# D36
LDRQ0# E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_EN# / GPIO33
C36
HDA_DOCK_RST# / GPIO13
N32
SRTCRST#
G22
SATA0RXN AM3
SATA0RXP AM1
SATA0TXN AP7
SATA0TXP AP5
SATA1RXN AM10
SATA1RXP AM8
SATA1TXN AP11
SATA1TXP AP10
SATA2RXN AD7
SATA2RXP AD5
SATA2TXN AH5
SATA2TXP AH4
SATA3RXN AB8
SATA3RXP AB10
SATA3TXN AF3
SATA3TXP AF1
SATA4RXN Y7
SATA4RXP Y5
SATA4TXN AD3
SATA4TXP AD1
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
SATA5TXP AB1
SATAICOMPI Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP / GPIO21 V14
SATA1GP / GPIO19 P1
JTAG_TCK
J3
JTAG_TMS
H7
JTAG_TDI
K5
JTAG_TDO
H1
SERIRQ V5
SPKR
T10
SATAICOMPO Y11
SATA3COMPI AB13
SATA3RCOMPO AB12
SATA3RBIAS AH1
U36
32M W25Q32BVSSIG_SO8
U36
32M W25Q32BVSSIG_SO8
CS#
1
SO/SIO1 2
WP#
3
GND
4
VCC 8
HOLD#
7
SCLK 6
SI/SIO0 5
R275 10K_0402_5%
R275 10K_0402_5%
1
2
G
D
S
Q36
G
D
S
Q36
2
1
3
U33
BD82HM77 QPRG C1 BGA 989P
HM77@
SA00005AGE0
U33
BD82HM77 QPRG C1 BGA 989P
HM77@
SA00005AGE0
R545
33_0402_5%
R545
33_0402_5%
1 2
R258
10K_0402_5%
@
R258
10K_0402_5%
@
1
2
C356
1U_0603_10V6K
C356
1U_0603_10V6K
1
2
JME1
SHORT
PADS
@
JME1
SHORT
PADS
@
1
2
R866
22_0402_5%
@
R866
22_0402_5%
@
1 2
D13
CHN202UPT_SC70-3
D13
CHN202UPT_SC70-3
1
2
3
R654 3.3K_0402_5%
R654 3.3K_0402_5%
1 2
R681 33_0402_5%
R681 33_0402_5%
1 2
R555
33_0402_5%
R555
33_0402_5%
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_GPIO11
PCH_SMBCLK
PCH_SMBDATA
XTAL25_IN
XTAL25_OUT
PCH_SML1CLK
PCH_SML1DATA
XCLK_RCOMP
CLK_PCI_LPBACK
CLK_CPU_DMI
CLK_CPU_DMI#
PCH_GPIO46
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2
PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N1
PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1
CLK_PCI_LPBACK
MINI1_CLKREQ#
PCH_GPIO45
XTAL25_OUT
XTAL25_IN
RST_GATE
CLK_FLEX2
LAN_CLKREQ#
MINI2_CLKREQ#
PCH_GPIO44
MINI1_CLKREQ#
USB30_CLKREQ#
PCH_GPIO45
PCH_GPIO46
PCH_SML1CLK
PCH_SML1DATA
EC_SMB_CK2
EC_SMB_DA2
CLKIN_GND1#
CLKIN_GND1
PCH_GPIO73
LAN_CLKREQ#
PEG_CLKREQ#_R
PCH_GPIO73
PCH_GPIO47
PCH_GPIO11
PCH_SMBCLK
PCH_SMBDATA
PCH_SML1CLK
PCH_SML1DATA
RST_GATE
PCH_GPIO47
USB30_CLKREQ#
PCH_GPIO74
PCH_GPIO74
DGPU_PRSNT#
D_CK_SCLK
D_CK_SDATA
PCH_SMBDATA
PCH_SMBCLK
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
CLK_BUF_ICH_14M
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLK_PEG_VGA#
CLK_PEG_VGA
DGPU_PRSNT#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
CLK_FLEX0
PCH_GPIO44
CLK_FLEX1
CLK_CPU_DPLL#
CLK_CPU_DPLL
PEG_CLKREQ#_R
MINI2_CLKREQ#
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
PCIE_PRX_DTX_N1
<35>
PCIE_PTX_C_DRX_N1
<35>
PCIE_PRX_DTX_P1
<35>
PCIE_PTX_C_DRX_P1
<35>
PCIE_PRX_DTX_N2
<37>
PCIE_PRX_DTX_P2
<37>
PCIE_PTX_C_DRX_N2
<37>
PCIE_PTX_C_DRX_P2
<37>
CLK_PCIE_MINI1#
<37>
CLK_PCIE_MINI1
<37>
MINI1_CLKREQ#
<37>
CLK_PCI_LPBACK <17>
PCH_SMBCLK <37>
PCH_SMBDATA <37>
RST_GATE <6,11,12>
EC_SMB_CK2 <22,40>
EC_SMB_DA2 <22,40>
CLK_PCIE_LAN#
<35>
CLK_PCIE_LAN
<35>
LAN_CLKREQ#
<35>
CLK_PEG_VGA#
<22>
CLK_PEG_VGA
<22>
D_CK_SDATA <11,12,41>
D_CK_SCLK <11,12,41>
CLK_CPU_DPLL# <5>
CLK_CPU_DPLL <5>
PEG_CLKREQ#
<22>
VGA_ON
<17,25,44,51,53>
+1.05VS_VTT
+3VALW_PCH
+3VS
+3VS
+3VALW_PCH
+3VS
+3VS
+3VS
+3VS
+3VALW_PCH
Title
Date: Sheet of
Custom
14
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
14
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
14
2011/06/02 2012/06/02
PCIE LAN
Mini Card 1 (WLAN)
Reserve for EMI please close to U33
Mini Card 1(WLAN)
PCIE LAN
Pull down 10K ohm
for using internal Clock
For DDR
Pull up at EC side.
For VGA,EC
GPIO67
0
1
DIS,OPTIMUS
UMA
DGPU_PRSNT#
120 MHz for eDP
Pull high @ VGA side
for safe
R02 Modify
R02 modify
SCHEMATIC,MB A7912
4019ID
60
B
R175 10K_0402_5%
R175 10K_0402_5%
1 2
R642 2.2K_0402_5%
R642 2.2K_0402_5%
1 2
Q38B
DMN66D0LDW-7_SOT363-6
Q38B
3 4
5
R273 10K_0402_5%
R273 10K_0402_5%
1
2
R669
4.7K_0402_5%
R669
4.7K_0402_5%
1 2
R238 10K_0402_5%
R238 10K_0402_5%
1
2
R160
10K_0402_5%
DIS@
R160
10K_0402_5%
DIS@
1
2
T29 PAD
@
T29 PAD
@
R233 10K_0402_5%
R233 10K_0402_5%
1 2
R662 2.2K_0402_5%
R662 2.2K_0402_5%
1 2
R264 10K_0402_5%
R264 10K_0402_5%
1 2
R280 10K_0402_5%
R280 10K_0402_5%
1 2
R663
10K_0402_5%
R663
10K_0402_5%
1
2
G
D
S
Q39
2N7002H_SOT23-3
DIS@
G
D
S
Q39
2N7002H_SOT23-3
DIS@
2
1
3
T73 PAD
@
T73 PAD
@
R234 10K_0402_5%
R234 10K_0402_5%
1 2
R647 10K_0402_5%
R647 10K_0402_5%
1 2
C672 .1U_0402_16V7K
C672 .1U_0402_16V7K
1 2
R561 10K_0402_5%
R561 10K_0402_5%
1 2
C630
10P_0402_50V8J
C630
10P_0402_50V8J
1
2
R293 10K_0402_5%
R293 10K_0402_5%
1
2
R630 10K_0402_5%
@
R630 10K_0402_5%
@ 1
2
R563 10K_0402_5%
R563 10K_0402_5%
1 2
Y2 25MHZ 10PF 7V25000014
Y2 25MHZ 10PF 7V25000014
GND
2
3
3 1 1
GND
4
R526
90.9_0402_1%
R526
90.9_0402_1%
1 2
C677 .1U_0402_16V7K
C677 .1U_0402_16V7K
1 2
Q38A
Q38A
6 1
2
T9 PAD
@
T9 PAD
@
R295 10K_0402_5%
R295 10K_0402_5%
1
2
R618 10K_0402_5%
R618 10K_0402_5%
1
2
R220 10K_0402_5%
R220 10K_0402_5%
1 2
R608 1K_0402_5%
R608 1K_0402_5%
1
2
C669 .1U_0402_16V7K
C669 .1U_0402_16V7K
1 2
R530
33_0402_5%
@R530
33_0402_5%
@
1
2
R668
2.2K_0402_5%
@
R668
2.2K_0402_5%
@
1
2
R638 10K_0402_5%
R638 10K_0402_5%
1
2
R644
2.2K_0402_5%
@
R644
2.2K_0402_5%
@
1
2
R670
4.7K_0402_5%
R670
4.7K_0402_5%
1 2
Q40B
Q40B
3 4
5
R159
10K_0402_5%
UMAO@
R159
10K_0402_5%
UMAO@
1
2
R631
0_0402_5%
DIS@
R631
0_0402_5%
DIS@ 1
2
R240 10K_0402_5%
R240 10K_0402_5%
1 2
R632
10K_0402_5%
DIS@
R632
10K_0402_5%
DIS@
1
2
PCI-E*
CLOCKS
FLEX
CLOCKS
SMBUS
Controller
Link
U33B
HM65@
PCI-E*
CLOCKS
FLEX
CLOCKS
SMBUS
Controller
Link
U33B
HM65@
PERN1
BG34
PERP1
BJ34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ38
PERP6
BG38
PERN7
BG40
PERP7
BJ40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_DMI2_N BJ30
CLKIN_DMI2_P BG30
CLKIN_DMI_N BF18
CLKIN_DMI_P BE18
CLKIN_DOT_96N G24
CLKIN_DOT_96P E24
CLKIN_SATA_N / CKSSCD_N AK7
CLKIN_SATA_P / CKSSCD_P AK5
XTAL25_IN V47
XTAL25_OUT V49
REFCLK14IN K45
CLKIN_PCILOOPBACK H45
CLKOUT_PEG_A_N AB37
CLKOUT_PEG_A_P AB38
PEG_A_CLKRQ# / GPIO47 M10
PCIECLKRQ0# / GPIO73
J2
M1
V10
A8
L12
L14
CLKOUTFLEX0 / GPIO64 K43
CLKOUTFLEX1 / GPIO65 F47
CLKOUTFLEX2 / GPIO66 H47
CLKOUTFLEX3 / GPIO67 K49
CLKOUT_DMI_N AV22
CLKOUT_DMI_P AU22
PEG_B_CLKRQ# / GPIO56
E6
CLKOUT_PEG_B_P
AB40
CLKOUT_PEG_B_N
AB42
XCLK_RCOMP Y47
CLKOUT_DP_P / CLKOUT_BCLK1_P AM13
CLKOUT_DP_N / CLKOUT_BCLK1_N AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK14
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AK13
SMBALERT# / GPIO11 E12
SMBCLK H14
SMBDATA C9
SML0ALERT# / GPIO60 A12
SML0CLK C8
SML0DATA G12
SML1ALERT# / PCHHOT# / GPIO74 C13
SML1CLK / GPIO58 E14
SML1DATA / GPIO75 M16
CL_CLK1 M7
CL_DATA1 T11
CL_RST1# P10
T13
Q40A
Q40A
6 1
2
C642
22P_0402_50V8J
@C642
22P_0402_50V8J
@
1 2
R265 10K_0402_5%
R265 10K_0402_5%
1 2
C631
10P_0402_50V8J
C631
10P_0402_50V8J
1
2
R643 2.2K_0402_5%
R643 2.2K_0402_5%
1 2
R527 1M_0402_5%
R527 1M_0402_5%
1 2
R221 10K_0402_5%
R221 10K_0402_5%
1 2
R653 10K_0402_5%
R653 10K_0402_5%
1
2
R677 2.2K_0402_5%
R677 2.2K_0402_5%
1 2
C675 .1U_0402_16V7K
C675 .1U_0402_16V7K
1 2
WWW.AliSaler.Com

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_IRCOMP
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CRX_PTX_N2
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_P2
DMI_CTX_PRX_N1
DMI_CRX_PTX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CRX_PTX_N3
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC1
FDI_LSYNC0
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P5
PCH_GPIO72
RI#
SUSACK#_R
RBIAS_CPY
SUSWARN#
PM_DRAM_PWRGD
PCH_RSMRST#
PBTN_OUT#
PCH_ACIN
DSWODVREN
PCH_PCIE_WAKE#
PCH_RSMRST#
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
SUS_STAT#
H_PM_SYNC
SUSCLK
PCH_GPIO29
XDP_DBRESET#_R
PCH_PCIE_WAKE#
DSWODVREN
PCH_GPIO32
PCH_GPIO32
SYS_PWROK
PCH_PWROK
PCH_GPIO29
PCH_RSMRST#
PCH_GPIO72
SUSWARN#
PCH_ACIN
RI#
PM_DRAM_PWRGD
PCH_PWROK_R
SYS_PWROK
DMI_CTX_PRX_N0
<4>
DMI_CRX_PTX_N2
<4>
DMI_CTX_PRX_N1
<4>
DMI_CTX_PRX_N3
<4>
DMI_CTX_PRX_N2
<4>
DMI_CTX_PRX_P0
<4>
DMI_CTX_PRX_P1
<4>
DMI_CTX_PRX_P3
<4>
DMI_CTX_PRX_P2
<4>
DMI_CRX_PTX_N3
<4>
DMI_CRX_PTX_N1
<4>
DMI_CRX_PTX_N0
<4>
DMI_CRX_PTX_P2
<4>
DMI_CRX_PTX_P3
<4>
DMI_CRX_PTX_P1
<4>
DMI_CRX_PTX_P0
<4>
FDI_CTX_PRX_N0 <4>
FDI_CTX_PRX_N1 <4>
FDI_CTX_PRX_N2 <4>
FDI_CTX_PRX_N3 <4>
FDI_CTX_PRX_N4 <4>
FDI_CTX_PRX_N5 <4>
FDI_CTX_PRX_N6 <4>
FDI_CTX_PRX_N7 <4>
FDI_CTX_PRX_P0 <4>
FDI_CTX_PRX_P1 <4>
FDI_CTX_PRX_P2 <4>
FDI_CTX_PRX_P3 <4>
FDI_CTX_PRX_P4 <4>
FDI_CTX_PRX_P5 <4>
FDI_CTX_PRX_P6 <4>
FDI_CTX_PRX_P7 <4>
FDI_FSYNC1 <4>
FDI_LSYNC0 <4>
FDI_FSYNC0 <4>
FDI_INT <4>
FDI_LSYNC1 <4>
XDP_DBRESET#
<5>
PM_DRAM_PWRGD
<5>
PCH_RSMRST#
<40>
PBTN_OUT#
<40>
ACIN
<40,44,47,48>
PCH_PCIE_WAKE# <35,37>
H_PM_SYNC <5>
PM_SLP_S3# <40>
PM_SLP_S4# <40>
PM_SLP_S5# <40>
SUSCLK <40>
PCH_PWROK
<40>
VGATE
<40,52>
SYS_PWROK <5>
+1.05VS_VTT
+RTCVCC
+3VALW_PCH
+3VS
+3VALW_PCH
+3VS
Title
Date: Sheet of
Custom
15
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
15
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
15
2011/06/02 2012/06/02
4mil width and place
within 500mil of the PCH
Can be left NC
when IAMT is not
support on the
platfrom
DSWODVREN - On Die DSW VR Enable
H：Enable
L：Disable
*
ALL power OK
tell PCH all power ok
but cpu core
not support AMT APWROK can mux
with PWROK (check list1.0 P.40)
Ring Indicator CRB1.0 PH 10K +3VALW
not support
Deep S4,S5 can NC
PCH EDS1.2 P.74
not support Deep S4,S5 DPWROK mux with PWROK
check list1.0 P.42
SCHEMATIC,MB A7912
4019ID
60
B
D9 CH751H-40PT_SOD323-2
D9 CH751H-40PT_SOD323-2
2
1
R559 10K_0402_5%
R559 10K_0402_5%
1
2
T20 PAD @
T20 PAD @
T22 PAD @
T22 PAD @
R610 10K_0402_5%
R610 10K_0402_5%
1
2
R635 0_0402_5%
R635 0_0402_5%
1 2
R613 10K_0402_5%
R613 10K_0402_5%
1 2
R235 10K_0402_5%
@
R235 10K_0402_5%
@
1 2
R581 330K_0402_5%
@
R581 330K_0402_5%
@
1
2
T47
PAD
@
T47
PAD
@
T21 PAD @
T21 PAD @
U35
MC74VHC1G08DFT2G_SC70-5
U35
MC74VHC1G08DFT2G_SC70-5
B
2
A
1
Y 4
P
5
G
3
DMI
FDI
System
Power
Management
U33C
HM65@ DMI
FDI
System
Power
Management
U33C
HM65@
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ18
DMI3RXP
BJ20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ24
DMI_IRCOMP
BG25
FDI_RXN0 BJ14
FDI_RXN1 AY14
FDI_RXN2 BE14
FDI_RXN3 BH13
FDI_RXN4 BC12
FDI_RXN5 BJ12
FDI_RXN6 BG10
FDI_RXN7 BG9
FDI_RXP0 BG14
FDI_RXP1 BB14
FDI_RXP2 BF14
FDI_RXP3 BG13
FDI_RXP4 BE12
FDI_RXP5 BG12
FDI_RXP6 BJ10
FDI_RXP7 BH9
FDI_FSYNC0 AV12
FDI_FSYNC1 BC10
FDI_LSYNC0 AV14
FDI_LSYNC1 BB10
FDI_INT AW16
PMSYNCH AP14
SLP_SUS# G16
SLP_S3# F4
SLP_S4# H4
SLP_S5# / GPIO63 D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE# B9
SUS_STAT# / GPIO61 G8
SUSCLK / GPIO62 N14
ACPRESENT / GPIO31
H20
BATLOW# / GPIO72
E10
PWROK
L22
CLKRUN# / GPIO32 N3
SUSWARN# / SUS_PWR_DN_ACK / GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN# / GPIO29 K14
APWROK
L10
DPWROK E22
DMI2RBIAS
BH21
SLP_A# G10
DSWVRMEN A18
SUSACK#
C12
R678 0_0402_5%
R678 0_0402_5%
1 2
T23 PAD @
T23 PAD @
T16 PAD
@
T16 PAD
@
R223 49.9_0402_1%
R223 49.9_0402_1%
1 2
R578 750_0402_1%
R578 750_0402_1%
1 2
R607 10K_0402_5%
R607 10K_0402_5%
1
2
R247 10K_0402_5%
R247 10K_0402_5%
1
2
R577 330K_0402_5%
R577 330K_0402_5%
1
2
T78
PAD
@ T78
PAD
@
R597 200_0402_1%
R597 200_0402_1%
1
2
R622 10K_0402_5%
R622 10K_0402_5%
1 2
R629
10K_0402_5%
R629
10K_0402_5%
1
2
R218 200K_0402_5%
R218 200K_0402_5%
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_DPB_HPD
SDVO_SDATA
SDVO_SCLK
PCH_TXOUT1-
PCH_TXOUT2-
PCH_TXOUT0+
PCH_TXOUT2+
PCH_TXOUT0-
PCH_TXOUT1+
PCH_TXCLK-
PCH_TXCLK+
PCH_CRT_DATA
PCH_CRT_CLK
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
CRT_IREF
IGPU_BKLT_EN
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
CTRL_CLK
CTRL_DATA
LVDS_IBG
LVD_VREF
PCH_DPB_N3
PCH_DPB_P0
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P3
PCH_DPB_N1
PCH_DPB_P2
PCH_DPB_N0
PCH_CRT_CLK
PCH_CRT_DATA
CTRL_CLK
CTRL_DATA
PCH_LCD_CLK
PCH_LCD_DATA
ENBKL IGPU_BKLT_EN
IGPU_BKLT_EN
PCH_DPB_HPD
SDVO_SCLK <33>
SDVO_SDATA <33>
PCH_DPB_HPD <33>
PCH_TXCLK-
<31>
PCH_TXCLK+
<31>
PCH_TXOUT0-
<31>
PCH_TXOUT1-
<31>
PCH_TXOUT2-
<31>
PCH_TXOUT0+
<31>
PCH_TXOUT1+
<31>
PCH_TXOUT2+
<31>
PCH_CRT_DATA
<32>
PCH_CRT_R
<32>
PCH_CRT_G
<32>
PCH_CRT_B
<32>
PCH_ENVDD
<31>
DPST_PWM
<31>
PCH_LCD_DATA
<31>
PCH_CRT_CLK
<32>
PCH_DPB_N1 <33>
PCH_DPB_N3 <33>
PCH_DPB_P1 <33>
PCH_DPB_P3 <33>
PCH_DPB_N0 <33>
PCH_DPB_P0 <33>
PCH_DPB_N2 <33>
PCH_DPB_P2 <33>
ENBKL
<40>
PCH_LCD_CLK
<31>
PCH_CRT_VSYNC
<32>
PCH_CRT_HSYNC
<32>
+3VS
+3VS
Title
Date: Sheet of
Custom
16
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
16
2011/06/02 2012/06/02
Title
Date: Sheet of
Custom
16
2011/06/02 2012/06/02
Pull high at LVDS conn side.
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
SDVO_CTRLDATA strap pull high
at level shift page
RF request
R02 Modify
SCHEMATIC,MB A7912
4019ID
60
B
R177
0_0402_5%
R177
0_0402_5%
1
2
R521 2.2K_0402_5%
R521 2.2K_0402_5%
1 2
C2043
10P_0402_50V8J
@
C2043
10P_0402_50V8J
@
1
2
R532 0_0402_5%
R532 0_0402_5%
1
2
R174 2.2K_0402_5%
R174 2.2K_0402_5%
1 2
R533 150_0402_1%
R533 150_0402_1%
1 2
R534 150_0402_1%
R534 150_0402_1%
1 2
C2044
10P_0402_50V8J
@
C2044
10P_0402_50V8J
@
1
2
R157 2.2K_0402_5%
R157 2.2K_0402_5%
1 2
R156 2.2K_0402_5%
R156 2.2K_0402_5%
1 2
R522 2.2K_0402_5%
R522 2.2K_0402_5%
1 2
R189
2.37K_0402_1%
R189
2.37K_0402_1%
1
2
C2076 1U_0402_6.3V6K
C2076 1U_0402_6.3V6K
1 2
LVDS
Digital
Display
Interface
CRT
U33D
HM65@
LVDS
Digital
Display
Interface
CRT
U33D
HM65@
L_BKLTCTL
P45
L_BKLTEN
J47
L_CTRL_CLK
T45
L_CTRL_DATA
P39
L_DDC_CLK
T40
L_DDC_DATA
K47
L_VDD_EN
M45
LVDSA_CLK#
AK39
LVDSA_CLK
AK40
LVDSA_DATA#0
AN48
LVDSA_DATA#1
AM47
LVDSA_DATA#2
AK47
LVDSA_DATA#3
AJ48
LVDSA_DATA0
AN47
LVDSA_DATA1
AM49
LVDSA_DATA2
AK49
LVDSA_DATA3
AJ47
LVDSB_CLK#
AF40
LVDSB_CLK
AF39
LVDSB_DATA#0
AH45
LVDSB_DATA#1
AH47
LVDSB_DATA#2
AF49
LVDSB_DATA#3
AF45
LVDSB_DATA0
AH43
DDPB_0N AV42
DDPB_1N AV45
LVD_VREFH
AE48
LVD_VREFL
AE47
DDPD_2N BF42
DDPD_3N BJ42
DDPB_2N AU48
DDPB_3N AV47
DDPC_0N AY47
DDPC_1N AY43
DDPC_2N BA47
DDPC_3N BB47
DDPD_0N BB43
DDPD_1N BF44
DDPB_0P AV40
DDPB_1P AV46
DDPD_2P BE42
DDPD_3P BG42
DDPB_2P AU47
DDPB_3P AV49
LVDSB_DATA1
AH49
LVDSB_DATA2
AF47
LVDSB_DATA3
AF43
LVD_IBG
AF37
LVD_VBG
AF36
DDPC_1P AY45
DDPC_0P AY49
DDPC_2P BA48
DDPC_3P BB49
DDPD_0P BB45
DDPD_1P BE44
CRT_BLUE
N48
CRT_DDC_CLK
T39
CRT_DDC_DATA
M40
CRT_GREEN
P49
CRT_HSYNC
M47
CRT_IRTN
T42
CRT_RED
T49
CRT_VSYNC
M49
DAC_IREF
T43
SDVO_CTRLCLK P38
SDVO_CTRLDATA M39
DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
DDPD_CTRLCLK M43
DDPD_CTRLDATA M36
DDPB_AUXN AT49
DDPC_AUXN AP47
DDPD_AUXN AT45
DDPB_AUXP AT47
DDPC_AUXP AP49
DDPD_AUXP AT43
DDPB_HPD AT40
DDPC_HPD AT38
DDPD_HPD BH41
SDVO_TVCLKINP AP45
SDVO_TVCLKINN AP43
SDVO_STALLP AM40
SDVO_STALLN AM42
SDVO_INTP AP40
SDVO_INTN AP39
R535 150_0402_1%
R535 150_0402_1%
1 2
R178
1K_0402_0.5%
R178
1K_0402_0.5%
1
2
R158 2.2K_0402_5%
R158 2.2K_0402_5%
1 2
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