Lenovo G50-80 ACLU3 NM-A362 Rev04 schematic.pdf

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Intel Broadwell U-Processor with DDRIIIL + AMD Jet-LE/Topaz-XT GPU
ACLU3 M/B Schematics Document
2014-09-10
REV:0.4
LCFC Confidential
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Cover Page
Custom
1 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Cover Page
Custom
1 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Cover Page
Custom
1 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05

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File Name : ACLU3
LCFC confidential
DPx2 Lane
SATA Gen1
SATA ODD
RTL8106EUL (10M/100M)
RTL8111GUL (1G)
Codec
UP TO 8G x 2
DDR3L-SO-DIMM X2
Page 14,15
SD/MMC Conn.
8MB
PCI-Express
USB Board
POWER BOARD
Sub-board ( for 15")
ODD Board
USB Board
POWER BOARD
Sub-board ( for 14")
SPK Conn.
Touch Screen
AMD Jet-LE / Topaz-XT
DDR3L*8 4GB/2GB/1GB
VRAM 256/128*16
Broadwell U 15W
BGA-1168
40mm*24mm
Cardreader Realtek
RTS5170
EC
ITE IT8586E-LQFP
Touch Pad Int.KBD Thermal Sensor
NCT7718W
HDMI Conn.
4x Gen2
USB Left
USB 2.0 2x
USB Right
USB 3.0 1x
NGFF Card
WLAN&BT
USB 2.0 1x
PCIe 1x
SATA Gen3
SATA HDD
Conexant CX20752
HD Audio
Int. MIC Conn.
HP&Mic Combo Conn.
SPI ROM
SPI BUS
PCIe 1x
LAN Realtek
RJ45 Conn.
Memory BUS (DDR3L)
Dual Channel
1.35V DDR3L 1600 MT/s
USB2.0 1x
USB 3.0 Port1
Intel MCP
HDMI
S3 Package: 23mmX23mm
DP to VGA
Realtek RTD2168
VGA Conn.
USB Board
USB Board
eDP x2 Lane
eDP Conn
USB2.0 1x
USB2.0 1x
USB 2.0 1x
USB2.0 Port5
SATA Port0
Int. Camera
SATA Port1
PCIe Port3
USB2.0 Port4
USB2.0 Port0
USB2.0 Port3
USB2.0 Port6
PCIe Port4
Page 18~24
Page 25~26
Page 34
Page 35
Page 36
Page 33
Page 42
Page 42
Page 37
Page 38
Page 43
Page 43
Page 33
Page 40
Page 07
Page 45 Page 45
Page 44
Page 39
Page 3~13
Page 41
USB 2.0 Port1
USB 2.0 Port2
Haswell U 15W /
SPI ROM 4MB
Page 07
for reserve
PCIe Port5
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Block Diagram
Custom
2 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Block Diagram
Custom
2 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Block Diagram
Custom
2 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
WWW.AliSaler.Com

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+3VALW
SOURCE
IT8586E
EC_SMB_CK1
EC_SMB_DA1 X
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
+3VS
+5VS
CPU_CORE
Power Plane
O
State
+1.35VS
+1.8VGS
+1.05VS
+VGA_CORE
Thermal Sensor NCT7718W 1001_100xb
EC SM Bus1 address
Device DDR DIMMA 1010 000Xb
DDR DIMMB 1010 010Xb
PCH SM Bus address
Device Address
Address
EC SM Bus2 address
Device
Smart Battery 0X16
+0.675VS
+1.35VGS
+3VGS
VGA 0x41(default)
LAN
4
5
3
2
1
PCIE PORT LIST
USB Port1 (Left Side)
WLAN
Port Device
Camera
USB 3.0
USB 2.0
USB Port (Right Side)
0
1
2
4
5
6
7
XHCI
USB Port Table
NGFF(WLAN)
XHCI
3
BTO Item
BOM Structure
BOM Structure Table
S0
S3
S5 S4/AC Only
S5 S4
Battery only
S5 S4
AC & Battery
don't exist
B+
+3VALW
+5VALW +1.35V
O O O
O
O
O
O
O
O
X X
X X
X
X
X
X
X
SMBUS Control Table
( O --> Means ON , X --> Means OFF )
X X
V
VGA BATT SODIMM
WLAN
WiMAX
Thermal
Sensor
PCH
IT8586E
+3VS
IT8586E
PCH
X
+3VALW_PCH
X
EC_SMB_CK2
EC_SMB_DA2
V
+3VGS
V
PCH_SMB_CLK
V V
+3VALW_PCH
V
TP
Module
X
X
X
X
X
X
X X X X
USB Port2 (Left Side)
Cardreader
TOUCH PANEL
+3VALW_PCH
S3
Battery only
O X
O
O
O
X
X
X
O
O
Not stuff
@
V
V
charger
V
X
X
+3VALW_PCH +3VS +3VS
+3VS +3VS
Wlan Rsvd
Charger 0001 0010 b
PCH need to update
6
Discrete GPU
1
2
3
4
USB Port1 (Left Side)
PCH_SMB_DATA X
+3VALW
O
+1.5VS
+0.95VGS
TS@ For support touch panel sku part
CD@ Cost down part
BCD@ Cost down part for BDW project
SINGLE@ Single Rank VRAM sku
DUAL@ Dual Rank VRAM sku
S4GX8@
M4GX8@ Micron 256Mx16 VRAM x8pcs sku
H4GX8@ Hynix 256Mx16 VRAM x8pcs sku
Samsung 256Mx16 VRAM x8pcs sku
H4GX4@
S4GX4@
Hynix 256Mx16 VRAM x4pcs sku
Samsung 256Mx16 VRAM x4pcs sku
M4GX4@ Micron 256Mx16 VRAM x4pcs sku
M4@
H4@ Hynix 256Mx16 VRAM part
S4@ Samsung 256Mx16 VRAM part
Micron 256Mx16 VRAM part
AOAC@ AOAC support part
ME@ ME part(connector, hole)
14@
For 15" part
15@
PX@
GIGA@
JET@
For 14" part
UMA@
TOPAZ@
GIGA LAN Part
Discrete GPU SKU part
UMA SKU part
100M@
RANKA@
RANKB@
For AMD Topaz GPU part
For AMD Jet GPU part
100M LAN Part
For VRAM RankB part
For VRAM RankA part
H2@
M2@
S2@
Micron 128Mx16 VRAM part
Hynix 128Mx16 VRAM part
Samsung 128Mx16 VRAM part
H2GX4@ Hynix 128Mx16 VRAM x4pcs sku
M2GX4@ Micron 128Mx16 VRAM x4pcs sku
S2GX4@ Samsung 128Mx16 VRAM x4pcs sku
H2GX8@
M2GX8@
S2GX8@
Hynix 128Mx16 VRAM x8pcs sku
Micron 128Mx16 VRAM x8pcs sku
Samsung 128Mx16 VRAM x8pcs sku
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Notes List
Custom
3 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Notes List
Custom
3 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Notes List
Custom
3 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05

4. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDPx_CTRLDATA
The signal has a weak internal pull-down.
H Port is detected.
L Port is not detected.
*
DP TO VGA Converter
+VCCIOA_OUT & EDP_COMP :
Trace Width: 20mil
Space: 25mil
Max length: 100mil
HDMI CLK
HDMI D0
HDMI D1
HDMI D2
Reserve for NV GPU
VGA_HPD pull down 100K at
DP to VGA Converter side.
EDP_COMP
LCD_BKLT_CTRL_R
PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQC#
CPU_EDP_AUX
CPU_EDP_AUX#
CPU_EDP_TX0-
CPU_EDP_TX0+
CPU_EDP_TX1+
CPU_EDP_TX1-
DDPB_CLK
DDPB_DATA
HDMI_HPD
EDP_HPD
EDP_HPD
PCH_EDP_PWM
PCH_ENVDD
GPIO52
PXS_PWREN
PXS_PWREN_R
PXS_RST#_R
PXS_RST#_R
PXS_RST#
VGA_TX1+
VGA_TX0+
VGA_TX1-
VGA_TX0-
VGA_AUX
VGA_AUX#
GPIO53
PXS_PWREN_R
GPIO52
GPIO53
DDPC_CLK
DDPC_DATA
PCH_ENBKL
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
HDMI_TX2-
HDMI_TX2+
HDMI_TX1+
HDMI_TX0+
HDMI_CLK-
HDMI_CLK+
HDMI_TX1-
HDMI_TX0-
BOARD_ID3
PXS_RST#_R
PXS_PWREN_R
GPIO52
GPIO53
VGA_HPD
DDPB_CLK
DDPC_CLK
DDPB_DATA
DDPC_DATA
INVT_PWM 33
CPU_EDP_AUX# 33
CPU_EDP_AUX 33
CPU_EDP_TX0- 33
CPU_EDP_TX0+ 33
CPU_EDP_TX1+ 33
CPU_EDP_TX1- 33
DDPB_DATA 34
HDMI_HPD 34
CPU_EDP_HPD 33
PCH_ENBKL
33
PCH_ENVDD
33
PCH_EDP_PWM
33
PXS_PWREN
23,57,58
PXS_RST#
19
VGA_AUX# 35
VGA_AUX 35
VGA_HPD 35
DDPB_CLK 34
HDMI_TX2-
34
HDMI_TX2+
34
HDMI_TX1-
34
HDMI_TX1+
34
HDMI_TX0-
34
HDMI_TX0+
34
HDMI_CLK-
34
HDMI_CLK+
34
VGA_TX0-
35
VGA_TX0+
35
VGA_TX1-
35
VGA_TX1+
35
VGA_GATE#
44
BOARD_ID3
9
GPIO53
20
GPIO52
20
+VCCIOA_OUT
+3VS
+3VS
+3VS
+3VS
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (DDI,EDP)
Custom
4 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (DDI,EDP)
Custom
4 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (DDI,EDP)
Custom
4 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
RC18 10K_0402_5%
1 2
RC27 10K_0402_5%
@
1 2
RC37
100K_0402_5%
@
1
2
RC17 100K_0402_5%
@ 1
2
RC170
0_0402_5%
@
1 2
RC9
1M_0402_5%
@
1
2
RC30 10K_0402_5%
@
1 2
CC96
.1U_0402_10V6-K
@
1
2
TC1
PAD
@ 1
G
D
S
QC13
2N7002KW_SOT323-3
@
2
1
3
RPC19
2.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
G
D
S
QC4
2N7002KW_SOT323-3
@
2
1
3
RC1 24.9_0402_1%
1 2
RC8 0_0402_5%
PX@
1 2
RC7 1K_0402_5%
PX@
1 2
RC10 10K_0402_5%
1 2
RC13
100K_0402_5%
1
2
RC11 10K_0402_5%
1 2
RC2 0_0402_5%
@
1 2
RPC1
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RC14 10K_0402_5%
1 2
HSW_ULT_DDR3L
eDP SIDEBAND
PCIE
DISPLAY
9 OF 19
UC1I
BROADWELL-ULT-DDR3L_BGA1168
DDPC_AUXN
B6
DDPC_AUXP
A6
DDPB_AUXP
B5
EDP_BKLEN
A9
GPIO53
L4 GPIO51
R5 GPIO54
L3 GPIO52
L1 GPIO55
U7
PME
AD4 PIRQD/GPIO80
N2 PIRQC/GPIO79
N4
DDPB_CTRLCLK
B9
DDPB_CTRLDATA
C9
DDPC_CTRLCLK
D9
DDPC_CTRLDATA
D11
DDPB_HPD
C8
EDP_HPD
D6
DDPC_HPD
A8
DDPB_AUXN
C5
EDP_VDDEN
C6
EDP_BKLCTL
B8
PIRQA/GPIO77
U6
PIRQB/GPIO78
P4
HSW_ULT_DDR3L
EDP
DDI
1 OF 19
UC1A
BROADWELL-ULT-DDR3L_BGA1168
DDI1_TXN0
C54
DDI1_TXP0
C55
DDI1_TXN1
B58
DDI1_TXP1
C58
DDI1_TXN2
B55
DDI1_TXP2
A55
DDI1_TXN3
A57
EDP_TXP0
B46
EDP_TXN0
C45
EDP_TXN1
A47
EDP_TXP1
B47
EDP_TXN2
C47
EDP_TXP2
C46
EDP_TXN3
A49
EDP_TXP3
B49
EDP_AUXP
B45
EDP_AUXN
A45
DDI1_TXP3
B57
DDI2_TXP1
B54
DDI2_TXP0
C50 DDI2_TXN0
C51
DDI2_TXN1
C53
DDI2_TXN2
C49
DDI2_TXP2
B50
DDI2_TXN3
A53
DDI2_TXP3
B53
EDP_RCOMP
D20
EDP_DISP_UTIL
A43
RC16
0_0402_5%
@
1 2
RC15 10K_0402_5%
@
1 2
WWW.AliSaler.Com

5. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_PROCHOT#_R
PROC_DETECT#
CPU_PROCPWRGD
SM_RCOMP_1
SM_RCOMP_2
SM_RCOMP_0
SM_PG_CNTL1
CATERR#
XDP_TCLK
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PREQ#
XDP_PRDY#
XDP_BPM3#
XDP_BPM5#
XDP_BPM2#
XDP_BPM1#
XDP_BPM0#
XDP_BPM4#
XDP_BPM6#
XDP_BPM7#
DDRA_ODT0
DDRA_ODT1
DDR_ODT
DDRB_ODT0
DDRB_ODT1
H_PECI
SM_RCOMP_0
SM_RCOMP_2
SM_RCOMP_1
SM_PG_CNTL1
CPU_DRAMRST#_R
H_PECI
44
H_PROCHOT#
44,51,52
CPU_DRAMPG_CNTL 55
DDRA_ODT0 14
DDRA_ODT1 14
DDRB_ODT0 15
DDRB_ODT1 15
CPU_DRAMRST#
14,15
+3VALW
+1.35V
+1.05V_VCCST
+1.35V
+1.35V
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (MISC,THERMAL,JATG)
Custom
5 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (MISC,THERMAL,JATG)
Custom
5 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (MISC,THERMAL,JATG)
Custom
5 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
RC31 0_0402_5%
@
1 2
TC11
PAD @
1
TC4
PAD @
1
RD4 66.5_0402_1%
1 2
RC21
10K_0402_5%
1 2
E
B
C
QC14
MMBT3904WH_SOT323-3
2
3
1
RC28
100K_0402_5%
1
2
TC5
PAD @
1
TC12
PAD @
1
TC16
PAD @
1
RC26
200_0402_1% 1
2
RD3 66.5_0402_1%
1 2
DDR3L
HSW_ULT_DDR3L
MISC
THERMAL
PWR
JTAG
2 OF 19
UC1B
BROADWELL-ULT-DDR3L_BGA1168
BPM#4
K59
BPM#5
H63
BPM#6
K60
SM_RCOMP0
AU60
BPM#7
J61
BPM#3
H62
BPM#1
H60
BPM#2
H61
BPM#0
J60
PROC_TDO
F62
PROC_TDI
F63
PROC_TMS
E61
PECI
N62 CATERR
K61
PROCPWRGD
C61
PROCHOT
K63
PROC_TRST
E59
PROC_TCK
E60
PRDY
J62
PREQ
K62
SM_PG_CNTL1
AV61 SM_DRAMRST
AV15 SM_RCOMP2
AU61 SM_RCOMP1
AV60
PROC_DETECT
D61
TC6
PAD @
1
TC2 @ 1
RC3
1K_0402_5%
1 2
RC22
470_0402_5%
1
2
TC7
PAD @
1
TC14
PAD @
1
TC8
PAD @
1
RC25
121_0402_1% 1
2
RC24
100_0402_1% 1
2
TC18
PAD @
1
RD2 66.5_0402_1%
1 2
TC17
PAD @
1
RC29
10K_0402_5%
@
1
2
TC9
PAD @
1
RC20
56_0402_5% 1 2
RD1 66.5_0402_1%
1 2
TC10
PAD @
1
TC15
PAD @
1
CD1
.1U_0402_10V6-K
@
1
2
RC19
62_0402_1%
1
2
CC1
0.01U_0402_25V7K
1
2
G
D
S
QC5
PJA138K_SOT23-3
2
1
3
TC3 @ 1
RC23
0_0402_5%
@
1 2
TC13
PAD @
1

6. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
WIDTH:20MIL
SPACING: 20MIL
SMVREF
SB_ODT0
SA_ODT0
DDRA_MA15
DDRA_MA0
DDRA_MA14
DDRA_MA5
DDRA_MA4
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA9
DDRA_MA7
DDRA_MA6
DDRA_MA12
DDRA_MA13
DDRA_MA8
DDRA_MA11
DDRA_MA10
DDRB_MA15
DDRB_MA9
DDRB_MA7
DDRB_MA0
DDRB_MA13
DDRB_MA2
DDRB_MA4
DDRB_MA11
DDRB_MA3
DDRB_MA5
DDRB_MA6
DDRB_MA10
DDRB_MA8
DDRB_MA1
DDRB_MA12
DDRB_MA14
DDRA_DQ4
DDRA_DQ7
DDRA_DQ1
DDRA_DQ5
DDRA_DQ6
DDRA_DQ8
DDRA_DQ3
DDRA_DQ0
DDRA_DQ2
DDRA_DQ10
DDRA_DQ14
DDRA_DQ15
DDRA_DQ9
DDRA_DQ13
DDRA_DQ12
DDRA_DQ11
DDRA_DQ16
DDRA_DQ26
DDRA_DQ27
DDRA_DQ31
DDRA_DQ25
DDRA_DQ24
DDRA_DQ20
DDRA_DQ30
DDRA_DQ18
DDRA_DQ23
DDRA_DQ29
DDRA_DQ28
DDRA_DQ19
DDRA_DQ21
DDRA_DQ17
DDRA_DQ22
DDRA_DQ43
DDRA_DQ42
DDRA_DQ46
DDRA_DQ47
DDRA_DQ35
DDRA_DQ45
DDRA_DQ44
DDRA_DQ39
DDRA_DQ34
DDRA_DQ37
DDRA_DQ36
DDRA_DQ38
DDRA_DQ40
DDRA_DQ41
DDRA_DQ33
DDRA_DQ32
DDRA_DQ62
DDRA_DQ63
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ56
DDRA_DQ60
DDRA_DQ61
DDRA_DQ48
DDRA_DQ51
DDRA_DQ54
DDRA_DQ55
DDRA_DQ53
DDRA_DQ52
DDRA_DQ49
DDRA_DQ50
DDRB_DQ14
DDRB_DQ10
DDRB_DQ13
DDRB_DQ4
DDRB_DQ0
DDRB_DQ11
DDRB_DQ15
DDRB_DQ3
DDRB_DQ7
DDRB_DQ9
DDRB_DQ8
DDRB_DQ2
DDRB_DQ6
DDRB_DQ1
DDRB_DQ12
DDRB_DQ5
DDRB_DQ24
DDRB_DQ29
DDRB_DQ26
DDRB_DQ21
DDRB_DQ27
DDRB_DQ25
DDRB_DQ23
DDRB_DQ30
DDRB_DQ18
DDRB_DQ19
DDRB_DQ17
DDRB_DQ28
DDRB_DQ22
DDRB_DQ31
DDRB_DQ20
DDRB_DQ16
DDRB_DQ42
DDRB_DQ33
DDRB_DQ43
DDRB_DQ34
DDRB_DQ44
DDRB_DQ46
DDRB_DQ40
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ47
DDRB_DQ39
DDRB_DQ45
DDRB_DQ32
DDRB_DQ38
DDRB_DQ41
DDRB_DQ63
DDRB_DQ59
DDRB_DQ53
DDRB_DQ55
DDRB_DQ57
DDRB_DQ49
DDRB_DQ48
DDRB_DQ50
DDRB_DQ60
DDRB_DQ56
DDRB_DQ51
DDRB_DQ52
DDRB_DQ62
DDRB_DQ54
DDRB_DQ61
DDRB_DQ58
DDRA_DQS#7
DDRA_DQS#4
DDRA_DQS#1
DDRA_DQS#3
DDRA_DQS#5
DDRA_DQS#2
DDRA_DQS#0
DDRA_DQS#6
DDRA_DQS0
DDRA_DQS2
DDRA_DQS7
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS1
DDRB_DQS#4
DDRB_DQS#5
DDRB_DQS#7
DDRB_DQS#1
DDRB_DQS#2
DDRB_DQS#6
DDRB_DQS#3
DDRB_DQS4
DDRB_DQS5
DDRB_DQS0
DDRB_DQS1
DDRB_DQS7
DDRB_DQS6
DDRB_DQS2
DDRB_DQS3
DDRB_DQS#0
DDRA_DQS#[0..7]
DDRA_DQS[0..7]
DDRB_DQS#[0..7]
DDRB_DQS[0..7]
DDRB_BS1# 15
DDRB_BS0# 15
DDRB_BS2# 15
DDRB_CAS# 15
DDRB_RAS# 15
DDRB_WE# 15
DDRB_CLK0# 15
DDRB_CLK0 15
DDRB_CLK1 15
DDRB_CKE0 15
DDRB_CLK1# 15
DDRB_CKE1 15
DDRB_CS1# 15
DDRB_CS0# 15
DDR_SB_VREFDQ 15
DDR_SM_VREFCA 14
DDRA_DQ[0..15]
14
DDRA_CKE0 14
DDRA_CLK0 14
DDRA_CLK0# 14
DDRA_CLK1 14
DDRA_CLK1# 14
DDRA_CKE1 14
DDRA_CS0# 14
DDRA_CS1# 14
DDRA_RAS# 14
DDRA_WE# 14
DDRA_CAS# 14
DDRA_BS0# 14
DDRA_BS1# 14
DDRA_BS2# 14
DDRA_MA[0..15] 14
DDR_SA_VREFDQ 14
DDRA_DQ[32..47]
14
DDRB_MA[0..15] 15
DDRB_DQ[0..15]
15
DDRA_DQ[16..31]
14
DDRB_DQ[16..31]
15
DDRA_DQ[48..63]
14
DDRB_DQ[32..47]
15
DDRB_DQ[48..63]
15
DDRA_DQS#[0..7] 14
DDRA_DQS[0..7] 14
DDRB_DQS#[0..7] 15
DDRB_DQS[0..7] 15
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (DDR3L)
Custom
6 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (DDR3L)
Custom
6 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (DDR3L)
Custom
6 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
TC20
PAD @
1
HSW_ULT_DDR3L
DDR CHANNEL A
3 OF 19
UC1C
BROADWELL-ULT-DDR3L_BGA1168
SM_VREF_DQ0
AR51
SM_VREF_DQ1
AP51
SM_VREF_CA
AP49
SA_DQSP7
AL49
SA_DQSP5
AW53
SA_DQSP6
AL42
SA_DQSP2
AN58
SA_DQSP3
AN55
SA_DQSP4
AW57
SA_DQSP0
AJ62
SA_DQSP1
AN61
SA_DQSN6
AL43
SA_DQSN7
AL48
SA_DQSN4
AV57
SA_DQSN5
AV53
SA_DQSN3
AM55
SA_DQSN1
AN62
SA_DQSN2
AM58
SA_DQSN0
AJ61
SA_MA15
AU42
SA_MA13
AR35
SA_MA14
AV42
SA_MA10
AP35
SA_MA12
AU41
SA_MA11
AW41
SA_MA8
AY39
SA_MA9
AU40
SA_MA6
AV40
SA_MA7
AW39
SA_MA5
AR36
SA_MA4
AU39
SA_MA3
AP36
SA_MA2
AR38
SA_MA0
AU36
SA_MA1
AY37
SA_BA2
AY41
SA_BA1
AV35
SA_BA0
AU35
SA_WE
AW34
SA_CAS
AU34
SA_RAS
AY34
SA_ODT0
AP32
SA_CS#0
AP33
SA_CS#1
AR32
SA_CKE3
AY43
SA_CKE0
AU43
SA_CKE1
AW43
SA_CKE2
AY42
SA_DQ15
AP60
SA_DQ63
AK51 SA_DQ62
AM51 SA_DQ61
AK48 SA_DQ60
AM48 SA_DQ59
AK49 SA_DQ58
AM49 SA_DQ57
AK46 SA_DQ56
AM46 SA_DQ55
AM42 SA_DQ54
AM40 SA_DQ53
AK43 SA_DQ52
AK45 SA_DQ51
AM45 SA_DQ50
AM43 SA_DQ49
AK42 SA_DQ48
AK40 SA_DQ47
AU52 SA_DQ46
AV52 SA_DQ45
AU54 SA_DQ44
AV54 SA_DQ43
AW52 SA_DQ42
AY52 SA_DQ41
AW54 SA_DQ40
AY54 SA_DQ39
AU56 SA_DQ38
AV56 SA_DQ37
AU58 SA_DQ36
AV58 SA_DQ35
AW56 SA_DQ34
AY56 SA_DQ33
AW58 SA_DQ32
AY58 SA_DQ31
AN54 SA_DQ30
AR54 SA_DQ29
AK55
SA_DQ26
AM54
SA_DQ27
AK54
SA_DQ24
AP55 SA_DQ23
AN57 SA_DQ22
AR57 SA_DQ21
AK58 SA_DQ20
AL58 SA_DQ19
AK57 SA_DQ18
AM57 SA_DQ17
AR58 SA_DQ16
AP58
SA_DQ14
AP61 SA_DQ13
AM60 SA_DQ12
AM61 SA_DQ11
AP62 SA_DQ10
AP63 SA_DQ9
AM62 SA_DQ8
AM63 SA_DQ7
AK60 SA_DQ6
AK61 SA_DQ5
AH60
SA_DQ3
AK62 SA_DQ2
AK63 SA_DQ1
AH62 SA_DQ0
AH63
SA_CLK#0
AU37
SA_CLK0
AV37
SA_CLK#1
AW36
SA_CLK1
AY36
SA_DQ28
AL55
SA_DQ25
AR55
SA_DQ4
AH61
HSW_ULT_DDR3L
DDR CHANNEL B
4 OF 19
UC1D
BROADWELL-ULT-DDR3L_BGA1168
SB_DQ14
AV25
SB_DQSN5
AV18
SB_DQSN7
AN18
SB_DQSP4
AV22
SB_DQSP5
AW18
SB_DQSP6
AM21
SB_DQSP3
AM25
SB_DQSP7
AM18
SB_DQSP2
AM28
SB_DQSP0
AV30
SB_DQSP1
AW26
SB_DQSN6
AN21
SB_DQSN2
AN28
SB_DQSN3
AN25
SB_DQSN4
AW22
SB_DQSN1
AV26
SB_DQSN0
AW30
SB_MA14
AR46
SB_MA15
AP46
SB_MA13
AK33
SB_MA9
AU46
SB_MA10
AK36
SB_MA11
AV47
SB_MA8
AY47
SB_MA12
AU47
SB_MA4
AR45
SB_MA5
AP45
SB_MA6
AW46
SB_MA3
AR42
SB_MA7
AY46
SB_MA2
AP42
SB_MA0
AP40
SB_MA1
AR40
SB_BA2
AU49
SB_WE
AK35
SB_CAS
AM33
SB_BA0
AL35
SB_BA1
AM36
SB_RAS
AM35
SB_CS#1
AK32
SB_ODT0
AL32
SB_CS#0
AM32
SB_CKE1
AU50
SB_CKE2
AW49
SB_CKE3
AV50
SB_CKE0
AY49
SB_CK#1
AK38
SB_CK1
AL38
SB_CK0
AN38
SB_CK#0
AM38
SB_DQ61
AM20
SB_DQ63
AP18 SB_DQ62
AR18
SB_DQ57
AR20 SB_DQ56
AN20
SB_DQ58
AK18
SB_DQ59
AL18
SB_DQ60
AK20
SB_DQ51
AM22
SB_DQ52
AN22
SB_DQ53
AP21
SB_DQ54
AK21
SB_DQ55
AK22
SB_DQ46
AV17
SB_DQ47
AU17
SB_DQ48
AR21
SB_DQ49
AR22
SB_DQ50
AL21
SB_DQ45
AU19
SB_DQ41
AW19
SB_DQ42
AY17
SB_DQ43
AW17
SB_DQ44
AV19
SB_DQ40
AY19
SB_DQ36
AV23
SB_DQ37
AU23
SB_DQ38
AV21
SB_DQ39
AU21
SB_DQ35
AW21
SB_DQ31
AL25
SB_DQ32
AY23
SB_DQ33
AW23
SB_DQ30
AK25
SB_DQ34
AY21
SB_DQ26
AR25 SB_DQ25
AR26
SB_DQ27
AP25
SB_DQ28
AK26
SB_DQ29
AM26
SB_DQ20
AR29
SB_DQ21
AN29
SB_DQ22
AR28
SB_DQ23
AP28
SB_DQ24
AN26
SB_DQ15
AU25
SB_DQ16
AM29
SB_DQ17
AK29
SB_DQ18
AL28
SB_DQ19
AK28
SB_DQ10
AY25
SB_DQ11
AW25
SB_DQ13
AU27
SB_DQ5
AU31
SB_DQ7
AU29
SB_DQ8
AY27
SB_DQ9
AW27
SB_DQ0
AY31
SB_DQ1
AW31
SB_DQ2
AY29
SB_DQ3
AW29
SB_DQ4
AV31
SB_DQ12
AV27
SB_DQ6
AV29
TC19
PAD @
1
WWW.AliSaler.Com

7. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IREF&RCOMP
Width: 12-15Mil
Space:12Mil
Length: 500Mil
DIMM1, DIMM2, NGFF
INTVRMEN
H Integrated VRM enable (Default)




L Integrated VRM disable




(INTVRMEN should always be pull high.)
*
CRYSTAL
1, Space 15MIL
2, No trace under crystal
3, Place on oppsosit side of MCP for temp influence
HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.
*
For EMI
HDD
ODD
GPU, EC, Thermal Sensor
1. If support DS3, connect to +3VS and don't support EC mirror code;
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
+3V_SPI
*
ODD_DETECT#
SATA2GP
SATA3GP
PCH_JTAG_TCK
SM_INTRUDER#
SRTC_RST#
RTC_RST#
HDA_SDIN0
SATALED#
HDA_RST#
HDA_SYNC
HDA_BCLK
INTVRMEN
SATA0GP
HDA_SDOUT
RTC_X2
RTC_X1
SML0_ALERT#
SML0_CLK
SML0_DATA
SML1_ALERT#
PCH_SML1_CLK
PCH_SML1_DAT
PCH_SMB_DATA
PCH_SMB_CLK
SMB_ALERT#
RTC_X2
RTC_X1
HDA_SDIN0
HDA_SDOUT
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAGX
PCH_JTAG_TRST#
SATA_RCOMP
SPI_CS0#
SPI_CLK SPI_CLK_R
SPI_CS0#_R
SPI_SO
SPI_SI
SPI_SO_R
SPI_SI_R
SRTC_RST#
RTC_RST#
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PRX_DTX_P1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_N1
SPI_CS0#
SPI_SO
SPI_WP#
SPI_HOLD#
SPI_CLK
SPI_SI
SPI_WP#_R
SPI_HOLD#_R
PCH_SMB_DATA
PCH_SMB_CLK
PCH_SML1_DAT
PCH_SML1_CLK
SML0_DATA
SML0_CLK
SMB_ALERT#
SML1_ALERT#
SML0_ALERT#
SPI_CLK_1
SPI_CLK_1
SPI_CS1#_R
SPI_CS1#
SPI_CS1#
SPI_SI_1
SPI_SO_1
SPI_SI_1
SPI_SO_1
SPI_HOLD#_R
SPI_WP#_R SPI_WP#_1
SPI_HOLD#_1
SPI_WP#_1
SPI_HOLD#_1
SPI_WP#_R
SPI_HOLD#_R
SPI_WP#
SPI_HOLD#
SATA2GP
SATA3GP
ODD_DETECT#
SATA0GP
HDA_BITCLK_AUDIO
43
HDA_SYNC_AUDIO
43
HDA_RST_AUDIO#
43
HDA_SDIN0
43
HDA_SDOUT_AUDIO
43
LPC_AD0
44
LPC_AD1
44
LPC_AD2
44
LPC_AD3
44
LPC_FRAME#
44
ME_FLASH
44
SATA_PTX_DRX_N0 42
SATA_PRX_DTX_P0 42
SATA_PRX_DTX_N0 42
SATA_PTX_DRX_P0 42
SATA_PTX_DRX_P1 42
SATA_PTX_DRX_N1 42
SATA_PRX_DTX_P1 42
SATA_PRX_DTX_N1 42
ODD_DETECT# 42
SPI_CLK
44
SPI_CS0#
44
SPI_SI
44
SPI_SO
44
SMB_CLK_S3 14,15,35,40
SMB_DATA_S3 14,15,35,40
EC_SMB_CK2 20,39,44
EC_SMB_DA2 20,39,44
RTC_RST# 44
+1.05VS_PSATA3PLL
+3VS
+3VALW_PCH
+3V_SPI
VCCRTC
VCCRTC
+3V_SPI
+3VS
+3VALW_PCH +3VS +3VS
+3VALW_PCH +3VS
+3VALW_PCH
+3VS
+3VALW_PCH
+3V_SPI
+3V_SPI
+3V_SPI
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (RTC&AUDIO&SATA&SMBUS)
C
7 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (RTC&AUDIO&SATA&SMBUS)
C
7 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (RTC&AUDIO&SATA&SMBUS)
C
7 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
TC24 @ 1
TC22 @ 1
RC176 33_0402_5%
@
1 2
RC174 0_0402_5%
@
1 2
RC47 1K_0402_5%
@
1 2
RC45 33_0402_5%
1 2
RC180
1K_0402_5%
@
1
2
RC48 3.01K_0402_1%
1
2
CC7
10P_0402_50V8J
@
1
2
RC55 33_0402_5%
@
1 2
RC42 33_0402_5%
1 2
RC49 10K_0402_5%
@
1 2
TC28 @ 1
RC35 2.2K_0402_5%
1 2
RPC25
2.2K_0404_4P2R_5%
1
4
2
3
RC171
0_0402_5%
@
1 2
RPC24
2.2K_0404_4P2R_5%
1
4
2
3
RC50 15_0402_5%
1 2
G
D
S
QC3A
2N7002KDWH_SOT363-6
@
2
6 1
CC4
15P_0402_50V8J
1
2
UC6
W25Q32FVSSIG_SO8
@
CS
1
DO(IO1)
2
WP(IO2)
3
GND
4
VCC
8
HOLD/RST(IO3)
7
CLK
6
DI(IO0)
5
RC36 2.2K_0402_5%
1 2
RC46 0_0402_5%
@
1 2
RPC2
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
JCMOS1
SHORT PADS
@
1
2
RC173 33_0402_5%
@
1 2
TC21 @ 1
RPC20
2.2K_0404_4P2R_5%
1
4
2
3
TC33 @ 1
G
D
S
QC3B
2N7002KDWH_SOT363-6
@
5
3 4
RC61
1K_0402_5%
1
2
TC32 @ 1
RC54 33_0402_5%
@
1 2
RC175 33_0402_5%
@
1 2
RC172
0_0402_5%
@
1 2
YC1
32.768KHZ_12.5PF_202740-PG14
1 2
RC33 20K_0402_1%
1 2
RC52 15_0402_5%
1 2
RC178 33_0402_5%
@
1 2
RC177 33_0402_5%
@
1 2
RC51 0_0402_5%
@
1 2
HSW_ULT_DDR3L
JTAG
RTC
AUDIO SATA
5 OF 19
UC1E
BROADWELL-ULT-DDR3L_BGA1168
RSVD3
L11
RSVD4
K10
PCH_TMS
AD62 PCH_TDO
AE61 PCH_TDI
AD61 PCH_TCK
AE62 PCH_TRST
AU62
HDA_DOCK_RST/I2S1_SFRM
AV10 HDA_DOCK_EN/I2S1_TXD
AW10
HDA_SDI1/I2S1_RXD
AU12
HDA_SDO/I2S0_TXD
AU11
HDA_SDI0/I2S0_RXD
AY10 HDA_RST/I2S_MCLK
AU8 HDA_SYNC/I2S0_SFRM
AV11 HDA_BCLK/I2S0_SCLK
AW8
RSVD2
AC4 RSVD1
AL11
RSVD0
AV2
I2S1_SCLK
AY8
SATALED
U3
JTAGX
AE63
RTCX2
AY5
SATA_RCOMP
C12
SATA_IREF
A12
SATA3GP/GPIO37
AC1
SATA2GP/GPIO36
V6
SATA1GP/GPIO35
U1
SATA0GP/GPIO34
V1
SATA_TP3/PETP6_L0
D17
SATA_TN3/PETN6_L0
C17
SATA_RP3/PERP6_L0
E5
SATA_RN3/PERN6_L0
F5
SATA_TP2/PETP6_L1
C15
SATA_TN2/PETN6_L1
B14
SATA_RN2/PERN6_L1
J6
SATA_RP2/PERP6_L1
H6
SATA_TP1/PETP6_L2
B17
SATA_TN1/PETN6_L2
A17
SATA_RN1/PERN6_L2
J8
SATA_RP1/PERP6_L2
H8
SATA_TP0/PETP6_L3
A15
SATA_TN0/PETN6_L3
B15
SATA_RP0/PERP6_L3
H5
SATA_RN0/PERN6_L3
J5
RTCX1
AW5
RTCRST
AU7 SRTCRST
AV6 INTVRMEN
AV7 INTRUDER
AU6
TC34 @ 1
RC34 20K_0402_1%
1 2
TC23 @ 1
HSW_ULT_DDR3L
LPC
SMBUS
C-LINK
SPI
7 OF 19
UC1G
BROADWELL-ULT-DDR3L_BGA1168
CL_RST
AF4
CL_DATA
AD2
CL_CLK
AF2
SML1CLK/GPIO75
AU3
SML1DATA/GPIO74
AH3
SML1ALERT/PCHHOT/GPIO73
AU4
SML0DATA
AK1
SML0CLK
AN1
SMBDATA
AH1
SML0ALERT/GPIO60
AL2
SMBCLK
AP2
SMBALERT/GPIO11
AN2
SPI_IO3
AF1 SPI_IO2
Y6 SPI_MISO
AA4 SPI_MOSI
AA2 SPI_CS2
AC2 SPI_CS1
Y4
SPI_CLK
AA3
SPI_CS0
Y7
LFRAME
AV12 LAD3
AW11 LAD2
AY12 LAD1
AW12 LAD0
AU14
RC179
1K_0402_5%
@
1
2
RC32 10M_0402_5%
1
2
CC8
.1U_0402_10V6-K
1
2
G
D
S
QC2A
2N7002KDWH_SOT363-6
2
6 1
RC53 15_0402_5%
1 2
RC43 33_0402_5%
1 2
TC26 @ 1
RC41 330K_0402_5%
1
2
CC97
.1U_0402_10V6-K
@
1
2
CC3
1U_0402_10V6K
1
2
RC44 33_0402_5%
1 2
TC25 @ 1
G
D
S
QC2B
2N7002KDWH_SOT363-6
5
3 4
RC60
1K_0402_5%
1
2
RC39 1M_0402_5%
1
2
RPC22
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
UC3
W25Q64FVSSIG_SO8
CLK
6
GND
4
DI
5
DO
2
WP#
3
VCC
8
HOLD#
7
CS#
1
CC6
1U_0402_10V6K
1
2
CC5
18P_0402_50V8J
1
2
TC30 @ 1

8. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Width: 12-15Mil
Space:12Mil
Length: 500Mil
DIFFCLK_BIASREF
LAN
WLAN
PCIE CLK2
PCIE CLK3
PCIE CLK4 GPU
*
DSWODVREN - On Die DSW VR Enable
H Enable 



L Disable
Reserve for DS3
Reserve for DS3
Reserve for DS3
XTAL24_OUT
XTAL24_IN
XTAL24_IN
XTAL24_OUT
DIFFCLK_BIASREF
MCP_TESTLOW2
MCP_TESTLOW4
MCP_TESTLOW1
MCP_TESTLOW3
SYS_PWROK_R
PCH_GPIO72
PM_SLP_SUS#_R
SUSCLK
APWROK
PCIE_CLKREQ0#
PCIE_CLKREQ1#
SYS_RESET#
DSWODVREN
PM_CLKRUN#
SUS_STAT#
PM_SLP_S5#
SUSACK#_R
SUSWARN#_R
SUSWARN#_R
PBTN_OUT#_R PM_SLP_S4#_R
PM_SLP_S3#_R
CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#
WLAN_CLKREQ#
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CLK_PCIE_GPU#
CLK_PCIE_GPU
GPU_CLKREQ#
CLK_PCI_EC_R
PCH_RSMRST#_R
WAKE#
PLT_RST#_R
PCIE_CLKREQ5#
SYS_RESET#
AC_PRESENT_R
AC_PRESENT_R
PCH_GPIO72
WAKE#
DSWODVREN
MCP_TESTLOW3
MCP_TESTLOW2
MCP_TESTLOW4
MCP_TESTLOW1
EC_RSMRST#
PCH_DPWROK_R
PCH_PWROK_R
WLAN_CLKREQ#
LAN_CLKREQ#
PCIE_CLKREQ5#
PM_CLKRUN#
GPU_CLKREQ#
PCH_GPIO72
PCIE_CLKREQ1#
PCIE_CLKREQ0#
AC_PRESENT_R
SYS_PWROK
PLT_RST#_R
PCH_DPWROK_R
SUSCLK
PCH_PWROK
PCH_RSMRST#_R
GPU_CLKREQ#
PCH_DPWROK_R
PCH_PWROK
CLK_PCI_DP_R
SUSACK#
44
SYS_PWROK
44
PCH_PWROK
10,44
EC_RSMRST#
44
PLT_RST#
19,37,40,44
PBTN_OUT#
44
PM_SLP_SUS# 44
PM_SLP_S4# 44
PM_SLP_S3# 44
SUSWARN#
44
CLK_PCI_EC 44
DPWROK_EC 44
PCIE_WAKE# 9,37,40,44
CLK_PCIE_LAN#
37
CLK_PCIE_LAN
37
CLK_PCIE_WLAN#
40
CLK_PCIE_WLAN
40
CLK_PCIE_GPU#
19
CLK_PCIE_GPU
19
LAN_CLKREQ#
37
WLAN_CLKREQ#
40
GPU_CLKREQ#
20
SUSCLK 40
PM_SLP_S5# 44
AC_PRESENT
44
ACIN#
44,53
CLK_PCI_DP 35
+1.05VS_PLPTCLKPLL
+3VALW_PCH
+3VS
+3VALW_PCH
VCCRTC
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Clock,PM)
Custom
8 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Clock,PM)
Custom
8 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Clock,PM)
Custom
8 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
RC141 0_0402_5%
@
1 2
CC104
1000P_0402_50V7K
@ 1 2
TC40
PAD
@
1
RC139 0_0402_5%
@
1 2
RC77
330K_0402_5%
1
2
TC39
PAD
@
1
RC93 22_0402_5%
@
1
2
RC73 22_0402_5%
1
2
RC85 0_0402_5%
@
1 2
RC81 0_0402_5%
@
1 2
RC89 0_0402_5%
@
1 2
RC80
330K_0402_5%
@
1
2
RC84 0_0402_5%
@
1 2
RC71 1M_0402_5%
1
2
RPC4
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RC88 0_0402_5%
@
1 2
RC95
1K_0402_5% @
1 2
RC182 0_0402_5%
@
1 2
RC87 0_0402_5%
@
1 2
RC94
100K_0402_1% @ 1
2
RC126 0_0402_5%
@
1 2
RC79 0_0402_5%
@
1 2
G
D
S
QC8
2N7002KW_SOT323-3
@
2
1
3
RC92
100K_0402_5% 1
2
RC82 0_0402_5%
@
1 2
CC101 1000P_0402_50V7K
1 2
CC12
4.7P_0402_50V8B
1
2
RC72 3.01K_0402_1%
1
2
YC2
24MHZ_6PF_7V24000032
OSC1
1
GND1
2
OSC2
3
GND2
4
RPC5
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RC86 0_0402_5%
@
1 2
HSW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
8 OF 19
UC1H
BROADWELL-ULT-DDR3L_BGA1168
SLP_A
AL5
SLP_SUS
AP4
SLP_LAN
AJ7
SLP_S3
AT4
SLP_S5/GPIO63
AP5
SLP_S4
AJ6
SUSCLK/GPIO62
AE6
CLKRUN/GPIO32
V5
SUS_STAT/GPIO61
AG4
WAKE
AJ5
DSWVRMEN
AW7
DPWROK
AV5
SLP_WLAN/GPIO29
AM5 SLP_S0
AF3
SUSWARN/SUSPWRDNACK/GPIO30
AV4
PWRBTN
AL7
BATLOW/GPIO72
AN4 ACPRESENT/GPIO31
AJ8
RSMRST
AW6
PCH_PWROK
AY7
SUSACK
AK2
PLTRST
AG7 APWROK
AB5
SYS_PWROK
AG2 SYS_RESET
AC3
RPC3
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RPC21
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RC140 0_0402_5%
@
1 2
TC37
@
1
RC76 10K_0402_5%
1 2
RC74 10K_0402_5%
1 2
RC91 10K_0402_5%
1 2
RC75 10K_0402_5%
@
1 2
TC38
PAD
@
1
RC120 10K_0402_5%
1 2
RC90 10K_0402_5%
1 2
RC105
10K_0402_5% @ 1
2
RC83 0_0402_5%
@
1 2
CLOCK
SIGNALS
HSW_ULT_DDR3L
6 OF 19
UC1F
BROADWELL-ULT-DDR3L_BGA1168
CLKOUT_PCIE_N1
B41
CLKOUT_PCIE_P1
A41
PCIECLKRQ1/GPIO19
Y5
PCIECLKRQ0/GPIO18
U2 CLKOUT_PCIE_P0
C42
CLKOUT_ITPXDP
B35
CLKOUT_LPC_0
AN15
CLKOUT_LPC_1
AP15
PCIECLKRQ4/GPIO22
U5 CLKOUT_PCIE_P4
B39 CLKOUT_PCIE_N4
A39
PCIECLKRQ3/GPIO21
N1
CLKOUT_PCIE_N0
C43
XTAL24_OUT
B25
XTAL24_IN
A25
PCIECLKRQ5/GPIO23
T2 CLKOUT_PCIE_P5
A37 CLKOUT_PCIE_N5
B37
CLKOUT_PCIE_P3
C37 CLKOUT_PCIE_N3
B38
PCIECLKRQ2/GPIO20
AD1
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
B42
DIFFCLK_BIASREF
C26
RSVD5
K21
RSVD6
M21
TESTLOW_C35
C35
TESTLOW_C34
C34
TESTLOW_AK8
AK8
TESTLOW_AL8
AL8
CLKOUT_ITPXDP_P
A35
RC78 10K_0402_5%
1 2
CC11
3.3P_0402_50V8-C
1
2
CC103
1000P_0402_50V7K
@ 1 2
WWW.AliSaler.Com

9. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPIO66, Internal 20K PD
1: Enable Top Swap Mode
*0: Disable Top Swap Mode(default)
GPIO86, Internal PD
1: LPC
*0: SPI
OPI_RCOMP
Width 20Mil
Space 15Mil
Length 500Mil
USBRBIAS
Width 20Mil
Space 15Mil
Length 500Mil
PCIE_RCOMP&PCIE_IREF
Width 12~15Mil
Space >12Mil
Length 500Mil
WLAN
LAN PCIE3
PCIE4
PCIE5
Camera
LEFT USB (3.0)
LEFT USB (2.0)
Card reader
RIGHT USB (2.0)
Touch panel
BT
LEFT USB (3.0)
GPU
1: Enabled No Reboot Mode
*0: Disable No Reboot Mode
GPIO81, No Reboot, Internal PD
GPIO15, Internal PD
1: INTEL ME TLS W/ Confidentiality
*0: INTEL ME TLS W/O Confidentiality
Stuff Resistor
RC107,RC108,RC109,RC121
* 14" + Jet-LE + Single-Rank sku
0
1
1 15" + Topaz-XT + Single-Rank sku RC100,RC101,RC109,RC121
1
1
0
1 RC100,RC108,RC109,RC121
0 14" + Topaz-XT + Single-Rank sku
RC107,RC101,RC109,RC121
15" + Jet-LE + Single-Rank sku
0 0
1 1
0
0 1
1
0
RC107,RC108,RC102,RC121
14" + Jet-LE + Dual-Rank sku
RC107,RC101,RC102,RC121
15" + Jet-LE + Dual-Rank sku
1
1
1
1
1
0
1
1
RC100,RC108,RC102,RC121
14" + Topaz-XT + Dual-Rank sku
RC100,RC101,RC102,RC121
15" + Topaz-XT + Dual-Rank sku
1
1
1
BOARD_ID3
BOARD_ID2
0 1
Description
BOARD_ID0
0
0
BOARD_ID1
KBRST#
SERIRQ
OPI_COMP
PCIE_RCOMP
PCH_GPIO25
PCH_GPIO46
PCH_GPIO13
PCH_GPIO83
PCH_GPIO76
PCH_GPIO15
VGA_PWRGD
PCH_GPIO9
PCH_GPIO10
PCH_GPIO69
PCH_GPIO67
PCH_GPIO66
PCH_GPIO65
PCH_GPIO64
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
ODD_EN
PCH_WLAN_OFF#
PCH_GPIO89
PCH_GPIO44
PCH_GPIO49
PCH_BT_OFF#
PCH_GPIO14
PCH_GPIO4
PCH_GPIO5
PCH_GPIO70
PCH_GPIO58
PCH_GPIO6
PCH_GPIO59
PCH_GPIO90
PCH_GPIO38
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID0
BOARD_ID2
BOARD_ID1
PCH_GPIO86
PCH_GPIO26
PCH_GPIO28
DS3_WAKE#
PCH_GPIO56
PCH_GPIO57
PCH_GPIO45
PCH_GPIO47
PCH_GPIO92
PCH_GPIO50
PCH_GPIO33
PCH_GPIO91
PCH_GPIO85
USB20_P0
USB20_N0
USB20_N3
USB20_P3
USB20_P2
USB20_N2
USB20_N6
USB20_P6
USB20_N4
USB20_P4
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC0#
USB20_P1
USB20_N1
USB20_P5
USB20_N5
PCH_GPIO12
PCH_BEEP
PCH_WLAN_OFF#
PCH_BT_OFF#
PCH_GPIO66
PCH_GPIO86
PCH_GPIO7
PCH_GPIO71
PCH_GPIO94
PCH_GPIO93
PCIE_PTX_DRX_P3
PCIE_PTX_DRX_N3
PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3
PCIE_PTX_DRX_N4
PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4
PCIE_PTX_DRX_P4
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_C_GRX_N0
PCIE_CTX_GRX_P0
PCIE_CTX_C_GRX_P0
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_C_GRX_N1
PCIE_CTX_GRX_P1
PCIE_CTX_C_GRX_P1
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_C_GRX_N2
PCIE_CTX_GRX_P2
PCIE_CTX_C_GRX_P2
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_C_GRX_N3
PCIE_CTX_GRX_P3
PCIE_CTX_C_GRX_P3
USB30_RX_N1
USB30_TX_N1
USB30_TX_P1
USB30_RX_P1
CMOS_ON#
USBRBIAS
USB_OC0#
USB_OC1#
PCH_GPIO12
DS3_WAKE#
PCH_GPIO28
PCH_GPIO26
PCH_GPIO58
PCH_GPIO59
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46
PCH_BEEP
PCH_GPIO8
EC_SMI#
PCH_GPIO8
PCH_GPIO15
PCH_GPIO14
ODD_EN
PCH_GPIO49
PCH_GPIO50
PCH_GPIO85
PCH_GPIO89
PCH_GPIO91
PCH_GPIO90
PCH_GPIO92
PCH_GPIO93
PCH_GPIO4
PCH_GPIO5
PCH_GPIO67
PCH_GPIO69
VGA_PWRGD
PCH_GPIO71
SERIRQ
BOARD_ID3
PCH_GPIO38
PCH_GPIO3
PCH_GPIO2
PCH_GPIO94
PCH_GPIO0
PCH_GPIO1
PCH_GPIO9
PCH_GPIO10
USB_OC2#
USB_OC3#
PCH_GPIO64
PCH_GPIO7
PCH_GPIO6
PCH_GPIO65
PCH_GPIO70
PCH_GPIO83
CMOS_ON#
KBRST#
PCH_GPIO56
PCH_GPIO57
PCH_GPIO44
PCH_GPIO47
PCH_GPIO33
PCH_GPIO76
H_THRMTRIP#_R
H_THRMTRIP#_R
ODD_DA#
ODD_DA#
USB20_N0 45
USB20_P0 45
USB20_P3 45
USB20_N2 41
USB20_P2 41
USB20_N3 45
USB20_N4 33
USB20_P4 33
USB20_N6 40
USB20_P6 40
USB_OC1# 41
USB20_N1 41
USB20_P1 41
USB20_N5 33
USB20_P5 33
PCH_BEEP
43
KBRST# 44
SERIRQ 44
PCH_BT_OFF# 40
PCH_WLAN_OFF# 40
CMOS_ON# 33
USB_OC2# 45
PCIE_PRX_DTX_N3
37
PCIE_PTX_C_DRX_N3
37
PCIE_PRX_DTX_P3
37
PCIE_PTX_C_DRX_P3
37
PCIE_PRX_DTX_N4
40
PCIE_PRX_DTX_P4
40
PCIE_PTX_C_DRX_N4
40
PCIE_PTX_C_DRX_P4
40
PCIE_CRX_GTX_N[0..3]
19
PCIE_CRX_GTX_P[0..3]
19
PCIE_CTX_C_GRX_N[0..3]
19
PCIE_CTX_C_GRX_P[0..3]
19
USB30_TX_N1 41
USB30_RX_P1 41
USB30_RX_N1 41
USB30_TX_P1 41
ODD_DA#
42
PCIE_WAKE#
8,37,40,44
ODD_EN
42
EC_SCI# 44
EC_LID_OUT#
44
H_THRMTRIP# 20
VGA_PWRGD
19,44,58
EC_SMI#
44
BOARD_ID3
4
+1.05VS_PUSB3PLL
+3VS
+3VALW_PCH
+3VS
+3VS
+3VS
+3VS
+3VALW_PCH
+3VALW_PCH
+3VS
+3VALW_PCH
+3VALW_PCH
+1.05V_VCCST
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (GPIO,USB,PCIE)
Custom
9 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (GPIO,USB,PCIE)
Custom
9 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (GPIO,USB,PCIE)
Custom
9 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
RC96
0_0402_5%
@
1 2
CC25 .1U_0402_10V6-K
1 2
RPC10
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RC114 1K_0402_5%
@
1 2
RC104
1K_0402_5%
1
2
RC107
10K_0402_5%
JET@
1
2
RC97 10K_0402_5%
@
1 2
RC124 0_0402_5%
@
1 2
RPC16
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
CC102
.01U_0402_16V7-K
@
1
2
RPC8
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RPC13
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RC116 1K_0402_5%
@ 1
2
RC121
10K_0402_5%
PX@
1
2
CC16
.1U_0402_10V6-K PX@ 1 2
RC125 10K_0402_5%
1 2
RPC15
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RPC17
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RC109
10K_0402_5%
SINGLE@
1
2
RC123
10K_0402_5%
UMA@
1
2
CC14
.1U_0402_10V6-K PX@ 1 2
RC106 49.9_0402_1%
1
2
RC101
10K_0402_5%
15@
1
2
RC181 10K_0402_5%
UMA@
1 2
RC112 0_0402_5%
@
1 2
CC17
.1U_0402_10V6-K PX@ 1 2
RC99 10K_0402_5%
1 2
RC108
10K_0402_5%
14@
1
2
DC2
SDM10U45LP-7_DFN1006-2-2
@
2
1
CC15
.1U_0402_10V6-K PX@ 1 2
HSW_ULT_DDR3L
PCIE USB
11 OF 19
UC1K
BROADWELL-ULT-DDR3L_BGA1168
RSVD12
AM10
RSVD11
AN10
USB2P1
AT7
USB2P0
AM8
PERN3
G11
PETN5_L0
C23
USBRBIAS
AJ10
USBRBIAS
AJ11
PETN5_L1
B23
PETP5_L1
A23
USB2N7
AR13
USB2P7
AP13
USB2N6
AP11
USB2P5
AN13
USB2N5
AM13
USB2P6
AN11
USB2P4
AL15
USB2N4
AM15
USB2P3
AT10
USB2N3
AR10
USB2P2
AP8
USB2N2
AR8
USB2N1
AR7
USB2N0
AN8
PETP4
A29
PERP4
G13
PERN5_L3
E6
PERP5_L3
F6
PETN5_L2
B21
PERP5_L2
G10 PERN5_L2
H10
OC0/GPIO40
AL3
OC1/GPIO41
AT1
OC2/GPIO42
AH2
OC3/GPIO43
AV3
PETN3
C29
PERP3
F11
PERN5_L1
F8
PETN5_L3
B22
PETP5_L3
A21
PERP5_L1
E8
PETN4
B29
PETP5_L0
C22
PERP5_L0
E10 PERN5_L0
F10
PERN4
F13
PETP3
B30
PCIE_IREF
B27 PCIE_RCOMP
A27 RSVD10
E13
PETP5_L2
C21
PERP1/USB3RP3
F17 PERN1/USB3RN3
G17
RSVD9
E15
PETP1/USB3TP3
C31 PETN1/USB3TN3
C30
PERN2/USB3RN4
F15
PETP2/USB3TP4
A31 PETN2/USB3TN4
B31
PERP2/USB3RP4
G15
USB3RN1
G20
USB3RP1
H20
USB3TN1
C33
USB3TP1
B34
USB3RN2
E18
USB3RP2
F18
USB3TN2
B33
USB3TP2
A33
RPC12
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
CC23 .1U_0402_10V6-K
1 2
RC103 10K_0402_5%
1 2
CC18
.1U_0402_10V6-K PX@ 1 2
RPC14
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
TC41
@
1
RC119 3.01K_0402_1%
1
2
RC122 10K_0402_5%
1 2
RC111
0_0402_5%
@
1 2
RPC18
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
CC19
.1U_0402_10V6-K PX@ 1 2
CC24 .1U_0402_10V6-K
1 2
RC118
22.6_0402_1%
1
2
RC102
10K_0402_5%
DUAL@
1
2
RPC9
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RC115 1K_0402_5%
@ 1
2
CC20
.1U_0402_10V6-K PX@ 1 2
RC113 1K_0402_5%
@
1 2
CC21
.1U_0402_10V6-K PX@ 1 2
RC110
0_0402_5%
@
1 2
RPC11
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RC100
10K_0402_5%
TOPAZ@
1
2
CC22 .1U_0402_10V6-K
1 2
RPC6
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
HSW_ULT_DDR3L
SERIAL IO
GPIO
MISC
CPU/
10 OF 19
UC1J
BROADWELL-ULT-DDR3L_BGA1168
RSVD8
AB21
RSVD7
AF20
SERIRQ
T4
LAN_PHY_PWR_CTRL/GPIO12
AM7
GPIO58
AL4
GPIO44
AK4
BMBUSY/GPIO76
P1
GPIO8
AU2
GPIO15
AD6
GPIO17
T3 GPIO16
Y1
GPIO59
AT5
GPIO48
U4 GPIO47
AB6
GPIO49
Y3
GPIO50
P3
HSIOPC/GPIO71
Y2
GPIO13
AT3
GPIO25
AM4 GPIO14
AH4
GPIO46
AG3
GPIO10
AM2 GPIO9
AM3
DEVSLP0/GPIO33
P2
SDIO_POWER_EN/GPIO70
C4
DEVSLP1/GPIO38
L2
SPKR/GPIO81
V2 DEVSLP2/GPIO39
N5
THRMTRIP
D60
RCIN/GPIO82
V4
GSPI0_CS/GPIO83
R6
GSPI0_MISO/GPIO85
N6
GSPI0_CLK/GPIO84
L6
GSPI0_MOSI/GPIO86
L8
GSPI1_CS/GPIO87
R7
GSPI1_CLK/GPIO88
L5
GSPI_MOSI/GPIO90
K2
GSPI1_MISO/GPIO89
N7
UART0_RXD/GPIO91
J1
UART0_RTS/GPIO93
J2
UART0_TXD/GPIO92
K3
UART0_CTS/GPIO94
G1
UART1_TXD/GPIO1
G2
UART1_RXD/GPIO0
K4
I2C0_SCL/GPIO5
F3
I2C1_SDA/GPIO6
G4
I2C1_SCL/GPIO7
F1
SDIO_CMD/GPIO65
F4
SDIO_CLK/GPIO64
E3
SDIO_D0/GPIO66
D3
SDIO_D3/GPIO69
E2
SDIO_D2/GPIO68
C3
SDIO_D1/GPIO67
E4
GPIO28
AD7
GPIO57
AP1 GPIO56
AG6
GPIO45
AG5
GPIO24
AD5
GPIO27
AN5
GPIO26
AN3
UART1_RST/GPIO2
J3
I2C0_SDA/GPIO4
F2
UART1_CTS/GPIO3
J4
PCH_OPI_RCOMP
AW15
RC98 10K_0402_5%
1 2
RPC7
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RC117 1K_0402_5%
@ 1
2

10. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_SENSE
Length Match: <25Mil
Space: More Than 25Mil
GND Reference
SVID
1, Stripline Line, No More Than 6000Mil
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil
VCCST(0.1A)
1.35V_CPU(1.4A)
HW 4PCS 2.2UF CAP Mounted
HW 6PCS 10UF CAP Mounted
PWR 2PCS 470U Near VR Output
For cost down, change to X5R.
For RF
For RF
Need short
CPU_SVID_CLK_R
CPU_SVID_DAT_R
CPU_SVID_CLK_R
CPU_SVID_DAT_R
CPU_SVID_ALERT#_R
VCCST_PWRGD
PWR_DEBUG
CPU_VR_READY
CPU_SVID_ALERT#_R
CPU_VR_ON
CPU_VR_ON
VCCST_PWRGD
CPU_VR_READY
CPU_SVID_DAT
59
CPU_VR_ON
59
CPU_VCC_SENSE
59
CPU_SVID_CLK
59
CPU_SVID_ALERT#
59
PCH_PWROK
8,44 VR_CPU_PWROK
44,59
+1.35V_CPU
+1.05V_VCCST
+1.05VS
CPU_CORE
+1.05VS
+VCCIO_OUT
CPU_CORE
+1.05VS
CPU_CORE
+VCCIOA_OUT
CPU_CORE
+1.35V_CPU
+1.35V_CPU
+1.35V
+3VALW
+1.05V_VCCST
+3VALW
+1.05V_VCCST
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Power)
Custom
10 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Power)
Custom
10 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Power)
Custom
10 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
CC28
2.2U_0603_10V6-K
BCD@
1
2
CC34
10U_0603_6.3V6M
1
2
TC45
@ 1
CC27
2.2U_0603_10V6-K
1
2
TC47
@ 1
CC39
22U_0805_6.3V6M
BCD@
1
2
RC146
10K_0402_5%
1
2
RC148
0_0402_5%
@ 1
2
RC129 150_0402_1%
@ 1
2
CC36
4.7U_0603_10V6-K
@
1
2
TC56
@ 1
TC48
@ 1
RC135 0_0402_5%
@
1 2
CC31
10U_0603_6.3V6M
1
2
TC46
@ 1
TC57
@ 1
CC49
0.01U_0402_16V7K
@
1
2
RC132
130_0402_1%
1
2
CC32
10U_0603_6.3V6M
BCD@
1
2
JC1
JUMP_43X79
@
1
1
2
2
TC54
@ 1
CC141
100P_0402_50V8J
@
1
2
TC58
@ 1
+
CC41
330U_2.5V_M
@
1
2
G
D
S
QC7B
2N7002KDWH_SOT363-6
@
5
3
4
TC59
@ 1
RC128
0_0402_5%
@
1 2
RC130
10K_0402_5%
1
2
RC155 0_0402_5%
1 2
RC136
10K_0402_5%
1
2
RC147
0_0402_5%
@ 1
2
TC55
@ 1
TC60
@ 1
HSW_ULT_DDR3L
HSW ULT POWER
12 OF 19
UC1L
BROADWELL-ULT-DDR3L_BGA1168
VCCIO_OUT
A59
VCCIOA_OUT
E20
RSVD18
AD23
RSVD17
AB23
RSVD16
AC58
VCC1
F59
VDDQ10
AY44 VDDQ9
AY40 VDDQ8
AY35
RSVD24
AA59
RSVD28
U59
RSVD29
V59
RSVD27
AG58 RSVD26
AC59 RSVD25
AE60
RSVD23
AD59
VCCST1
AC22
VDDQ11
AY50
RSVD15
N58
VCC_SENSE
E63
RSVD19
AA23
RSVD20
AE59
VCCST_PWRGD
B59
VR_READY
C59 VR_EN
F60
VDDQ7
AR48 VDDQ6
AP43 VDDQ5
AN33 VDDQ4
AJ37 VDDQ3
AJ33 VDDQ2
AJ31 VDDQ1
AH26
RSVD14
J58 RSVD13
L59
VCC5
C24
VCC6
C28
VCC7
C32
VCC4
AG57
VCC68
W57
VCC67
U57
VCC64
M23
VCC65
M57
VCC66
P57
VCC63
L22
VCC62
K57
VCC59
H23
VCC60
J23
VCC57
G55
VCC58
G57
VCC54
G49
VCC55
G51
VCC56
G53
VCC52
G45
VCC53
G47
VCC51
G43
VCC49
G39
VCC50
G41
VCC48
G37
VCC47
G35
VCC46
G33
VCC44
G29
VCC45
G31
VCC43
G27
VCC42
G25
VCC41
G23
VCC39
F52
VCC40
F56
VCC38
F48
VCC37
F44
VCC36
F40
VCC33
F28
VCC34
F32
VCC35
F36
VCC32
F24
VCC31
E57
VCC28
E51
VCC29
E53
VCC30
E55
VCC26
E47
VCC27
E49
VCC23
E41
VCC24
E43
VCC25
E45
VCC21
E37
VCC22
E39
VCC18
E31
VCC19
E33
VCC20
E35
VCC16
E27
VCC17
E29
VCC13
C56
VCC14
E23
VCC15
E25
VCC11
C48
VCC12
C52
VCC8
C36
VCC9
C40
VCC10
C44
VCC61
K23
VCC3
AD57 VCC2
AB57
VCCST3
AE23 VCCST2
AE22
VIDSOUT
L63 VIDSCLK
N63 VIDALERT
L62
VSS345
P62
RSVD_TP1
P60
RSVD_TP2
P61
RSVD_TP3
N59
RSVD_TP4
N61
RSVD21
T59
RSVD22
AD60
VSS344
D63
PWR_DEBUG
H59
TC50
@ 1
CC26
2.2U_0603_10V6-K
CD@
1
2
CC42
.1U_0402_10V6-K
@
1
2
TC61
@ 1
CC2
33P_0402_50V8J
@ 1
2
TC51
@ 1
RC144
10K_0402_5%
@
1
2
RC138
0_0402_5%
@ 1
2
TC62
@ 1
CC46
0.01U_0402_16V7K
@
1
2
RC133 43_0402_5%
1
2
TC52
@ 1
G
D
S
QC7A
2N7002KDWH_SOT363-6
@
2
6
1
CC35
10U_0603_6.3V6M
1
2
TC63
@ 1
CC37
33P_0402_50V8J
@
1
2
RC145
10K_0402_5%
@
1
2
RC131
75_0402_1%
1
2
TC53
@ 1
RC137
1K_0402_5%
1
2
LC1
0_0402_5%
@
1 2
CC140
1000P_0402_50V7K
@
1
2
CC33
10U_0603_6.3V6M
1
2
G
D
S
QC6A
2N7002KDWH_SOT363-6
2
6
1
TC64
@ 1
CC38
33P_0402_50V8J
@
1
2
CC40
1U_0402_10V6K
BCD@
1
2
CC30
10U_0603_6.3V6M
CD@
1
2
RC134 0_0402_5%
@
1 2
CC29
2.2U_0603_10V6-K
1
2
RC127
100_0402_1%
1
2
G
D
S
QC6B
2N7002KDWH_SOT363-6
5
3
4
WWW.AliSaler.Com

11. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCHSIO 1.838A
VCCDSW 114mA
VCCSUS3_3[1:5] 65mA
VCCHDA 11mA
VCCSPI 18mA
VCCRTC 1mA
VCC3_3[1:4] 41mA
VCCSDIO 17mA
VCCASW[1:5] 658mA
VCCTS1_5 3mA
VCC1_05[1:9] 1.741A
+1.05VS_PLPTVCC1P05 185mA
+1.05VS_POPIPLL 57mA
+1.05VS_PLPTCLKPLL 31mA
+1.05VS_PUSB3PLL 41mA
+1.05VS_PSATA3PLL 42mA
For RF
For Intel recommend, place one 0.47uF
capacitor to address temporary inrush
current.(DOC.489999)
Need short
+DCPRTC
+PCH_DCPSUSBYP
+1.05VS_DCPSUS2
+1.05VS_DCPSUS3
+1.05VS_DCPSUS1
VCCHDA
VCCDSW3_3
VCCSPI
VCCDSW3_3 +PCH_DCPSUSBYP
+1.05VS_DCPSUS4
+1.5VS
+3VS
+1.05VS
+3VALW_PCH
+1.05VS_VCCHSIO
+1.05VS_POPIPLL
VCCSPI
+1.05VS_PLPTCLKPLL
+1.05VS
+1.05VS_PLPTVCC1P05
+1.05VS
+1.05VS
+3VS
+3VALW_PCH
+3VALW_PCH
+3VALW_PCH
+3VS
+3VL
+3VALW_PCH +1.05VS_PLPTVCC1P05
+1.05VS_POPIPLL
+1.05VS_PLPTCLKPLL
+1.05VS
+1.05VS_VCCHSIO
+1.05VS_PSATA3PLL
+1.05VS_PUSB3PLL
+3VS
VCCDSW3_3
VCCHDA
+1.05VS
+3V_SPI
+3VS
+1.05VS_PSATA3PLL
+1.05VS_PUSB3PLL
+1.05VS
VCCRTC
+1.05VS
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Power2)
Custom
11 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Power2)
Custom
11 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (Power2)
Custom
11 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
RC154
0_0402_5% @ 1
2
CC88
22U_0805_6.3V6M
1
2
CC73
1U_0402_10V6K
@
1
2
CC90 0.47U_0402_25V6K
1 2
CC93
47U_0805_4V6-M
@
1
2
CC86
22U_0805_6.3V6M
1
2
RC151
0_0402_5%
@ 1
2
CC95
22U_0805_6.3V6M
BCD@
1
2
CC91
33P_0402_50V8J
@
1
2
CC92
47U_0805_4V6-M
@
1
2
CC69
22U_0805_6.3V6M
@
1
2
CC81
22U_0805_6.3V6M
BCD@
1
2
CC87
1U_0402_10V6K
1
2
CC67
22U_0805_6.3V6M
1
2
CC98
22U_0805_6.3V6M
BCD@
1
2
LC4
2.2UH_CIG10W2R2MNC_20%
1 2
CC99
22U_0805_6.3V6M
1
2
RC149
0_0402_5%
@ 1
2
CC51
1U_0402_10V6K
1
2
CC61
1U_0402_10V6K
1
2
CC77
1U_0402_10V6K
1
2
CC100
22U_0805_6.3V6M
1
2
CC53
1U_0402_10V6K
1
2
CC59
1U_0402_10V6K
@ 1 2
TC67 @ 1
CC85
22U_0805_6.3V6M
1
2
CC54
1U_0402_10V6K
BCD@
1
2
CC94
1U_0402_10V6K
1
2
CC83
22U_0805_6.3V6M
1
2
RC153
0_0402_5%
@ 1
2
TC66 @ 1
CC74
1U_0402_10V6K
BCD@
1
2
LC2
2.2UH_CIG10W2R2MNC_20%
1 2
LC5
2.2UH_CIG10W2R2MNC_20%
1 2
CC66
1U_0402_10V6K
@
1
2
CC50
1U_0402_10V6K
1
2
LC6 0_0603_5%
@
1 2
RC150
0_0402_5%
@ 1
2
CC80
1U_0402_10V6K
1
2
JC2
JUMP_43X79
@
1
1
2
2
CC70
1U_0402_10V6K
@
1
2
CC79
22U_0805_6.3V6M
1
2
CC84
1U_0402_10V6K
1
2
RC152
0_0402_5%
@ 1
2
CC60
1U_0402_10V6K
@ 1 2
CC89
1U_0402_10V6K
1
2
CC64
1U_0402_10V6K
CD@
1
2
CC52
0.1U_0402_10V7K
1
2
CC57
1U_0402_10V6K
1
2
CC68
1U_0402_10V6K
1
2
USB2
THERMAL SENSOR
HSIO
HSW_ULT_DDR3L
USB3
OPI
RTC
GPIO/LPC
VRM
HDA
SERIAL IO
SUS OSCILLATOR
SPI
LPT LP POWER
CORE
13 OF 19
UC1M
BROADWELL-ULT-DDR3L_BGA1168
VCCHDA
AH14
VCCTS1_5
J15
DCPSUS1[2]
AD8
DCPSUS1[1]
AD10
DCPSUSBYP[2]
AG20
DCPSUSBYP[1]
AG19
DCPSUS4
AB8
VCCASW[3]
AE9
VCCASW[4]
AF9
VCCASW[5]
AG8
VCCSUS3_3[5]
AH11
VCCRTC
AG10
DCPRTC
AE7
VCCSPI
Y8
VCCASW[1]
AG14
VCCASW[2]
AG13
VCC3_3[4]
K16
VCC3_3[3]
K14
VCCSDIO[2]
T9
VCCSDIO[1]
U8
DCPSUS3
J13
VCCAPLL[2]
W21
VCCHSIO[1]
K9
VCCHSIO[2]
L10
VCCHSIO[3]
M9
VCCAPLL[1]
AA21 RSVD30
Y20
VCCSATA3PLL
B11 VCCUSB3PLL
B18
VCC1_05[1]
N8
VCC1_05[2]
P9
VCC1_05[3]
J11
VCC1_05[4]
H11
VCC1_05[5]
H15
VCC1_05[6]
AE8
VCC1_05[7]
AF22
VCCSUS3_3[4]
AE21 VCCSUS3_3[3]
AE20 RSVD33
V21 RSVD32
M20 RSVD31
K18 VCCCLK[5]
T21 VCCCLK[4]
R21 VCCCLK[3]
J17 VCCACLKPLL
A20
VCC3_3[2]
W9 VCC3_3[1]
V8 VCCDSW3_3
AH10
VCCSUS3_3[1]
AC9
RSVD34
AC20
VCCSUS3_3[2]
AA9
DCPSUS2
AH13
VCC1_05[8]
AG16
VCC1_05[9]
AG17
VCCCLK[1]
J18
VCCCLK[2]
K19
CC58
0.1U_0402_10V7K
@
1
2
CC82
22U_0805_6.3V6M
BCD@
1
2
CC76
1U_0402_10V6K
CD@
1
2
CC65
10U_0603_6.3V6M
1
2
CC56
0.1U_0402_10V7K
1
2
CC71
22U_0805_6.3V6M
1
2
CC72
0.1U_0402_10V7K
1
2
CC75
1U_0402_10V6K
1
2
CC63
1U_0402_10V6K
1
2
CC78
22U_0805_6.3V6M
1
2
CC62
1U_0402_10V6K
1
2
CC55
0.1U_0402_10V7K
1
2
LC3
2.2UH_CIG10W2R2MNC_20%
1 2

12. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Length Match: No More Than 25Mil
Space: More Than 25Mil
GND Reference
VSS_SENSE
CPU_VSS_SENSE 59
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (VSS)
Custom
12 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (VSS)
Custom
12 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (VSS)
Custom
12 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
HSW_ULT_DDR3L
14 OF 19
UC1N
BROADWELL-ULT-DDR3L_BGA1168
VSS53
AH44
VSS54
AH49
VSS55
AH51
VSS50
AH38
VSS126
AP10
VSS120
AN49
VSS114
AN40
VSS108
AN23
VSS102
AM1
VSS96
AL51
VSS5
A28
VSS1
A11
VSS2
A14
VSS3
A18
VSS4
A24
VSS6
A32
VSS7
A36
VSS8
A40
VSS9
A44
VSS10
A48
VSS11
A52
VSS12
A56
VSS13
AA1
VSS14
AA58
VSS15
AB10
VSS16
AB20
VSS17
AB22
VSS18
AB7
VSS19
AC61
VSS20
AD21
VSS21
AD3
VSS22
AD63
VSS23
AE10
VSS24
AE5
VSS25
AE58
VSS26
AF11
VSS27
AF12
VSS28
AF14
VSS30
AF17
VSS32
AG1
VSS33
AG11
VSS35
AG23
VSS36
AG60
VSS38
AG62
VSS39
AG63
VSS41
AH19
VSS44
AH24
VSS45
AH28
VSS46
AH30
VSS47
AH32
VSS51
AH40
VSS52
AH42
VSS56
AH53
VSS57
AH55
VSS58
AH57
VSS59
AJ13
VSS60
AJ14
VSS61
AJ23
VSS62
AJ25
VSS63
AJ27
VSS64
AJ29
VSS68
AJ43
VSS69
AJ45
VSS71
AJ50
VSS72
AJ52
VSS74
AJ56
VSS75
AJ58
VSS76
AJ60
VSS77
AJ63
VSS78
AK23
VSS79
AK3
VSS80
AK52
VSS81
AL10
VSS82
AL13
VSS83
AL17
VSS84
AL20
VSS85
AL22
VSS86
AL23
VSS87
AL26
VSS88
AL29
VSS89
AL31
VSS90
AL33
VSS91
AL36
VSS92
AL39
VSS93
AL40
VSS94
AL45
VSS95
AL46
VSS97
AL52
VSS98
AL54
VSS99
AL57
VSS100
AL60
VSS101
AL61
VSS103
AM17
VSS104
AM23
VSS105
AM31
VSS106
AM52
VSS107
AN17
VSS109
AN31
VSS110
AN32
VSS111
AN35
VSS112
AN36
VSS113
AN39
VSS115
AN42
VSS116
AN43
VSS117
AN45
VSS118
AN46
VSS119
AN48
VSS121
AN51
VSS122
AN52
VSS123
AN60
VSS124
AN63
VSS125
AN7
VSS127
AP17
VSS128
AP20
VSS31
AF18
VSS29
AF15
VSS73
AJ54
VSS70
AJ47
VSS65
AJ35
VSS67
AJ41
VSS66
AJ39
VSS49
AH36 VSS48
AH34
VSS43
AH22 VSS42
AH20
VSS40
AH17
VSS37
AG61
VSS34
AG21
HSW_ULT_DDR3L
16 OF 19
UC1P
BROADWELL-ULT-DDR3L_BGA1168
VSS277
D59
VSS337
Y63
VSS336
Y59
VSS335
Y10
VSS330
V10
VSS329
U9
VSS327
U22
VSS328
U61
VSS326
U20
VSS325
T58
VSS324
T1
VSS322
R22
VSS323
R8
VSS321
R10
VSS320
P63
VSS319
P59
VSS318
N3
VSS317
N10
VSS316
M22
VSS314
L61
VSS313
L58
VSS312
L20
VSS311
L18
VSS310
L17
VSS309
L15
VSS308
L13
VSS307
K12
VSS306
K1
VSS305
J63
VSS304
J59
VSS303
J22
VSS300
H17
VSS286
F38
VSS289
F50
VSS341
AH16
VSS287
F42
VSS285
F34
VSS281
E17
VSS294
G22
VSS297
G6
VSS262
D39 VSS261
D38 VSS260
D37 VSS259
D35 VSS258
D34
VSS265
D43
VSS266
D45
VSS267
D46
VSS268
D47
VSS270
D5
VSS271
D50
VSS272
D51
VSS273
D53
VSS274
D54
VSS275
D55
VSS276
D57
VSS278
D62
VSS279
D8
VSS280
E11
VSS288
F46
VSS290
F54
VSS291
F58
VSS292
F61
VSS293
G18
VSS295
G3
VSS296
G5
VSS298
G8
VSS299
H13
VSS264
D42 VSS263
D41
VSS301
H57
VSS315
L7
VSS257
D33
VSS302
J10
VSS338
V58
VSS339
AH46
VSS340
V23
VSS_SENSE
E62
VSS334
W22
VSS333
W20
VSS332
V7
VSS331
V3
VSS269
D49
VSS284
F30 VSS283
F26 VSS282
F20
HSW_ULT_DDR3L
15 OF 19
UC1O
BROADWELL-ULT-DDR3L_BGA1168
VSS179
AV16
VSS181
AV24
VSS183
AV33 VSS182
AV28
VSS180
AV20
VSS141
AR11
VSS172
AU33
VSS175
AU55
VSS252
D26
VSS253
D27
VSS251
D25
VSS250
D23
VSS192
AV55
VSS135
AP38
VSS132
AP29
VSS134
AP31
VSS136
AP39
VSS138
AP52
VSS139
AP54
VSS140
AP57
VSS142
AR15
VSS143
AR17
VSS144
AR23
VSS145
AR31
VSS146
AR33
VSS147
AR39
VSS148
AR43
VSS149
AR49
VSS150
AR5
VSS151
AR52
VSS152
AT13
VSS153
AT35
VSS154
AT37
VSS155
AT40
VSS156
AT42
VSS157
AT43
VSS158
AT46
VSS159
AT49
VSS160
AT61
VSS161
AT62
VSS162
AT63
VSS163
AU1
VSS165
AU18
VSS167
AU22
VSS171
AU30
VSS173
AU51
VSS174
AU53
VSS176
AU57
VSS177
AU59
VSS178
AV14
VSS185
AV36
VSS186
AV39
VSS187
AV41
VSS188
AV43
VSS189
AV46
VSS190
AV49
VSS191
AV51
VSS196
AW24
VSS197
AW33
VSS198
AW35
VSS199
AW37
VSS200
AW4
VSS202
AW42
VSS203
AW44
VSS204
AW47
VSS205
AW50
VSS206
AW51
VSS207
AW59
VSS209
AY11
VSS210
AY16
VSS211
AY18
VSS212
AY22
VSS213
AY24
VSS214
AY26
VSS215
AY30
VSS216
AY33
VSS217
AY4
VSS218
AY51
VSS219
AY53
VSS220
AY57
VSS221
AY59
VSS222
AY6
VSS223
B20
VSS224
B24
VSS225
B26
VSS226
B28
VSS227
B32
VSS228
B36
VSS229
B4
VSS230
B40
VSS231
B44
VSS232
B48
VSS233
B52
VSS234
B56
VSS235
B60
VSS238
C18
VSS239
C20
VSS240
C25
VSS241
C27
VSS242
C38
VSS243
C39
VSS244
C57
VSS245
D12
VSS246
D14
VSS247
D18
VSS248
D2
VSS249
D21
VSS254
D29
VSS255
D30
VSS256
D31
VSS184
AV34
VSS193
AV59
VSS194
AV8
VSS195
AW16
VSS201
AW40
VSS208
AW60
VSS236
C11
VSS237
C14
VSS170
AU28 VSS169
AU26 VSS168
AU24
VSS166
AU20
VSS164
AU16
VSS137
AP48
VSS131
AP26
VSS129
AP22
VSS130
AP23
VSS133
AP3
RC159
100_0402_1%
1
2
RC158 0_0402_5%
@
1 2
WWW.AliSaler.Com

13. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROC_OPI_RCOMP
Width 20Mil
Space 15Mil
Length 500Mil
CFG_RCOMP&TD_IREF
Width 20Mil
Space 15Mil
Length 500Mil
CFG4
CFG3
*1: Disable
0: Enable, Set DFX Enabled BIT
In Debug Interface MSR
*L: eDP enable
H: eDP disable
TP_DC_TEST_A4
DC_TEST_A3_B3
DC_TEST_A61_B61
TP_DC_TEST_A60
DC_TEST_AY2_AW2
TP_DC_TEST_AV1
TP_DC_TEST_A62
TP_DC_TEST_AW1
TP_DC_TEST_AW63
DC_TEST_AY61_AW61
DC_TEST_AY3_AW3
DC_TEST_AY62_AW62
PROC_OPI_COMP
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_AY3_AW3
DC_TEST_A3_B3
DC_TEST_AY61_AW61
DC_TEST_C1_C2
DC_TEST_AY62_AW62
DC_TEST_AY2_AW2
TP_DC_TEST_B2
TP_DC_TEST_AY60
CFG0
CFG1
CFG15
CFG4
CFG13
CFG7
CFG5
CFG9
CFG10
CFG12
CFG6
CFG2
CFG8
CFG11
CFG14
CFG3
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
TD_IREF
CFG0
CFG1
CFG8
CFG9
CFG10
CFG3
CFG4
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (OTHER)
Custom
13 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (OTHER)
Custom
13 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
MCP (OTHER)
Custom
13 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
TC74
@
1
TC106 @ 1
RC165 1K_0402_1%
@ 1
2
TC103
@
1
TC126
@
1
TC104 @ 1
TC86
@
1
TC109 @ 1
RC167 1K_0402_1%
@ 1
2
TC120 @ 1
TC112
@
1
TC135 @ 1
TC105
@
1
TC111 @ 1
TC82 @ 1
RC162
49.9_0402_1%
1
2
RC164 1K_0402_1%
@ 1
2
TC96 @ 1
TC124 @ 1
TC77
@
1
RC163 49.9_0402_1%
1
2
TC101
@
1
TC117 @ 1
TC88 @ 1
TC76
@
1
TC127 @ 1
TC114 @ 1 TC115
@
1
TC73 @ 1
TC75
@
1
TC98 @ 1
TC107
@
1
TC110
@
1
TC70 @ 1
TC108 @ 1
TC100 @ 1
HSW_ULT_DDR3L
18 OF 19
UC1R
BROADWELL-ULT-DDR3L_BGA1168
RSVD52
AY14
RSVD51
AW14
RSVD35
AT2
RSVD36
AU44
RSVD37
AV44
RSVD38
D15
RSVD39
F22
RSVD40
H22
RSVD41
J21
RSVD44
T23
RSVD42
N23
RSVD43
R23
RSVD50
AU15
RSVD49
AU10
RSVD47
AM11
RSVD46
AL1
RSVD45
U10
RSVD48
AP7
TC118
@
1
TC78 @ 1
TC71
@
1
RC168 1K_0402_1%
@ 1
2
TC84 @ 1
RC166 8.2K_0402_1%
1
2
TC119 @ 1
TC83
@
1
RC160 1K_0402_1%
@ 1
2
HSW_ULT_DDR3L
17 OF 19
UC1Q
BROADWELL-ULT-DDR3L_BGA1168
DAISY_CHAIN_NCTF_AY2
AY2
DAISY_CHAIN_NCTF_AY60
AY60
DAISY_CHAIN_NCTF_AY61
AY61
DAISY_CHAIN_NCTF_B2
B2
DAISY_CHAIN_NCTF_A3
A3
DAISY_CHAIN_NCTF_A4
A4
DAISY_CHAIN_NCTF_A61
A61
DAISY_CHAIN_NCTF_A60
A60
DAISY_CHAIN_NCTF_AW1
AW1
DAISY_CHAIN_NCTF_AV1
AV1
DAISY_CHAIN_NCTF_A62
A62
DAISY_CHAIN_NCTF_AW2
AW2
DAISY_CHAIN_NCTF_AW3
AW3
DAISY_CHAIN_NCTF_AW61
AW61
DAISY_CHAIN_NCTF_AW63
AW63
DAISY_CHAIN_NCTF_AW62
AW62
DAISY_CHAIN_NCTF_C1
C1
DAISY_CHAIN_NCTF_B62
B62
DAISY_CHAIN_NCTF_B3
B3
DAISY_CHAIN_NCTF_AY3
AY3
DAISY_CHAIN_NCTF_AY62
AY62
DAISY_CHAIN_NCTF_B61
B61
DAISY_CHAIN_NCTF_B63
B63
DAISY_CHAIN_NCTF_C2
C2
TC113 @ 1
TC102 @ 1
TC129 @ 1
TC72
@
1
RC161 1K_0402_1%
1
2
TC123 @ 1
TC99 @ 1
TC93
@
1
RC169 1K_0402_1%
@ 1
2
TC97
@
1
TC116 @ 1
TC125 @ 1
RESERVED
HSW_ULT_DDR3L
19 OF 19
UC1S
BROADWELL-ULT-DDR3L_BGA1168
CFG4
AA60
CFG5
Y62
CFG17
AA61 CFG18
U63
CFG7
Y60
CFG11
U60
RSVD_TP6
AU63
RSVD_TP7
C63
RSVD_TP8
C62
RSVD_TP11
L60
RSVD_TP10
B51
RSVD_TP9
A51
CFG10
V60 CFG9
V61 CFG8
V62
RSVD59
N60
RSVD61
Y22
RSVD60
W23
RSVD63
D58
RSVD62
AV62
RSVD_TP5
AV63
VSS343
N21
VSS342
P22
CFG19
U62
RSVD65
R20
RSVD64
P20
RSVD56
J20
CFG3
AA63 CFG2
AC63 CFG1
AC62
CFG16
AA62
CFG15
T60 CFG14
T61
CFG_RCOMP
V63
RSVD53
A5
RSVD54
E1
RSVD55
D1
TD_IREF
B12 RSVD57
H18
PROC_OPI_RCOMP
AY15
CFG12
T63
CFG13
T62
CFG0
AC60
CFG6
Y61
RSVD58
B43

14. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y0J)
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM (10uF_0603_6.3V)*8
(1U_0402_6.3V)*4
3A@1.5V
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V
For RF
DDR3 SO-DIMM A
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
Trace width:20 mils
Space:20mils
(.1U_0402_10V)*4
(10U_0603_6.3V)*2
For RF
(.1U_0402_10V6-K)*4
SMB_CLK_S3
SMB_DATA_S3
+VREF_CA
DDRA_MA15
DDRA_DQ31
DDRA_DQ12
DDRA_DQ6
DDRA_DQ39
DDRA_BS1#
DDRA_DQS0
DDRA_MA7
DDRA_MA0
DDRA_DQS7
DDRA_DQ46
DDRA_DQ28
DDRA_DQS#5
DDRA_DQ4
DDRA_DQ30
DDRA_DQ44
DDRA_RAS#
DDRA_DQS3
DDRA_CS0#
DDRA_MA6
CPU_DRAMRST#
DDRA_DQS#7
DDRA_DQ29
DDRA_DQ52
DDRA_DQS5
DDRA_DQ54
DDRA_DQ45
DDRA_DQ7
DDRA_DQ13
DDRA_DQ20
DDRA_DQ60
DDRA_ODT0
DDRA_DQ37
DDRA_MA14
DDRA_DQ55
DDRA_MA4
DDRA_DQ21
DDRA_DQ62
DDRA_DQ15
DDRA_DQ23
DDRA_DQ53
DDRA_DQ47
DDRA_ODT1
DDRA_CLK1
DDRA_CLK1#
DDRA_DQ38
DDRA_DQS#3
DDRA_MA11
DDRA_DQ61
DDRA_MA2
DDRA_DQ36
DDRA_DQ63
DDRA_DQ5
DDRA_DQ22
DDRA_DQ14
DDRA_DQS#0
DDRA_CKE1
DDRA_CLK0#
DDRA_MA8
DDRA_DQ58
DDRA_DQ35
DDRA_DQ51
DDRA_DQ40
DDRA_DQ50
DDRA_DQ16
DDRA_DQ57
DDRA_DQ56
DDRA_DQ25
DDRA_DQ24
DDRA_DQS#6
DDRA_BS2#
DDRA_DQS2
DDRA_DQ10
DDRA_DQ8
DDRA_DQ3
DDRA_CS1#
DDRA_MA13
DDRA_DQ1
DDRA_MA3
DDRA_CLK0
DDRA_MA9
DDRA_DQ27
DDRA_DQ26
DDRA_DQ32
DDRA_CKE0
DDRA_MA12
DDRA_DQ59
DDRA_DQ43
DDRA_BS0#
DDRA_MA10
DDRA_DQ19
DDRA_DQ18
DDRA_DQS6
DDRA_DQ49
DDRA_WE#
DDRA_DQ41
DDRA_DQ34
DDRA_DQS4
DDRA_DQ17
DDRA_CAS#
DDRA_DQS#2
DDRA_DQ2
DDRA_DQ42
DDRA_DQS#4
DDRA_MA5
DDRA_DQ11
DDRA_DQ0
DDRA_DQ48
DDRA_DQ9
DDRA_DQ33
DDRA_MA1
DDRA_DQS1
DDRA_DQS#1
+VREF_CA
+VREF_DQ_DIMMA
DDRA_DQ[0..63] 6
DDRA_DQS[0..7] 6
DDRA_DQS#[0..7] 6
DDRA_MA[0..15] 6
DDRA_CKE0
6
DDRA_BS2#
6
DDRA_CLK0
6
DDRA_CLK0#
6
DDRA_BS0#
6
DDRA_WE#
6
DDRA_CAS#
6
DDRA_CS1#
6
DDRA_CKE1 6
DDRA_BS1# 6
DDRA_RAS# 6
DDRA_CS0# 6
DDRA_ODT0 5
DDRA_CLK1 6
DDRA_CLK1# 6
DDRA_ODT1 5
CPU_DRAMRST# 5,15
SMB_CLK_S3 7,15,35,40
SMB_DATA_S3 7,15,35,40
+VREF_CA 15
DDR_SA_VREFDQ 6
DDR_SM_VREFCA 6
+0.675VS
+1.35V
+1.35V
+0.675VS
+3VS
+1.35V
+1.35V
+1.35V
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
DDRIII SO-DIMM A
Custom
14 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
DDRIII SO-DIMM A
Custom
14 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
DDRIII SO-DIMM A
Custom
14 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
RD8
24.9_0402_1%
BCD@
1
2
CD8
10U_0603_6.3V6M
CD@
1
2
CD18
.1U_0402_10V6-K
1
2
RD7
1.82K_0402_1%
1
2
RD12
24.9_0402_1%
BCD@
1
2
CD19
.1U_0402_10V6-K
BCD@
1
2
CD64
10U_0603_6.3V6M
1
2
CD24
.1U_0402_10V6-K
1
2
CD4
2.2U_0603_6.3V6K
CD@
1
2
CD65
10U_0603_6.3V6M
CD@
1
2
RD14
0_0402_5%
@
1
2
CD12
10U_0603_6.3V6M
1
2
CD25
.1U_0402_10V6-K
CD@
1
2
CD9
10U_0603_6.3V6M
CD@
1
2
CD11
10U_0603_6.3V6M
1
2
CD10
10U_0603_6.3V6M
1
2
CD26
.1U_0402_10V6-K
BCD@
1
2
RD6
2_0402_5%
1 2
CD70
1000P_0402_50V7K
1
2
CD5
33P_0402_50V8J
@
1
2
CD14
10U_0603_6.3V6M
BCD@
1
2
CD27
.1U_0402_10V6-K
CD@
1
2
RD13
0_0402_5%
@
1 2
CD3
0.022U_0402_16V7-K
BCD@
1
2
CD13
10U_0603_6.3V6M
1
2
CD7
33P_0402_50V8J
@
1
2
RD5
1.82K_0402_1%
1
2
CD21
0.022U_0402_16V7-K
BCD@
1
2
CD2
.1U_0402_10V6-K
1
2
CD56
1U_0402_6.3V6K
CD@
1
2
CD6
33P_0402_50V8J
@
1
2
CD16
.1U_0402_10V6-K
1
2
CD29
.1U_0402_10V6-K
1
2
CD57
1U_0402_6.3V6K
CD@
1
2
+ CD20
220U_6.3V_M
@
1
2
CD15
10U_0603_6.3V6M
BCD@
1
2
CD58
1U_0402_6.3V6K
CD@
1
2
CD23
2.2U_0603_6.3V6K
CD@
1
2
RD9
1.82K_0402_1%
1
2
CD59
1U_0402_6.3V6K
CD@
1
2
CD28
2.2U_0603_6.3V6K
BCD@
1
2
JDDR1
LCN_DAN06-K4406-0103
ME@
VREF_DQ
1
VSS_1
3
DQ0
5
DQ1
7
VSS_3
9
DM0
11
VSS_5
13
DQ2
15
DQ3
17
VSS_7
19
DQ8
21
DQ9
23
VSS_9
25
DQS1#
27
DQS1
29
VSS_11
31
DQ10
33
DQ11
35
VSS_13
37
DQ16
39
VSS_2
2
DQ4
4
DQ5
6
VSS_4
8
DQS0#
10
DQS0
12
VSS_6
14
DQ6
16
DQ7
18
VSS_8
20
DQ12
22
DQ13
24
VSS_10
26
DM1
28
RESET#
30
VSS_12
32
DQ14
34
DQ15
36
VSS_14
38
DQ20
40
DQ17
41
VSS_15
43
DQS2#
45
DQS2
47
VSS_17
49
DQ18
51
DQ19
53
VSS_19
55
DQ24
57
DQ25
59
VSS_21
61
DM3
63
VSS_23
65
DQ26
67
DQ27
69
VSS_25
71
CKE0
73
VDD_1
75
NC_1
77
BA2
79
VDD_3
81
A12/BC#
83
A9
85
VDD_5
87
A8
89
A5
91
VDD_7
93
A3
95
A1
97
VDD_9
99
CK0
101
CK0#
103
VDD_11
105
A10/AP
107
BA0
109
VDD_13
111
WE#
113
CAS#
115
VDD_15
117
A13
119
S1#
121
VDD_17
123
TEST
125
VSS_27
127
DQ32
129
DQ33
131
VSS_29
133
DQS4#
135
DQS4
137
VSS_31
139
DQ34
141
DQ35
143
VSS_33
145
DQ40
147
DQ41
149
VSS_36
151
DM5
153
VSS_37
155
DQ42
157
DQ43
159
VSS_39
161
DQ48
163
DQ49
165
VSS_41
167
DQS6#
169
DQS6
171
VSS_43
173
DQ50
175
DQ51
177
VSS_45
179
DQ56
181
DQ57
183
VSS_47
185
DM7
187
VSS_49
189
DQ58
191
DQ59
193
VSS_51
195
SA0
197
VDDSPD
199
DQ21
42
VSS_16
44
DM2
46
VSS_18
48
DQ22
50
DQ23
52
VSS_20
54
DQ28
56
DQ29
58
VSS_22
60
DQS3#
62
DQS3
64
VSS_24
66
DQ30
68
DQ31
70
VSS_26
72
CKE1
74
VDD_2
76
A15
78
A14
80
VDD_4
82
A11
84
A7
86
VDD_6
88
A6
90
A4
92
VDD_8
94
A2
96
A0
98
VDD_10
100
CK1
102
CK1#
104
VDD_12
106
BA1
108
RAS#
110
VDD_14
112
S0#
114
ODT0
116
VDD_16
118
ODT1
120
NC_2
122
VDD_18
124
VREF_CA
126
VSS_28
128
DQ36
130
DQ37
132
VSS_30
134
DM4
136
VSS_32
138
DQ38
140
DQ39
142
VSS_34
144
DQ44
146
DQ45
148
VSS_35
150
DQS5#
152
DQS5
154
VSS_38
156
DQ46
158
DQ47
160
VSS_40
162
DQ52
164
DQ53
166
VSS_42
168
DM6
170
VSS_44
172
DQ54
174
DQ55
176
VSS_46
178
DQ60
180
DQ61
182
VSS_48
184
DQS7#
186
DQS7
188
VSS_50
190
DQ62
192
DQ63
194
VSS_52
196
EVENT#
198
SDA
200
SA1
201
VTT_1
203
GND1
205
SCL
202
VTT_2
204
GND2
206
BOSS1
207
BOSS2
208
CD22
.1U_0402_10V6-K
1
2
CD68
33P_0402_50V8J
@
1
2
RD11
1.82K_0402_1%
1
2
CD17
.1U_0402_10V6-K
1
2
RD10
0_0402_5%
@
1 2
WWW.AliSaler.Com

15. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
(10uF_0603_6.3V)*8
(1U_0402_6.3V)*8
For RF
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V
DDR3 SO-DIMM B
3A@1.5V
(.1U_0402_10V)*4
(10U_0603_6.3V)*2
For RF
(.1U_0402_10V6-K)*4
Pin
Number Pin Name Net Name
5
7
15
17
4
6
16
18
10
12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS#0
DQS0
DDRB_DQ17
DDRB_DQ23
DDRB_DQ18
DDRB_DQ21
DDRB_DQ16
DDRB_DQ22
DDRB_DQ19
DDRB_DQ20
DDRB_DQS#2
DDRB_DQS2
21
23
33
35
22
24
34
36
27
29
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS#1
DQS1
DDRB_DQ3
DDRB_DQ5
DDRB_DQ6
DDRB_DQ1
DDRB_DQ2
DDRB_DQ4
DDRB_DQ0
DDRB_DQ7
DDRB_DQS#0
DDRB_DQS0
39
41
51
53
40
42
50
52
45
47
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS#2
DQS2
DDRB_DQ8
DDRB_DQ10
DDRB_DQ14
DDRB_DQ15
DDRB_DQ13
DDRB_DQ12
DDRB_DQ9
DDRB_DQ11
DDRB_DQS#1
DDRB_DQS1
57
59
67
69
56
58
68
70
62
64
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS#3
DQS3
DDRB_DQ27
DDRB_DQ26
DDRB_DQ28
DDRB_DQ24
DDRB_DQ31
DDRB_DQ30
DDRB_DQ29
DDRB_DQ25
DDRB_DQS#3
DDRB_DQS3
129
131
141
143
130
132
140
142
135
137
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS#4
DQS4
DDRB_DQ33
DDRB_DQ36
DDRB_DQ39
DDRB_DQ38
DDRB_DQ37
DDRB_DQ32
DDRB_DQ35
DDRB_DQ34
DDRB_DQS#4
DDRB_DQS4
147
149
157
159
146
148
158
160
152
154
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS#5
DQS5
DDRB_DQ40
DDRB_DQ43
DDRB_DQ42
DDRB_DQ44
DDRB_DQ45
DDRB_DQ41
DDRB_DQ46
DDRB_DQ47
DDRB_DQS#5
DDRB_DQS5
163
165
175
177
164
166
174
176
169
171
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS#6
DQS6
DDRB_DQ52
DDRB_DQ51
DDRB_DQ50
DDRB_DQ48
DDRB_DQ49
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQS#6
DDRB_DQS6
181
183
191
193
180
182
192
194
186
188
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS#7
DQS7
DDRB_DQ62
DDRB_DQ57
DDRB_DQ59
DDRB_DQ63
DDRB_DQ56
DDRB_DQ61
DDRB_DQ58
DDRB_DQ60
DDRB_DQS#7
DDRB_DQS7
Swap Table
+VREF_DQ_DIMMB
DDRB_MA7
DDRB_BS1#
DDRB_MA15
DDRB_CS0#
DDRB_RAS#
DDRB_DQS#5
DDRB_DQ46
DDRB_DQS7
DDRB_MA0
DDRB_ODT0
DDRB_DQ54
DDRB_DQS5
DDRB_DQS#7
DDRB_MA6
DDRB_ODT1
DDRB_DQ47
DDRB_DQ53
DDRB_MA4
DDRB_DQ55
DDRB_MA14
SMB_CLK_S3
DDRB_MA2
DDRB_DQ61
DDRB_MA11
DDRB_CLK1#
DDRB_CLK1
DDRB_CKE0
DDRB_DQ42
DDRB_DQS4
DDRB_MA12
DDRB_DQS6
SMB_DATA_S3
DDRB_DQ57
DDRB_WE#
DDRB_CS1#
DDRB_MA3
DDRB_BS2#
DDRB_DQS#4
DDRB_MA9
DDRB_DQ40
DDRB_DQS#6
DDRB_MA10
DDRB_MA8
DDRB_MA5
DDRB_CAS#
DDRB_BS0#
DDRB_MA1
DDRB_DQ50
DDRB_MA13
DDRB_CLK0#
DDRB_CLK0
CPU_DRAMRST#
DDRB_DQS3
DDRB_CKE1
DDRB_DQS#3
+VREF_CB
DDRB_DQ56
DDRB_DQ62
DDRB_DQ60
DDRB_DQ59 DDRB_DQ58
DDRB_DQ63
DDRB_DQ52
DDRB_DQ51
DDRB_DQ49
DDRB_DQ48
DDRB_DQ44
DDRB_DQ45
DDRB_DQ43
DDRB_DQ41
DDRB_DQ35
DDRB_DQ34
DDRB_DQ39
DDRB_DQ38
DDRB_DQ33
DDRB_DQ32
DDRB_DQ36
DDRB_DQ37
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ24
DDRB_DQ31
DDRB_DQ28 DDRB_DQ29
DDRB_DQ30
DDRB_DQS#0
DDRB_DQS0
DDRB_DQS#1
DDRB_DQS1
DDRB_DQS2
DDRB_DQS#2
DDRB_DQ5
DDRB_DQ7
DDRB_DQ6
DDRB_DQ4
DDRB_DQ3 DDRB_DQ2
DDRB_DQ0
DDRB_DQ1
DDRB_DQ15
DDRB_DQ14
DDRB_DQ10 DDRB_DQ12
DDRB_DQ13
DDRB_DQ11
DDRB_DQ9
DDRB_DQ8
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ18
DDRB_DQ17
DDRB_DQ23
DDRB_DQ16
DDRB_DQ22
DDRB_DQ[0..63] 6
DDRB_DQS[0..7] 6
DDRB_DQS#[0..7] 6
DDRB_MA[0..15] 6
CPU_DRAMRST# 5,14
DDRB_CKE1 6
DDRB_CLK1 6
DDRB_BS1# 6
DDRB_CLK1# 6
DDRB_CS0# 6
DDRB_RAS# 6
DDRB_ODT0 5
SMB_DATA_S3 7,14,35,40
DDRB_ODT1 5
SMB_CLK_S3 7,14,35,40
DDRB_CKE0
6
DDRB_BS2#
6
DDRB_CLK0#
6
DDRB_CLK0
6
DDRB_BS0#
6
DDRB_CAS#
6
DDRB_WE#
6
DDRB_CS1#
6
+VREF_CA 14
DDR_SB_VREFDQ 6
+0.675VS
+1.35V
+0.675VS
+1.35V
+1.35V +1.35V
+3VS
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
DDRIII SO-DIMM B
Custom
15 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
DDRIII SO-DIMM B
Custom
15 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
DDRIII SO-DIMM B
Custom
15 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
CD33
33P_0402_50V8J
@
1
2
CD48
.1U_0402_10V6-K
1
2
RD20
0_0402_5%
@
1 2
CD55
.1U_0402_10V6-K
1
2
CD35
33P_0402_50V8J
@
1
2
CD69
33P_0402_50V8J
@
1
2
RD17
1.82K_0402_1%
1
2
CD44
.1U_0402_10V6-K
1
2
RD21 10K_0402_5%
1 2
RD18
24.9_0402_1%
BCD@
1
2
CD37
10U_0603_6.3V6M
CD@
1
2
CD71
1000P_0402_50V7K
1
2
CD45
.1U_0402_10V6-K
1
2
CD66
10U_0603_6.3V6M
1
2
CD32
0.022U_0402_16V7-K
BCD@
1
2
CD31
.1U_0402_10V6-K
1
2
CD38
10U_0603_6.3V6M
1
2
CD46
.1U_0402_10V6-K
BCD@
1
2
RD19
0_0402_5%
@
1 2
CD50
.1U_0402_10V6-K
CD@
1
2
CD47
.1U_0402_10V6-K
1
2
CD67
10U_0603_6.3V6M
CD@
1
2
CD60
1U_0402_6.3V6K
CD@
1
2
CD43
10U_0603_6.3V6M
BCD@
1
2
CD40
10U_0603_6.3V6M
1
2
CD51
.1U_0402_10V6-K
1
2
CD61
1U_0402_6.3V6K
CD@
1
2
CD52
.1U_0402_10V6-K
CD@
1
2
CD36
10U_0603_6.3V6M
CD@
1
2
CD34
33P_0402_50V8J
@
1
2
CD42
10U_0603_6.3V6M
BCD@
1
2
RD16
2_0402_5%
1 2
CD53
.1U_0402_10V6-K
1
2
CD62
1U_0402_6.3V6K
CD@
1
2
RD15
1.82K_0402_1%
1
2
CD49
2.2U_0603_6.3V6K
CD@
1
2
CD54
2.2U_0603_6.3V6K
BCD@
1
2
CD30
2.2U_0603_6.3V6K
CD@
1
2
JDDR2
LCN_DAN06-K4406-0102
ME@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
CD63
1U_0402_6.3V6K
CD@
1
2
CD39
10U_0603_6.3V6M
1
2
CD41
10U_0603_6.3V6M
1
2

16. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Blank
Custom
16 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Blank
Custom
16 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Blank
Custom
16 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
WWW.AliSaler.Com

17. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Blank
Custom
17 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Blank
Custom
17 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
Blank
Custom
17 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05

18. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VDD_CT(+1.8VGS)
VDDR3(+3VGS)
Power-Up/Down Sequence
VDDR1(+1.35VGS)
PCIE_VDDC(+0.95VGS)
"Topaz" has the following requirements with regards to power-supply sequencing to
avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 µs
before VDDC, VDDCI, and VMEMIO start to ramp up.
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/µs).
For power down, reversing the ramp-up sequence is recommended.
VDDC/VDDCI(+VGA_CORE)
100us min.
PERSTb(GPU_RST#)
REFCLK(CLK_PCIE_VGA)
10us min.
0 ~ 20ms
100ms min.
0 ~ 20ms
ROM_CONFIG[0]
ROM_CONFIG[1]
ROM_CONFIG[2]
The LSB (least significant bit) of the strap option that
indicates the number of audio-capable display outputs.
Define the ROM type when STRAP_BIOS_ROM_EN = 1,
Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
0 = The transmitter half-swing is enabled
1 = The transmitter full-swing is enabled
0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.
111= No usable endpoints.
PS_1[1]
X
PS_1[2]
0= Disable
STRAP_BIF_GEN3_EN_A
STRAP_BIF_CLK_PM_EN
1 = PCIe GEN3 is supported.
0 = PCIe GEN3 is not supported.
0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled
1= Enable
PS_1[3]
PS_1[4]
0= Not support
X
PS_1[5]
PS_2[1]
PS_2[2]
PS_2[3]
100 = 256MB
PS_2[4]
PS_3[1]
PS_3[2]
PS_3[3]
BOARD_CONFIG[0]
BOARD_CONFIG[1]
BOARD_CONFIG[2]
Board configuration related strapping, such as for memory ID
X
PS_0[4] N/A
PS_2[5]
PS_3[4]
PS_3[5]
Reserved for internal use only. Must be 1 at reset.
N/A Reserved 1
AUD_PORT_CONN_
PINSTRAP[1]
AUD_PORT_CONN_
PINSTRAP[2]
0
11
1
Determines the maximum number of digital display audio endpoints
that will be presented to the OS and user.(Combine with PS_0[5])
N/A
111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.
STRAP_TX_CFG_DRV_
FULL_SWING
STRAP_TX_DEEMPH_EN
N/A
PS_0[5]
N/A
AUD_PORT_CONN_
PINSTRAP[0]
STRAP_BIOS_ROM_EN
STRAP_BIF_VGA_DIS
X
RECOMMENDED
SETTINGS
CONFIGURATION STRAPS RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system’s VGA controller.
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET
Reserved.
0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.
MLPS Bit Description
Strap Name
Reserved.
000 = Hynix 256M*16
100 = Samsung 256M*16
010 = Micron 256M*16
X
1
1
1
0
0
0
Reserved for internal use only. Must be 0 at reset.
001 = Hynix 128M*16
011 = Samsung 128M*16
111 = Micron 128M*16
PS_0[1]
PS_0[2]
PS_0[3]
VRAM ID config
H5TC2G63FFR-11C
Hynix
100
128Mx16
Memory Type
MT41J128M16JT-093G
K4W2G1646Q-BC1A
H5TC4G63AFR-11C
MT41J256M16HA-093G
K4W4G1646D-BC1A
256Mx16
PS_3[3:1]
VRAM ID PU resistor PD resistor
RV33 RV36
Micron
Samsung
Hynix
Micron
Samsung
111
110
000
010
001
4.53K 4.99K
NC
4.75K
10K
3.4K
NC 4.75K
4.53K 2K
8.45K 2K
MT41K256M16HA-107G
Micron
011 6.98K 4.99K
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
VGA Notes List
Custom
18 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
VGA Notes List
Custom
18 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
VGA Notes List
Custom
18 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
WWW.AliSaler.Com

19. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P[3..0]
PCIE_CRX_GTX_N[3..0]
PCIE_CTX_C_GRX_P[3..0]
PCIE_CTX_C_GRX_N[3..0]
CLK_PCIE_GPU
CLK_PCIE_GPU#
PCIE_CRX_C_GTX_P0 PCIE_CRX_GTX_P0
PCIE_CRX_C_GTX_N0 PCIE_CRX_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
GPU_RST#
GPU_RST#
VGA_PWRGD
GPU_RST#
GPU_PWROK
PCIE_CRX_GTX_P[3..0] 9
PCIE_CRX_GTX_N[3..0] 9
PCIE_CTX_C_GRX_P[3..0]
9
PCIE_CTX_C_GRX_N[3..0]
9
CLK_PCIE_GPU
8
CLK_PCIE_GPU#
8
PLT_RST#
8,37,40,44
PXS_RST#
4
GPU_RST#
20
VGA_PWRGD
9,44,58
GPU_PWROK 58
+0.95VGS
+3VGS
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
ATI_JET-LE_PCIE
A3
19 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
ATI_JET-LE_PCIE
A3
19 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
Size Document Number Rev
Date: Sheet of
Security Classification LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date Deciphered Date
Title
ACLU3 0.4
ATI_JET-LE_PCIE
A3
19 59
Wednesday, September 17, 2014
2013/08/08 2013/08/05
CV6
.1U_0402_10V6-K PX@
1 2
CV5
.1U_0402_10V6-K PX@
1 2
RV7 0_0402_5%
@
1 2
CV8
.1U_0402_10V6-K PX@
1 2
CV7
.1U_0402_10V6-K PX@
1 2
RV3 1.69K_0402_1%
PX@
1 2
RV27 0_0402_5%
@
1 2
DV3
BAT54AWT1G_SOT323-3
PX@
1
3
2
PCI
EXPRESS
INTERFACE
CLOCK
CALIBRATION
UV1A
JET-S3-LE_FCBGA631
@
TEST_PG
N10
PCIE_CALR_RX
AA22
PCIE_CALR_TX
Y22
PCIE_REFCLKN
AK32 PCIE_REFCLKP
AK30
PCIE_RX0N
AE31 PCIE_RX0P
AF30
NC#R31
R31 NC#T30
T30
NC#P28
P28 NC#R29
R29
NC#N31
N31 NC#P30
P30
NC#M28
M28 NC#N29
N29
NC#L31
L31 NC#M30
M30
NC#K30
K30 NC#L29
L29
PCIE_RX1N
AD28 PCIE_RX1P
AE29
PCIE_RX2N
AC31 PCIE_RX2P
AD30
PCIE_RX3N
AB28 PCIE_RX3P
AC29
PCIE_RX4N
AA31 PCIE_RX4P
AB30
PCIE_RX5N
Y28 PCIE_RX5P
AA29
PCIE_RX6N
W31 PCIE_RX6P
Y30
PCIE_RX7N
V28 PCIE_RX7P
W29
NC#U31
U31 NC#V30
V30
NC#T28
T28 NC#U29
U29
PERSTB
AL27
PCIE_TX0N
AG31
PCIE_TX0P
AH30
NC#U23
U23
NC#U24
U24
NC#T27
T27
NC#T26
T26
NC#T23
T23
NC#T24
T24
NC#P26
P26
NC#P27
P27
NC#P23
P23
NC#P24
P24
NC#N26
N26
NC#M27
M27
PCIE_TX1N
AF28
PCIE_TX1P
AG29
PCIE_TX2N
AF26
PCIE_TX2P
AF27
PCIE_TX3N
AD26
PCIE_TX3P
AD27
PCIE_TX4N
AB25
PCIE_TX4P
AC25
PCIE_TX5N
Y24
PCIE_TX5P
Y23
PCIE_TX6N
AB26
PCIE_TX6P
AB27
PCIE_TX7N
Y26
PCIE_TX7P
Y27
NC#W23
W23
NC#W24
W24
NC#U26
U26
NC#V27
V27
CV1
.1U_0402_10V6-K PX@
1 2
RV6
100K_0402_5%
PX@
1
2
CV2
.1U_0402_10V6-K PX@
1 2
RV5 1K_0402_1%
PX@
1 2
CV4
.1U_0402_10V6-K PX@
1 2
UV2
MC74VHC1G08DFT2G_SC70-5
PX@
IN1
1
IN2
2 OUT
4
VCC
5
GND
3
CV3
.1U_0402_10V6-K PX@
1 2
RV4
1K_0402_1% PX@
1 2