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NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf

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A A B B C C D D E E 1 1 2 2 3 3 4 4 Intel Kabylake H-Processor with DDR4 + NV N17P-G0/G1 GPU DY512 M/B Schematics Document 2016-11-25 REV:1.0 LCFC Confidential MB NM-B191 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Cover Page Custom 1 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Cover Page Custom 1 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Cover Page Custom 1 75 Friday, November 25, 2016 2015/02/26 2016/02/26
A A B B C C D D E E 1 1 2 2 3 3 4 4 PCIE 4x Gen3 SSD BH611FJ1LN Codec 8MB IO Board (RJ45/USB2.0/Aduio combo jack) Sub-board SPK Conn. NV N17P-G0 40W GDDR5*4 4GB/2GB VRAM 256/128*32 EC ITE IT8226-LQFP Touch Pad Int.KBD Thermal Sensor Fintek F75303M HDMI Conn. USB Right USB 2.0 2x 480Mbps USB Left USB 3.0 2x 5Gbps NGFF Card WLAN&BT SATA Gen3 6Gbps SATA HDD Realtek ALC3248 HD Audio(24MHz) HP&Mic Combo Conn. SPI ROM SPI BUS(17/33/48MHz) PCIe 1x Gne1 250MGB/s CardReader SD/MMC Memory BUS (DDR4 non-ECC) Dual Channel 1.2V DDR4 2400 MT/s 19.2GB/s *2 Total 38.4GB/s USB 3.0 Port1 TMDS 2.97Gbps IO Board IO Board eDP x2 Lane eDP Conn SATA Port2 PCIe Port2 USB2.0 Port1 USB2.0 Port11 PCIe Port3 Page 24~29 Page 30~33 Page 35 Page 42 Page 41 Page 39 Page 39 Page 43 Page 44 Page 41 Page 18 Page 46 Page 46 Page 45 Page 40 Page 14~22 Page 43 USB 3.0 Port2 USB 2.0 Port2 USB 2.0 Port3 SPI ROM 4MB Page 18 PCI-Express 8x Gen3 BGA-1440 42mm*28mm Intel CPU Kaby Lake-H 45W Intel PCH Kaby Lake-H FCBGA 23mm*23mm DMI *4 1GB/s * 4 Total 4GB/s PCIe Port4 LPC(24MHz) TPM Z32H320TC Page 46 FHD : 15"1920*1080 HDMI level shift PS8203 Optane memory One M.2 CONN RTL8111GUL(1000M) LAN Realtek RJ45 Conn. Dual DMIC USB2.0 1x 480Mbps Int. Camera DMIC Page 5~11 Page 35 Page 34 Page 34 RTS5400 Page 36~37 USB 3.0 1x 5Gbps USB2.0 1x 480Mbps DP x4Lane Typec CONN Page 37 PCIe Port9~12 Type C controller UP TO 8G x 2 DDR4-SO-DIMM X2 Page 12,13 TP BUTTON Board (Only for Provence‐5R) 1GB/s * 8 Total 8GB/s 1GB/s * 4 Total 4GB/s USB 2.0 1x 480Mbps PCIe 1x Gne1 250MGB/s USB 2.0 1x 480Mbps PCIe 1x Gne1 250MGB/s 2.7Gb/s * 2 Total 5.4Gb/s 5.4Gb/s * 4 Total 21.6Gb/s DP Redriver PS8330B NV N17P-G1 50W CPU FAN GPU FAN Page 40 Battery Page 58 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Block Diagram C 2 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Block Diagram C 2 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Block Diagram C 2 75 Friday, November 25, 2016 2015/02/26 2016/02/26 WWW.AliSaler.Com
A A B B C C D D E E 1 1 2 2 3 3 4 4 STATE SIGNAL Full ON S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF) SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock Voltage Rails ON ON ON ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH +3VS +5VS CPU_CORE Power Plane O State +1.8V_AON VCCIO NVVDD +0.6VS +1.35VGS NVVDDS BTO Item BOM Structure BOM Structure Table S0 S3 S5 S4/AC Only S5 S4 Battery only S5 S4 AC & Battery don't exist B+ +3VALW +5VALW +1.2V O O O O O O O O O X X X X X X X X X ( O --> Means ON , X --> Means OFF ) +3VALW_PCH S3 Battery only O X O O O X X X O O Not stuff @ O +0.95VGS ME@ OPT@ ME part(connector, hole) For GPU part CD@ Cost down part TPM@ For support TPM sku part +2.5V +1.0VALW +1.8V_MAIN GFX VCCSTG VCCST VCCSA EMC@ EMC_NS@ EMC part stuff EMC part Not stuff RF@ RF_NS@ RF part stuff RF part Not stuff N16@ N17@ For N16 GPU part For N17 GPU part USB2.0 Port table Port Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Right USB2 Left USB3 Left USB3 TypeC USB2 Camera BT HSIO port Table Port Description 8 1 2 3 4 11 12 5 6 7 14 9 10 13 Left USB3 15 16 17 18 19 20 21 22 23 24 25 26 Left USB3 TypeC USB3 Function USB3#1 USB3#2 USB3#3 USB3#4 USB3#5 USB3#6 USB3#7 / PCIE#1 USB3#8 / PCIE#2 USB3#9 / PCIE#3 USB3#10 / PCIE#4 PCIE#5 PCIE#6 PCIE#7 PCIE#8 PCIE#9 / SATA#0 PCIE#10 / SATA#1 PCIE#11 PCIE#12 PCIE#13 / SATA#0 PCIE#14 / SATA#1 PCIE#15 / SATA#2 PCIE#16 / SATA#3 PCIE#17 / SATA#4 PCIE#18 / SATA#5 PCIE#19 / SATA#6 PCIE#20 / SATA#6 CarderReader(PCIE) WLAN(PCIE) LAN(PCIE) PCIe x4 SSD HDD(SATA3.0) HDD cable(SATA3.0) Reserved Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Notes List Custom 3 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Notes List Custom 3 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Notes List Custom 3 75 Friday, November 25, 2016 2015/02/26 2016/02/26
5 5 4 4 3 3 2 2 1 1 D D C C B B A A EC IT8226 Battery JBATT2 EC_SMB_CK1 EC_SMB_DA1 Change IC PU102 BQ24780SRUYR +3VALW_R 2.2K 2.2K +3VS Dual MOS EC_SMB_CK2 EC_SMB_DA2 Thermal sensor U1 F75303M Dual MOS +3VS_AON Control +3VS Control PCH( UH1 ) +3VALW_PCH 2.2K NV GPU( UV1 ) +3VS_AON 2.2K VGA_SMB_CK2 VGA_SMB_DA2 SML1CLK SML1DATA VGA V X X SODIMM BATT IT8586E PCH Thermal Sensor WLAN WiMAX PCH IT8226 +3VS V +3VALW_PCH X +3VGS V EC_SMB_DA2 EC_SMB_CK2 V PCH_SMB_CLK SMBUS Control Table +3VALW_PCH V V X TP Module V X X X X X X X X X X +3VS +3VS +3VALW_PCH X +3VS +3VS PCH 0001 0010 b Charger Rsvd WLAN need to update 0x41(default) VGA 0xD4 RTS5400 X PCH_SMB_DATA +3VALW V V charger V X EC_SMB_DA1 EC_SMB_CK1 IT8226 SOURCE +3VALW PCH SM Bus address 1010 010Xb DDR DIMMB 1010 000Xb DDR DIMMA Device EC SM Bus1 address 1001_100xb Thermal Sensor F75303M 0X16 Smart Battery Device EC SM Bus2 address Address Address Device +3VALW_PCH 2.2K PCH_SMBCLK PCH_SMBDATA +3VS DDR1 2.2K VGA_SMB_CK2 VGA_SMB_DA2 PCH +3VS Control Dual MOS DDR2 WLAN TP EC_SMB_CK0 EC_SMB_DA0 +3VALW Control RTS5400 Dual MOS +3.3V_LDO_RTS5400 2.2K RTS5400_SM_SCL RTS5400_SM_SDA 2.2K +3VALW Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Blank4 Custom 4 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Blank4 Custom 4 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Blank4 Custom 4 75 Friday, November 25, 2016 2015/02/26 2016/02/26 WWW.AliSaler.Com
5 5 4 4 3 3 2 2 1 1 D D C C B B A A CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils. I7 : SA00007HB20 I5 : SA00007HS10 Change PEG from X16 to X8 HLZ SDV 20160510 Change PEG from X16 to X8 HLZ SDV 20160510 PEG_COMP DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 DMI_CTX_PRX_N0 DMI_CTX_PRX_N3 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CTX_PRX_P0 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3 DMI_CRX_PTX_P2 DMI_CRX_PTX_P1 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_P0 PEG_COMP PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P7 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N[0..7] 24 PCIE_CRX_GTX_P[0..7] 24 PCIE_CTX_C_GRX_N[0..7] 24 PCIE_CTX_C_GRX_P[0..7] 24 DMI_CTX_PRX_N0 19 DMI_CTX_PRX_N1 19 DMI_CTX_PRX_N2 19 DMI_CTX_PRX_N3 19 DMI_CTX_PRX_P0 19 DMI_CTX_PRX_P1 19 DMI_CTX_PRX_P2 19 DMI_CTX_PRX_P3 19 DMI_CRX_PTX_N0 19 DMI_CRX_PTX_N1 19 DMI_CRX_PTX_N2 19 DMI_CRX_PTX_N3 19 DMI_CRX_PTX_P0 19 DMI_CRX_PTX_P1 19 DMI_CRX_PTX_P2 19 DMI_CRX_PTX_P3 19 VCCIO Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (1/7) DMI,PEG Custom 5 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (1/7) DMI,PEG Custom 5 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (1/7) DMI,PEG Custom 5 75 Friday, November 25, 2016 2015/02/26 2016/02/26 CC24 0.22U_0402_10V6K OPT@ 1 2 CC7 0.22U_0402_10V6K OPT@ 1 2 CC22 0.22U_0402_10V6K OPT@ 1 2 CC5 0.22U_0402_10V6K OPT@ 1 2 RC1 24.9_0402_1% 1 2 CC20 0.22U_0402_10V6K OPT@ 1 2 CC8 0.22U_0402_10V6K OPT@ 1 2 CC19 0.22U_0402_10V6K OPT@ 1 2 CC23 0.22U_0402_10V6K OPT@ 1 2 CC18 0.22U_0402_10V6K OPT@ 1 2 CC6 0.22U_0402_10V6K OPT@ 1 2 CC21 0.22U_0402_10V6K OPT@ 1 2 CC4 0.22U_0402_10V6K OPT@ 1 2 CC3 0.22U_0402_10V6K OPT@ 1 2 CC2 0.22U_0402_10V6K OPT@ 1 2 SKYLAKE_HALO BGA1440 3 OF 14 UC1C SKYLAKE-H-CPU_BGA1440 @ PEG_RXN[0] D25 PEG_RXN[2] D23 PEG_RXP[2] E23 PEG_RXN[1] F24 PEG_RXP[13] F12 DMI_TXN[3] B4 DMI_TXP[3] D4 DMI_TXN[2] A5 DMI_TXP[2] B5 DMI_TXP[1] C6 DMI_TXN[1] B6 DMI_TXN[0] A8 DMI_TXP[0] B8 DMI_RXP[3] J8 DMI_RXN[3] J9 DMI_RXN[2] E5 DMI_RXP[2] D5 DMI_RXP[1] E6 DMI_RXN[1] F6 DMI_RXP[0] D8 DMI_RXN[0] E8 PEG_RCOMP G2 PEG_RXP[15] F10 PEG_RXP[14] D11 PEG_RXN[15] E10 PEG_RXP[8] D17 PEG_RXN[7] F18 PEG_RXP[7] E18 PEG_RXN[3] F22 PEG_RXP[1] E24 PEG_RXP[3] E22 PEG_RXP[4] E21 PEG_RXN[4] D21 PEG_RXP[5] E20 PEG_RXP[6] E19 PEG_RXP[10] D15 PEG_RXN[10] E15 PEG_RXP[11] F14 PEG_RXN[11] E14 PEG_RXP[12] D13 PEG_RXN[13] E12 PEG_RXN[14] E11 PEG_TXP[0] B25 PEG_TXN[0] A25 PEG_TXP[1] B24 PEG_TXN[1] C24 PEG_TXN[2] A23 PEG_TXP[2] B23 PEG_TXN[3] C22 PEG_TXP[3] B22 PEG_TXP[4] B21 PEG_TXN[5] C20 PEG_TXN[4] A21 PEG_TXP[5] B20 PEG_TXN[6] A19 PEG_TXP[6] B19 PEG_TXP[7] B18 PEG_TXP[8] A17 PEG_TXN[10] B15 PEG_TXP[10] A15 PEG_TXN[9] B16 PEG_TXP[11] C14 PEG_TXN[11] B14 PEG_TXN[12] B13 PEG_TXP[12] A13 PEG_TXN[13] B12 PEG_TXP[13] C12 PEG_TXN[14] B11 PEG_TXP[14] A11 PEG_TXP[15] C10 PEG_TXN[15] B10 PEG_RXN[12] E13 PEG_RXN[9] E16 PEG_RXN[8] E17 PEG_TXP[9] C16 PEG_TXN[8] B17 PEG_RXP[9] F16 PEG_TXN[7] C18 PEG_RXN[5] F20 PEG_RXN[6] D19 PEG_RXP[0] E25 CC1 0.22U_0402_10V6K OPT@ 1 2 CC17 0.22U_0402_10V6K OPT@ 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A CFG STRAPS for CPU(Internal PH) R e s e r v e d c o n f i g u r a t i o n l a n e . CFG1 e D P e n a b l e 1 = Disabled. CFG4 P E G T r a i n i n g CFG7 1 = (default) PEG Train immediately following RESET# deassertion. 0 = PEG Wait for BIOS for training. 10 = 2 x8 PCI Express* 00 = 1 x8, 2 x4 PCI Express* 11 = 1 x16 PCI Express* 01 = reserved P C I E x p r e s s * B i f u r c a t i o n CFG[6:5] S t a l l r e s e t s e q u e n c e a f t e r P C U P L L l o c k u n t i l d e - a s s e r t e d 0 = Stall. 1 = (Default) Normal Operation; No stall. CFG0 P C I E x p r e s s * S t a t i c x 1 6 L a n e N u m b e r i n g R e v e r s a l . 1 = Normal operation CFG2 R e s e r v e d c o n f i g u r a t i o n l a n e . CFG3 N/A N/A R e s e r v e d c o n f i g u r a t i o n l a n e . CFG[19:8] N/A 20150527_Mount RC176 to enable DCI function Reserved Cap HLZ SDV 0616 0 = Lane reserval 0 = Enable Change C52&C127 from @ to stuff HLZ SIV 0811 Add C929 HLZ SIV 0811 Add RC184 HLZ SIV 0811 EC_PECI VCCST_PWRGD H_THRMTRIP#_R H_PM_SYNC VCCPWRGOOD_0_R H_PROCHOT#_R CPU_BCLK CPU_PCIBCLK# CPU_PCIBCLK CPU_NSSC_CLK# CPU_NSSC_CLK VR_SVID_ALRT#_R VR_SVID_CLK VR_SVID_DAT VR_SVID_ALRT#_R BUF_CPU_RST# DDR_PG_CTRL H_PM_DOWN_R CPU_TRIGOUT CPU_TRIGIN PCH_TRIGIN XDP_PREQ# CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG0 CFG1 CFG2 CFG0 CFG4 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG5 CFG6 CFG7 H_CATERR# CFG1 H_THRMTRIP#_R H_CATERR# SM_PG_CTRL CPU_BCLK# VR_SVID_DAT VR_SVID_CLK H_PROCHOT#_R H_CPUPWRGD H_THRMTRIP# BUF_CPU_RST# H_PM_SYNC CPU_TRIGIN DDR_PG_CTRL VCCST_PWRGD H_PM_SYNC 14 H_CPUPWRGD 16 H_PROCHOT# 49,65 PCH_CPU_BCLK# 17 PCH_CPU_BCLK 17 PCH_CPU_PCIBCLK# 17 PCH_CPU_PCIBCLK 17 PCH_CPU_NSSC_CLK# 17 PCH_CPU_NSSC_CLK 17 SVID_ALERT# 65 SVID_CLK 65 SVID_DATA 65 CPU_PLTRST# 14 H_PM_DOWN 14 H_THRMTRIP# 14,24 PCH_TRIGIN 22 CPU_TRIGIN 22 XDP_TDO 42 XDP_PRDY# 42 EC_PECI 14,49 CFG3 42 XDP_TDI 42 XDP_TMS 42 XDP_TCK 42 XDP_TRST# 42 XDP_PREQ# 42 SM_PG_CTRL 61 CPUCORE_ON 49,65 VCCST VCCST VCCST VCCIO VCCST +3VALW +1.2V +3VS +3VALW VCCST +3VS Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (2/7) PM, XDP, CLK, CFG C 6 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (2/7) PM, XDP, CLK, CFG C 6 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (2/7) PM, XDP, CLK, CFG C 6 75 Friday, November 25, 2016 2015/02/26 2016/02/26 TC29 PAD @ 1 C128 .1U_0402_10V6-K @ 1 2 C925 .1U_0402_10V6-K @ 1 2 RC4 30_0402_1% 1 2 RC50 60.4_0402_1% 1 2 TC105 PAD @ 1 TC100 PAD @ 1 TC89 PAD @ 1 TC95 PAD @ 1 TC82 PAD @ 1 TC91 PAD @ 1 RC52 1K_0402_5% @ 1 2 RC32 0_0402_5% 1 2 TC77 PAD @ 1 RC75 1K_0402_5% 1 2 RC179 10K_0402_5% @ 1 2 RC142 1K_0402_5% @ 1 2 TC42 PAD @ 1 RC140 1K_0402_5% @ 1 2 RC3 0_0402_5% 1 2 RC28 0_0402_5% 1 2 R292 10K_0402_5% @ 1 2 RC34 0_0402_5% 1 2 RC7 1K_0402_5% 1 2 TC101 PAD @ 1 TC96 PAD @ 1 TC92 PAD @ 1 RC29 0_0402_5% 1 2 TC78 PAD @ 1 RC14 0_0402_5% 1 2 RC22 0_0402_5% 1 2 RC54 1K_0402_5% 1 2 G D S Q1 2N7002KW_SOT323-3 2 1 3 RC177 100K_0402_5% @ 1 2 RC11 1K_0402_5% 1 2 RC15 0_0402_5% 1 2 C929 330P_0402_50V8J 1 2 RC53 1K_0402_5% 1 2 RC33 20_0402_1% 1 2 RC174 10K_0402_5% @ 1 2 RC13 0_0402_5% 1 2 C126 .1U_0402_10V6-K @ 1 2 TC102 PAD @ 1 TC97 PAD @ 1 TC83 PAD @ 1 TC79 PAD @ 1 TC86 PAD @ 1 RC76 56.2_0402_1% 1 2 RC143 1K_0402_5% @ 1 2 RC17 0_0402_5% 1 2 RC146 1K_0402_5% @ 1 2 E B C QC1 MMBT3904WH_SOT323-3 2 3 1 G D S Q2 2N7002KW_SOT323-3 2 1 3 RC56 1K_0402_5% @ 1 2 RC184 1K_0402_5% 1 2 RC66 100_0402_1% 1 2 RC16 0_0402_5% 1 2 RC55 1K_0402_5% @ 1 2 RC65 220_0402_5% 1 2 TC103 PAD @ 1 RC57 1K_0402_1% @ 1 2 TC98 PAD @ 1 TC93 PAD @ 1 TC84 PAD @ 1 RC178 100K_0402_5% 1 2 TC80 PAD @ 1 TC87 PAD @ 1 C133 .1U_0402_10V6-K @ 1 2 C120 .1U_0402_10V6-K @ 1 2 RC141 1K_0402_5% @ 1 2 TC27 PAD @ 1 RC175 49.9_0402_1% 1 2 RC139 1K_0402_5% @ 1 2 R291 10K_0402_5% 1 2 C52 .1U_0402_10V6-K 1 2 TC104 PAD @ 1 RC51 1K_0402_5% @ 1 2 TC99 PAD @ 1 TC94 PAD @ 1 TC28 PAD @ 1 TC90 PAD @ 1 RC144 1K_0402_5% @ 1 2 TC85 PAD @ 1 TC81 PAD @ 1 TC88 PAD @ 1 SKYLAKE_HALO BGA1440 5 OF 14 UC1E SKYLAKE-H-CPU_BGA1440 @ PROC_SELECT# BN1 CATERR# BM30 SKTOCC# BR33 PM_DOWN BP31 PM_SYNC BM34 RESET# BP35 PROCPWRGD BT31 VCCST_PWRGD H13 CFG[17] BN23 CFG[15] BT19 CFG[16] BP23 CFG[11] BT22 CFG[12] BM19 CFG[10] BT23 CFG[9] BR22 CLK24N D31 CFG[1] BN27 CFG[3] BN28 CFG[18] BN22 PROC_TDI BL32 CFG[0] BN25 CFG[2] BN26 CFG[4] BR20 CFG[6] BT20 CFG[5] BM20 CFG[7] BP20 CFG[8] BR23 CFG[13] BR19 CFG[14] BP19 CFG[19] BP22 PROC_PREQ# BL30 PROC_PRDY# BP27 VIDSCK BH32 PROC_TDO BT28 CLK24P E31 PCI_BCLKN C36 PCI_BCLKP D35 BCLKN A32 VIDSOUT BH29 PROCHOT# BR30 DDR_VTT_CNTL BT13 CFG_RCOMP BT25 PROC_TRST# BP30 PROC_TCK BR28 PROC_TMS BP28 VIDALERT# BH31 THERMTRIP# J31 PECI BT34 BCLKP B31 BPM#[0] BR27 BPM#[1] BT27 BPM#[2] BM31 BPM#[3] BT30 BGA1440 SKYLAKE_HALO 11 OF 14 UC1K SKYLAKE-H-CPU_BGA1440 @ RSVD_47 BT17 RSVD_48 BR17 RSVD_44 BJ28 RSVD_43 BK28 RSVD_TP_12 BK16 RSVD_TP_11 BJ16 VSS_447 BJ18 RSVD_27 BL34 RSVD_26 BN33 RSVD_TP_10 BJ13 RSVD_31 AA14 RSVD_30 AE29 RSVD_TP_6 BT2 RSVD_23 BN35 RSVD_24 J24 RSVD_TP_3 E3 RSVD_TP_4 E2 RSVD_TP_5 BR1 RSVD_32 A36 NCTF_6 C38 NCTF_5 C1 NCTF_4 BR2 NCTF_3 BP1 NCTF_1 B2 NCTF_2 B38 PROC_TRIGOUT J23 PROC_TRIGIN H23 RSVD_33 A37 RSVD_29 R14 RSVD_28 N29 RSVD_25 H24 RSVD_TP_9 BJ14 RSVD_50 AJ8 RSVD_TP_1 D1 RSVD_TP_2 E1 RSVD_TP_7 BM33 RSVD_TP_8 BL33 RSVD_TP_13 BK24 RSVD_TP_14 BJ24 RSVD_45 BK21 RSVD_46 BJ21 VSS_448 BK18 RSVD_TP_15 BJ34 RSVD_TP_16 BJ33 RSVD_49 G13 RSVD_51 BL31 RSVD_34 F30 RSVD_35 E30 RSVD_36 B30 RSVD_37 C30 RSVD_38 G3 RSVD_39 J3 RSVD_40 BR35 RSVD_41 BR31 RSVD_42 BH30 RC176 51_0402_1% 1 2 RC9 499_0402_1% 1 2 C127 .1U_0402_10V6-K 1 2 WWW.AliSaler.Com
5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR4 COMPENSATION SIGNALS CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil CAD Note: Trace width= 20 mil, Spcing=20 mils DDR_VREF_CA : Connected to VREF_CA on DIMM CH-A DDR0_VREF_DQ : NC DDR1_VREF_DQ : Connected to VREF_CA on DIMM CH-B DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10_AP DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_BG1 DDRA_ACT# DDRA_DQS0 DDRA_DQS1 DDRA_DQS2 DDRA_DQS3 DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63 +VREF_DQ_DIMM_R +V_DDR_REF_R +V_DDR_REFB_R DDRA_DQS#0 DDRA_DQS#1 DDRA_DQS#2 DDRA_DQS#3 DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10_AP DDRB_MA11 DDRB_MA12 DDRB_MA13 DDRB_BG1 DDRB_ACT# DDRB_DQS#0 DDRB_DQS#1 DDRB_DQS#2 DDRB_DQS#3 DDRB_DQS#4 DDRB_DQS#5 DDRB_DQS#6 DDRB_DQS#7 DDRB_DQS0 DDRB_DQS1 DDRB_DQS2 DDRB_DQS3 DDRB_DQS4 DDRB_DQS5 DDRB_DQS6 DDRB_DQS7 SM_RCOMP1 SM_RCOMP2 SM_RCOMP0 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 +V_DDR_REFA_R DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 DDRA_PARITY DDRA_ALERT# DDRB_PARITY DDRB_ALERT# DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS7 DDRA_DQS#4 DDRA_DQS#5 DDRA_DQS#6 DDRA_DQS#7 DDRA_DQ[0..63] 12 DDRA_CLK0# 12 DDRA_CS0# 12 DDRA_BA0 12 DDRA_MA16_RAS# 12 DDRA_MA14_WE# 12 DDRA_MA15_CAS# 12 DDRA_CLK0 12 DDRA_CKE0 12 DDRA_CLK1 12 DDRA_CLK1# 12 DDRA_CKE1 12 DDRA_CS1# 12 DDRA_BA1 12 DDRA_BG0 12 DDRA_MA[0..9] 12 DDRB_DQ[0..63] 13 DDRB_CLK0# 13 DDRB_CLK0 13 DDRB_CKE0 13 DDRB_CLK1 13 DDRB_CLK1# 13 DDRB_CKE1 13 DDRB_CS0# 13 DDRB_CS1# 13 DDRB_MA16_RAS# 13 DDRB_MA14_WE# 13 DDRB_MA15_CAS# 13 DDRB_MA[0..9] 13 DDRB_DQS#[0..7] 13 DDRB_DQS[0..7] 13 DDRB_BA0 13 DDRB_BA1 13 DDRB_BG0 13 DDRA_ODT0 12 DDRA_ODT1 12 DDRB_ODT0 13 DDRB_ODT1 13 DDRB_MA10_AP 13 DDRB_MA11 13 DDRB_MA12 13 DDRB_MA13 13 DDRB_BG1 13 DDRB_ACT# 13 DDRA_MA10_AP 12 DDRA_MA11 12 DDRA_MA12 12 DDRA_MA13 12 DDRA_BG1 12 DDRA_ALERT# 12 DDRA_PARITY 12 DDRB_ALERT# 13 DDRB_PARITY 13 DDRA_DQS#[0..7] 12 DDRA_DQS[0..7] 12 DDRA_ACT# 12 +VREF_DQ_DIMMB_R +VREF_CA_DIMMA_R Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (3/7) DDRVI C 7 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (3/7) DDRVI C 7 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (3/7) DDRVI C 7 75 Friday, November 25, 2016 2015/02/26 2016/02/26 RC6 75_0402_1% 1 2 RC147 0_0402_5% 1 2 RC36 0_0402_5% @ 1 2 RC37 0_0402_5% 1 2 RC8 100_0402_1% 1 2 TC109 PAD @ 1 DDR CHANNEL A SKYLAKE_HALO BGA1440 1 OF 14 UC1A SKYLAKE-H-CPU_BGA1440 @ DDR0_DQ[36]/DDR1_DQ[4] AB5 DDR0_DQ[35]/DDR1_DQ[3] AA5 DDR0_DQ[34]/DDR1_DQ[2] AA4 DDR0_DQ[32]/DDR1_DQ[0] AB1 DDR0_DQ[31]/DDR0_DQ[47] BC2 DDR0_DQ[30]/DDR0_DQ[46] BC1 DDR0_DQ[45]/DDR1_DQ[13] V4 DDR0_ECC[6] AY1 DDR0_DQ[63]/DDR1_DQ[47] L1 DDR0_DQ[54]/DDR1_DQ[38] R1 DDR0_DQ[55]/DDR1_DQ[39] P1 DDR0_DQ[43]/DDR1_DQ[11] U2 DDR0_DQ[28]/DDR0_DQ[44] BD5 DDR0_DQ[20]/DDR0_DQ[36] BG2 DDR0_DQ[19]/DDR0_DQ[35] BF5 DDR0_DQ[16]/DDR0_DQ[32] BG4 DDR0_ECC[4] BA5 DDR0_DQ[60]/DDR1_DQ[44] M5 DDR0_DQ[4] BN5 DDR0_DQ[2] BP3 DDR0_DQ[3] BR3 DDR0_DQ[5] BP6 DDR0_DQ[6] BP2 DDR0_DQ[7] BN3 DDR0_DQ[8] BL4 DDR0_DQ[9] BL5 DDR0_DQ[10] BL2 DDR0_DQ[11] BM1 DDR0_DQ[13] BK5 DDR0_DQ[14] BK1 DDR0_DQ[18]/DDR0_DQ[34] BF4 DDR0_DQ[21]/DDR0_DQ[37] BG1 DDR0_DQ[23]/DDR0_DQ[39] BF2 DDR0_DQ[25]/DDR0_DQ[41] BD1 DDR0_DQ[27]/DDR0_DQ[43] BC5 DDR0_DQ[29]/DDR0_DQ[45] BD4 DDR0_DQ[12] BK4 DDR0_DQ[17]/DDR0_DQ[33] BG5 DDR0_DQ[15] BK2 DDR0_CKP[0] AG1 DDR0_DQ[42]/DDR1_DQ[10] U1 DDR0_DQ[41]/DDR1_DQ[9] V2 DDR0_DQ[40]/DDR1_DQ[8] V5 DDR0_DQ[37]/DDR1_DQ[5] AB4 DDR0_DQ[33]/DDR1_DQ[1] AB2 DDR0_DQ[26]/DDR0_DQ[42] BC4 DDR0_DQ[22]/DDR0_DQ[38] BF1 DDR0_ECC[3] AY5 DDR0_DQ[58]/DDR1_DQ[42] L4 DDR0_DQ[52]/DDR1_DQ[36] R5 DDR0_DQ[47]/DDR1_DQ[15] U4 DDR0_DQ[44]/DDR1_DQ[12] V1 DDR0_DQ[39]/DDR1_DQ[7] AA1 DDR0_DQSP[8] AY3 DDR0_DQSN[8] BA3 DDR0_DQSN[7]/DDR1_DQSN[5] L3 DDR0_DQSN[6]/DDR1_DQSN[4] P3 DDR0_DQSN[5]/DDR1_DQSN[1] U3 DDR0_DQSN[4]/DDR1_DQSN[0] AA3 DDR0_DQSP[3]/DDR0_DQSP[5] BC3 DDR0_DQSP[2]/DDR0_DQSP[4] BF3 DDR0_DQSP[1] BK3 DDR0_DQSP[0] BP5 DDR0_DQSP[7]/DDR1_DQSP[5] M3 DDR0_DQSP[5]/DDR1_DQSP[1] V3 DDR0_DQSP[6]/DDR1_DQSP[4] R3 DDR0_DQSN[3]/DDR0_DQSN[5] BD3 DDR0_DQSP[4]/DDR1_DQSP[0] AB3 DDR0_DQSN[1] BL3 DDR0_DQSN[2]/DDR0_DQSN[4] BG3 DDR0_DQSN[0] BR5 DDR0_PAR AG3 DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU2 DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AU3 DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AE3 DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AU4 DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] AN2 DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AN3 DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AT4 DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AH2 DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AP3 DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AN1 DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AP1 DDR0_MA[4] AP2 DDR0_MA[3] AP5 DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AN4 DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AP4 DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AH3 DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AD1 DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AG4 DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AH4 DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AU1 DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AH1 DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AH5 DDR0_ODT[3] AD4 DDR0_ODT[2] AE1 DDR0_ODT[1] AE4 DDR0_CS#[3] AE5 DDR0_ODT[0] AD3 DDR0_CS#[2] AD2 DDR0_CS#[1] AE2 DDR0_CKE[3] AT5 DDR0_CS#[0] AD5 DDR0_CKE[1] AT2 DDR0_CKE[2] AT3 DDR0_CKE[0] AT1 DDR0_CLKN[3] AL1 DDR0_CLKN[2] AK3 DDR0_CLKP[3] AL2 DDR0_CLKP[2] AL3 DDR0_CKP[1] AK2 DDR0_CKN[1] AK1 DDR0_CKN[0] AG2 DDR0_ECC[7] AY2 DDR0_ECC[5] BA4 DDR0_ECC[2] AY4 DDR0_ECC[1] BA1 DDR0_ECC[0] BA2 DDR0_DQ[62]/DDR1_DQ[46] L5 DDR0_DQ[61]/DDR1_DQ[45] M2 DDR0_DQ[59]/DDR1_DQ[43] L2 DDR0_DQ[56]/DDR1_DQ[40] M4 DDR0_DQ[57]/DDR1_DQ[41] M1 DDR0_DQ[53]/DDR1_DQ[37] P2 DDR0_DQ[51]/DDR1_DQ[35] P4 DDR0_DQ[50]/DDR1_DQ[34] R4 DDR0_DQ[49]/DDR1_DQ[33] P5 DDR0_DQ[48]/DDR1_DQ[32] R2 DDR0_DQ[46]/DDR1_DQ[14] U5 DDR0_DQ[38]/DDR1_DQ[6] AA2 DDR0_DQ[24]/DDR0_DQ[40] BD2 DDR0_ALERT# AU5 DDR0_DQ[1] BT6 DDR0_DQ[0] BR6 RC5 121_0402_1% 1 2 DDR CHANNEL B BGA1440 SKYLAKE_HALO 2 OF 14 UC1B SKYLAKE-H-CPU_BGA1440 @ DDR1_DQ[0]/DDR0_DQ[16] BT11 DDR1_DQ[3]/DDR0_DQ[19] BR8 DDR1_DQ[4]/DDR0_DQ[20] BP11 DDR1_DQ[5]/DDR0_DQ[21] BN11 DDR1_DQ[6]/DDR0_DQ[22] BP8 DDR1_DQ[7]/DDR0_DQ[23] BN8 DDR1_DQ[8]/DDR0_DQ[24] BL12 DDR1_DQ[9]/DDR0_DQ[25] BL11 DDR1_DQ[11]/DDR0_DQ[27] BJ8 DDR1_DQ[12]/DDR0_DQ[28] BJ11 DDR1_DQ[14]/DDR0_DQ[30] BL7 DDR1_DQ[15]/DDR0_DQ[31] BJ7 DDR1_DQ[2]/DDR0_DQ[18] BT8 DDR1_DQ[1]/DDR0_DQ[17] BR11 DDR1_ECC[3] AW8 DDR1_ECC[4] AY10 DDR1_ECC[5] AW10 DDR1_ECC[6] AY7 DDR1_ECC[7] AW7 DDR1_DQ[61] M10 DDR1_DQ[60] L10 DDR1_DQ[59] M8 DDR1_DQ[58] L7 DDR1_DQ[57] M11 DDR1_DQ[56] L11 DDR1_DQ[55] P8 DDR1_DQ[54] R7 DDR1_DQ[53] P10 DDR1_ODT[0] AF7 DDR1_CS#[3] AE10 DDR1_CS#[2] AF10 DDR1_ODT[1] AE8 DDR1_ODT[2] AE9 DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] AH10 DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AH9 DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] AJ9 DDR1_DQSN[6] R9 DDR0_VREF_DQ BP13 DDR_VREF_CA BN13 DDR1_DQSN[5]/DDR1_DQSN[3] W9 DDR1_PAR AJ7 DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AT9 DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] AR7 DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AF9 DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN11 DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AR10 DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AH7 DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AN8 DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AR11 DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN10 DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN7 DDR1_MA[3] AL5 DDR1_MA[4] AL6 DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AM6 DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AK5 DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AK6 DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AR9 DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AH8 DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AH11 DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AF8 DDR1_ODT[3] AE11 DDR1_CS#[1] AE7 DDR1_CKE[3] AT11 DDR1_CS#[0] AF11 DDR1_CKE[2] AT7 DDR1_CKE[1] AT10 DDR1_CKE[0] AT8 DDR1_CLKN[3] AJ11 DDR1_CLKP[3] AJ10 DDR1_CLKN[2] AM10 DDR1_CLKP[2] AM11 DDR1_CKP[1] AM7 DDR1_CKN[1] AM8 DDR1_CKP[0] AM9 DDR1_CKN[0] AN9 DDR1_ECC[2] AY8 DDR1_ECC[1] AY11 DDR1_ECC[0] AW11 DDR1_DQ[63] L8 DDR1_DQ[62] M7 DDR1_DQ[51] R8 DDR1_DQ[52] R10 DDR1_DQ[50] P7 DDR1_DQ[49] P11 DDR1_DQ[48] R11 DDR1_DQ[46]/DDR1_DQ[30] V7 DDR1_DQ[47]/DDR1_DQ[31] V8 DDR1_DQ[45]/DDR1_DQ[29] W10 DDR1_DQ[43]/DDR1_DQ[27] V11 DDR1_DQ[44]/DDR1_DQ[28] W11 DDR1_DQ[40]/DDR1_DQ[24] W8 DDR1_DQ[42]/DDR1_DQ[26] V10 DDR1_DQ[41]/DDR1_DQ[25] W7 DDR1_DQ[39]/DDR1_DQ[23] AC7 DDR1_DQ[38]/DDR1_DQ[22] AC8 DDR1_DQ[37]/DDR1_DQ[21] AA8 DDR1_DQ[29]/DDR0_DQ[61] BB10 DDR1_DQ[23]/DDR0_DQ[55] BF7 DDR1_DQ[20]/DDR0_DQ[52] BF11 DDR1_DQ[21]/DDR0_DQ[53] BF10 DDR1_DQ[17]/DDR0_DQ[49] BG10 DDR1_DQ[18]/DDR0_DQ[50] BG8 DDR1_DQ[16]/DDR0_DQ[48] BG11 DDR1_DQ[13]/DDR0_DQ[29] BJ10 DDR1_DQ[10]/DDR0_DQ[26] BL8 DDR1_DQ[19]/DDR0_DQ[51] BF8 DDR1_DQ[26]/DDR0_DQ[58] BB8 DDR1_VREF_DQ BR13 DDR1_DQSN[8] AY9 DDR1_DQSP[8] AW9 DDR1_DQSP[7] L9 DDR1_DQSP[6] P9 DDR1_DQSP[5]/DDR1_DQSP[3] V9 DDR1_DQSP[4]/DDR1_DQSP[2] AA9 DDR1_DQSP[3]/DDR0_DQSP[7] BB9 DDR1_DQSP[2]/DDR0_DQSP[6] BF9 DDR1_DQSP[1]/DDR0_DQSP[3] BJ9 DDR1_DQSP[0]/DDR0_DQSP[2] BR9 DDR1_DQSN[7] M9 DDR1_DQSN[4]/DDR1_DQSN[2] AC9 DDR1_DQSN[3]/DDR0_DQSN[7] BC9 DDR1_DQSN[2]/DDR0_DQSN[6] BG9 DDR1_DQSN[1]/DDR0_DQSN[3] BL9 DDR1_DQSN[0]/DDR0_DQSN[2] BP9 DDR1_ALERT# AR8 DDR1_DQ[36]/DDR1_DQ[20] AA7 DDR1_DQ[35]/DDR1_DQ[19] AC10 DDR1_DQ[34]/DDR1_DQ[18] AC11 DDR1_DQ[33]/DDR1_DQ[17] AA10 DDR1_DQ[32]/DDR1_DQ[16] AA11 DDR1_DQ[31]/DDR0_DQ[63] BB7 DDR1_DQ[30]/DDR0_DQ[62] BC7 DDR1_DQ[28]/DDR0_DQ[60] BC10 DDR1_DQ[27]/DDR0_DQ[59] BC8 DDR1_DQ[25]/DDR0_DQ[57] BC11 DDR1_DQ[24]/DDR0_DQ[56] BB11 DDR1_DQ[22]/DDR0_DQ[54] BG7 DDR_RCOMP[0] G1 DDR_RCOMP[1] H1 DDR_RCOMP[2] J2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A COMPENSATION PU FOR eDP CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils. Need create 5% P/N Place near CPU. Delete eDP Lane2&3 HLZ SDV 20160510 HDMI D1 HDMI D0 HDMI CLK HDMI D2 Type C DP Different to Y710 HLZ SDV 20160510 Reserved Cap HLZ SDV 0616 CPU_EDP_AUX# CPU_EDP_AUX EDP_COMP CPU_EDP_TX0- CPU_EDP_TX0+ CPU_EDP_TX1- CPU_EDP_TX1+ PROC_AUDIO_SDO_CPU PROC_AUDIO_SDI_CPU_R PROC_AUDIO_CLK_CPU TYPE-C_DP_TXN2 TYPE-C_DP_TXN1 TYPE-C_DP_TXN3 TYPE-C_DP_TXP3 TYPE-C_DP_TXN0 TYPE-C_DP_AUXN TYPE-C_DP_AUXP TYPE-C_DP_TXP2 TYPE-C_DP_TXP1 TYPE-C_DP_TXP0 HDMI_TXC+ HDMI_TXC- HDMI_TX0+ HDMI_TX1+ HDMI_TX2+ HDMI_TX2- HDMI_TX0- HDMI_TX1- PROC_AUDIO_SDO_CPU CPU_EDP_AUX# 35 CPU_EDP_AUX 35 CPU_EDP_TX0- 35 CPU_EDP_TX0+ 35 CPU_EDP_TX1- 35 CPU_EDP_TX1+ 35 PROC_AUDIO_SDI_CPU 16 PROC_AUDIO_CLK_CPU 16 PROC_AUDIO_SDO_CPU 16 TYPE-C_DP_AUXP 37 TYPE-C_DP_AUXN 37 TYPE-C_DP_TXN3 37 TYPE-C_DP_TXP3 37 TYPE-C_DP_TXN2 37 TYPE-C_DP_TXP2 37 TYPE-C_DP_TXN1 37 TYPE-C_DP_TXP1 37 TYPE-C_DP_TXP0 37 TYPE-C_DP_TXN0 37 HDMI_TX2+ 36 HDMI_TX2- 36 HDMI_TX1+ 36 HDMI_TX1- 36 HDMI_TX0+ 36 HDMI_TX0- 36 HDMI_TXC+ 36 HDMI_TXC- 36 VCCIO Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (4/7) eDP, DDI Custom 8 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (4/7) eDP, DDI Custom 8 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (4/7) eDP, DDI Custom 8 75 Friday, November 25, 2016 2015/02/26 2016/02/26 CH14 10P_0402_50V8J @ 1 2 RC49 24.9_0402_1% 1 2 RC180 20_0402_1% 1 2 RH762 33_0402_5% @ 1 2 SKYLAKE_HALO BGA1440 4 OF 14 UC1D SKYLAKE-H-CPU_BGA1440 @ DDI1_TXN[3] J38 EDP_TXN[1] E28 EDP_TXN[2] B29 EDP_TXP[2] A29 DDI1_TXN[2] H36 DDI1_TXP[3] J37 EDP_TXP[0] D29 EDP_TXN[0] E29 EDP_TXP[1] F28 EDP_TXN[3] B28 EDP_TXP[3] C28 EDP_AUXP C26 EDP_AUXN B26 EDP_DISP_UTIL A33 EDP_RCOMP D37 PROC_AUDIO_CLK G27 PROC_AUDIO_SDI G25 PROC_AUDIO_SDO G29 DDI1_AUXP D27 DDI2_TXN[2] F35 DDI2_TXP[3] E37 DDI2_TXP[2] F34 DDI2_TXN[1] G38 DDI2_TXP[1] F37 DDI2_TXN[0] H33 DDI2_TXP[0] H34 DDI1_AUXN E27 DDI2_TXN[3] E36 DDI2_AUXN E26 DDI2_AUXP F26 DDI3_TXP[0] C34 DDI3_TXN[0] D34 DDI3_TXP[1] B36 DDI3_TXN[1] B34 DDI3_TXP[2] F33 DDI3_TXN[2] E33 DDI3_TXP[3] C33 DDI3_TXN[3] B33 DDI3_AUXN B27 DDI3_AUXP A27 DDI1_TXP[0] K36 DDI1_TXN[0] K37 DDI1_TXP[1] J35 DDI1_TXN[1] J34 DDI1_TXP[2] H37 CH264 10P_0402_50V8J @ 1 2 WWW.AliSaler.Com
5 5 4 4 3 3 2 2 1 1 D D C C B B A A VCC_SENSE CAD Note: RC39 SHOULD BE PLACED CLOSE TO CPU CAD Note: RC38 SHOULD BE PLACED CLOSE TO CPU VCCGT_SENSE CRB place to CPU CRB place to CPU 10uF 28pcs 1uF 64pcs 10uF 35pcs 1uF 68pcs Near CPU Near CPU MAX 68A MAX 55A SDV Cost down list: 10U 10Pcs 1U 28Pcs Cost down list: 10U 5Pcs 1U 19Pcs SIV Cost down list: 10U 9Pcs 1U 19Pcs Change CH109&CH110&CH135&CH140 from stuff to@ Change CH93&CH122&CH105&CH150 from @ to stuff HLZ SIV 0811 VSSSENSE_R VCCSENSE_R VCCGT_SENSE_R VSSGT_SENSE_R VCCSENSE_R VSSSENSE_R VSSGT_SENSE_R VCCGT_SENSE_R VSSCORE_SENSE 65 VCCCORE_SENSE 65 VSSGT_SENSE 65 VCCGT_SENSE 65 VCCCPUCORE VCCCPUCORE VCCCPUCORE VCCCPUCORE VCCGFXCORE VCCGFXCORE VCCGFXCORE VCCGFXCORE VCCGFXCORE VCCGFXCORE Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (5/7) PWR, BYPASS D 9 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (5/7) PWR, BYPASS D 9 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (5/7) PWR, BYPASS D 9 75 Friday, November 25, 2016 2015/02/26 2016/02/26 CH147 1U_0201_6.3V6K 1 2 CH205 1U_0201_6.3V6K 1 2 CH115 1U_0201_6.3V6K 1 2 RC63 100_0402_1% 1 2 CH104 1U_0201_6.3V6K @ 1 2 CH122 1U_0201_6.3V6K @ 1 2 CC113 10U_0402_6.3V6M 1 2 CH154 1U_0201_6.3V6K 1 2 CH235 1U_0201_6.3V6K 1 2 CC76 10U_0402_6.3V6M 1 2 CD77 33P_0402_50V8J RF_NS@ 1 2 RC59 100_0402_1% 1 2 CC132 10U_0402_6.3V6M @ 1 2 CH135 1U_0201_6.3V6K 1 2 CC88 10U_0402_6.3V6M @ 1 2 CC111 10U_0402_6.3V6M 1 2 CH206 1U_0201_6.3V6K 1 2 CH182 1U_0201_6.3V6K @ 1 2 CH148 1U_0201_6.3V6K 1 2 CH116 1U_0201_6.3V6K 1 2 CH218 1U_0201_6.3V6K 1 2 CH105 1U_0201_6.3V6K @ 1 2 CH123 1U_0201_6.3V6K 1 2 CC77 10U_0402_6.3V6M 1 2 CH155 1U_0201_6.3V6K 1 2 CH136 1U_0201_6.3V6K 1 2 TC60 PAD @ 1 CH194 1U_0201_6.3V6K @ 1 2 CH170 1U_0201_6.3V6K @ 1 2 SKYLAKE_HALO BGA1440 14 OF 14 UC1N SKYLAKE-H-CPU_BGA1440 @ VCCGT_189 AU38 VCCGT_188 AU37 VCCGT_187 AU36 VCCGT_186 AU35 VCCGT_185 AU32 VCCGT_184 AU31 VCCGT_183 AU30 VCCGT_182 AU29 VCCGT_181 AU14 VCCGT_180 AT38 VCCGT_179 AT37 VCCGT_178 AT36 VCCGT_177 AT35 VCCGT_176 AT34 VCCGT_175 AT33 VCCGT_174 AT32 VCCGT_173 AT31 VCCGT_172 AT14 VCCGT_171 AR36 VCCGT_170 AR35 VCCGT_169 AR34 VCCGT_168 AR33 VCCGT_167 AR32 VCCGT_166 AR31 VCCGT_165 AR30 VCCGT_164 AR29 VCCGT_163 AP38 VCCGT_162 AP37 VCCGT_161 AP36 VCCGT_160 AP35 VCCGT_159 AP32 VCCGT_158 AP31 VCCGT_157 AP30 VCCGT_156 AP29 VCCGT_155 AP14 VCCGT_154 AP13 VCCGT_153 AN38 VCCGT_152 AN37 VCCGT_151 AN36 VCCGT_150 AN35 VCCGT_149 AN34 VCCGT_148 AN33 VCCGT_147 AN32 VCCGT_146 AN31 VCCGT_145 AN14 VCCGT_144 AN13 VCCGT_143 AM36 VCCGT_142 AM35 VCCGT_141 AM34 VCCGT_140 AM33 VCCGT_139 AM32 VCCGT_138 AM31 VCCGT_137 AM30 VCCGT_136 AM29 VCCGT_135 AM14 VCCGT_134 AM13 VCCGT_133 AL38 VCCGT_132 AL37 VCCGT_131 AL36 VCCGT_130 AL35 VCCGT_129 AL32 VCCGT_128 AL31 VCCGT_127 AL30 VCCGT_126 AL29 VCCGT_125 AL13 VCCGT_124 AK38 VCCGT_123 AK37 VCCGT_122 AK36 VCCGT_121 AK35 VCCGT_120 AK34 VCCGT_119 AK33 VCCGT_118 AK32 VCCGT_117 AK31 VCCGT_116 AJ36 VCCGT_115 AJ35 VCCGT_114 AJ34 VCCGT_113 AJ33 VCCGT_112 AJ32 VCCGT_111 AJ31 VCCGT_110 AJ30 VCCGT_109 AJ29 VCCGTX_22 AJ14 VCCGTX_21 AJ13 VCCGT_SENSE AH38 VSSGT_SENSE AH37 VCCGTX_SENSE AH36 VSSGTX_SENSE AH35 VCCGTX_20 AH32 VCCGTX_19 AH31 VCCGTX_18 AH30 VCCGTX_17 AH29 VCCGTX_16 AH14 VCCGTX_15 AH13 VCCGTX_14 AG36 VCCGTX_13 AG35 VCCGTX_12 AG34 VCCGTX_11 AG33 VCCGTX_10 AG32 VCCGTX_9 AG31 VCCGTX_8 AG14 VCCGTX_7 AG13 VCCGTX_6 AF34 VCCGTX_5 AF33 VCCGTX_4 AF32 VCCGTX_3 AF31 VCCGTX_2 AF30 VCCGTX_1 AF29 CC90 10U_0402_6.3V6M @ 1 2 CH96 1U_0201_6.3V6K 1 2 CC112 10U_0402_6.3V6M @ 1 2 CH106 1U_0201_6.3V6K 1 2 CH158 1U_0201_6.3V6K @ 1 2 CH124 1U_0201_6.3V6K 1 2 CC115 10U_0402_6.3V6M 1 2 CD78 33P_0402_50V8J RF_NS@ 1 2 CH156 1U_0201_6.3V6K 1 2 CC78 10U_0402_6.3V6M 1 2 CC134 10U_0402_6.3V6M 1 2 CH195 1U_0201_6.3V6K @ 1 2 RC62 100_0402_1% 1 2 CH137 1U_0201_6.3V6K 1 2 CC91 10U_0402_6.3V6M 1 2 CH208 1U_0201_6.3V6K 1 2 CH184 1U_0201_6.3V6K @ 1 2 RC41 0_0402_5% 1 2 RC60 100_0402_1% 1 2 CH220 1U_0201_6.3V6K @ 1 2 CH107 1U_0201_6.3V6K 1 2 CH159 1U_0201_6.3V6K @ 1 2 CH125 1U_0201_6.3V6K @ 1 2 CC116 10U_0402_6.3V6M @ 1 2 CC79 10U_0402_6.3V6M @ 1 2 CH138 1U_0201_6.3V6K 1 2 CH117 1U_0201_6.3V6K 1 2 CH196 1U_0201_6.3V6K @ 1 2 CH172 1U_0201_6.3V6K @ 1 2 CC92 10U_0402_6.3V6M 1 2 CH185 1U_0201_6.3V6K 1 2 CH160 1U_0201_6.3V6K @ 1 2 CH126 1U_0201_6.3V6K @ 1 2 CH108 1U_0201_6.3V6K 1 2 CH97 1U_0201_6.3V6K 1 2 CC80 10U_0402_6.3V6M 1 2 CH197 1U_0201_6.3V6K @ 1 2 CH173 1U_0201_6.3V6K 1 2 CH139 1U_0201_6.3V6K 1 2 CC123 10U_0402_6.3V6M 1 2 CH118 1U_0201_6.3V6K 1 2 CC103 10U_0402_6.3V6M 1 2 CC93 10U_0402_6.3V6M @ 1 2 CH210 1U_0201_6.3V6K @ 1 2 CH161 1U_0201_6.3V6K 1 2 CH127 1U_0201_6.3V6K 1 2 CC118 10U_0402_6.3V6M 1 2 CC81 10U_0402_6.3V6M 1 2 CH98 1U_0201_6.3V6K @ 1 2 CH119 1U_0201_6.3V6K @ 1 2 CH140 1U_0201_6.3V6K 1 2 CC124 10U_0402_6.3V6M 1 2 CC95 10U_0402_6.3V6M @ 1 2 CC102 10U_0402_6.3V6M @ 1 2 CC104 10U_0402_6.3V6M @ 1 2 CH186 1U_0201_6.3V6K @ 1 2 CH128 1U_0201_6.3V6K 1 2 CC119 10U_0402_6.3V6M 1 2 CH99 1U_0201_6.3V6K @ 1 2 CC82 10U_0402_6.3V6M 1 2 CH141 1U_0201_6.3V6K 1 2 CC125 10U_0402_6.3V6M 1 2 CH120 1U_0201_6.3V6K @ 1 2 CH109 1U_0201_6.3V6K 1 2 CC94 10U_0402_6.3V6M 1 2 RC38 0_0402_5% 1 2 CH187 1U_0201_6.3V6K 1 2 CH129 1U_0201_6.3V6K @ 1 2 CC120 10U_0402_6.3V6M 1 2 CC83 10U_0402_6.3V6M 1 2 CH100 1U_0201_6.3V6K 1 2 CH200 1U_0201_6.3V6K 1 2 CH142 1U_0201_6.3V6K 1 2 CC97 10U_0402_6.3V6M 1 2 CH110 1U_0201_6.3V6K 1 2 CC106 10U_0402_6.3V6M 1 2 CH149 1U_0201_6.3V6K 1 2 CH164 1U_0201_6.3V6K @ 1 2 CH130 1U_0201_6.3V6K 1 2 CC121 10U_0402_6.3V6M @ 1 2 CH188 1U_0201_6.3V6K 1 2 CC84 10U_0402_6.3V6M 1 2 CH143 1U_0201_6.3V6K @ 1 2 CC127 10U_0402_6.3V6M @ 1 2 TC62 PAD @ 1 CH201 1U_0201_6.3V6K 1 2 CH213 1U_0201_6.3V6K 1 2 CC173 10U_0402_6.3V6M 1 2 CH111 1U_0201_6.3V6K @ 1 2 CH150 1U_0201_6.3V6K @ 1 2 CC107 10U_0402_6.3V6M @ 1 2 CH121 1U_0201_6.3V6K 1 2 CH165 1U_0201_6.3V6K @ 1 2 CH131 1U_0201_6.3V6K 1 2 CC85 10U_0402_6.3V6M 1 2 CH94 1U_0201_6.3V6K 1 2 CH202 1U_0201_6.3V6K 1 2 CD75 33P_0402_50V8J RF_NS@ 1 2 CH144 1U_0201_6.3V6K 1 2 CC128 10U_0402_6.3V6M @ 1 2 CC100 10U_0402_6.3V6M 1 2 CH112 1U_0201_6.3V6K 1 2 CH101 1U_0201_6.3V6K @ 1 2 CC108 10U_0402_6.3V6M 1 2 CC62 10U_0402_6.3V6M 1 2 CH151 1U_0201_6.3V6K @ 1 2 CH132 1U_0201_6.3V6K @ 1 2 BGA1440 SKYLAKE_HALO 7 OF 14 UC1G SKYLAKE-H-CPU_BGA1440 @ VCC_126 P14 VCC_125 V31 VCC_123 V13 VCC_124 V14 VCC_122 U36 VCC_118 U32 VCC_117 U31 VCC_119 U33 VCC_120 U34 VCC_121 U35 VCC_113 T37 VCC_112 T36 VCC_116 U30 VCC_115 U29 VCC_107 T29 VCC_111 T35 VCC_110 T32 VCC_106 R38 VCC_103 R35 VCC_104 R36 VCC_102 R34 VCC_105 R37 VCC_101 R33 VCC_99 R31 VCC_98 R13 VCC_97 P36 VCC_100 R32 VCC_92 P31 VCC_91 P30 VCC_90 P29 VCC_82 Y30 VCC_83 Y31 VCC_81 Y29 VCC_78 W36 VCC_77 W35 VCC_76 W32 VCC_80 W38 VCC_73 W29 VCC_75 W31 VCC_74 W30 VCC_67 V35 VCC_68 V36 VCC_63 P13 VCC_61 N37 VCC_62 N38 VCC_60 N36 VCC_59 N35 VCC_58 N32 VCC_57 N31 VCC_56 N30 VCC_55 N14 VCC_54 N13 VCC_53 L13 VCC_50 AF38 VCC_51 K13 VCC_52 K14 VCC_49 AF37 VCC_48 AF36 VCC_47 AF35 VCC_46 AE38 VCC_45 AE37 VCC_31 AD32 VSS_SENSE AG38 VCC_SENSE AG37 VCC_27 AC36 VCC_28 AD13 VCC_29 AD14 VCC_30 AD31 VCC_32 AD33 VCC_33 AD34 VCC_34 AD35 VCC_35 AD36 VCC_36 AD37 VCC_37 AD38 VCC_38 AE13 VCC_39 AE14 VCC_40 AE30 VCC_41 AE31 VCC_42 AE32 VCC_44 AE36 VCC_43 AE35 VCC_109 T31 VCC_108 T30 VCC_89 L14 VCC_84 Y32 VCC_85 Y33 VCC_86 Y34 VCC_87 Y35 VCC_88 Y36 VCC_93 P32 VCC_94 P33 VCC_95 P34 VCC_96 P35 VCC_66 V34 VCC_64 V32 VCC_114 T38 VCC_79 W37 VCC_65 V33 VCC_72 W14 VCC_12 AB31 VCC_13 AB32 VCC_21 AC30 VCC_23 AC32 VCC_24 AC33 VCC_25 AC34 VCC_26 AC35 VCC_16 AB37 VCC_17 AB38 VCC_18 AC13 VCC_19 AC14 VCC_20 AC29 VCC_22 AC31 VCC_70 V38 VCC_69 V37 VCC_71 W13 VCC_11 AB30 VCC_10 AB29 VCC_9 AA38 VCC_8 AA37 VCC_6 AA35 VCC_5 AA34 VCC_4 AA33 VCC_3 AA32 VCC_2 AA31 VCC_1 AA13 VCC_7 AA36 VCC_15 AB36 VCC_14 AB35 CH190 1U_0201_6.3V6K 1 2 CC87 10U_0402_6.3V6M 1 2 RC39 0_0402_5% 1 2 BGA1440 SKYLAKE_HALO 8 OF 14 UC1H SKYLAKE-H-CPU_BGA1440 @ VCCGT_98 BB37 VCCGT_96 BB35 VCCGT_95 BB34 VCCGT_93 BB32 VCCGT_84 BA31 VCCGT_83 BA30 VCCGT_82 BA29 VCCGT_81 BA14 VCCGT_56 AV30 VCCGT_55 AV29 VCCGT_57 AV31 VCCGT_58 AV32 VCCGT_59 AV33 VCCGT_61 AV35 VCCGT_60 AV34 VCCGT_62 AV36 VCCGT_63 AW14 VCCGT_64 AW31 VCCGT_66 AW33 VCCGT_65 AW32 VCCGT_67 AW34 VCCGT_68 AW35 VCCGT_69 AW36 VCCGT_70 AW37 VCCGT_71 AW38 VCCGT_79 AY38 VCCGT_80 BA13 VCCGT_86 BA33 VCCGT_88 BA35 VCCGT_89 BA36 VCCGT_90 BB13 VCCGT_92 BB31 VCCGT_91 BB14 VCCGT_94 BB33 VCCGT_97 BB36 VCCGT_100 BC29 VCCGT_99 BB38 VCCGT_101 BC30 VCCGT_102 BC31 VCCGT_103 BC32 VCCGT_104 BC35 VCCGT_39 BC36 VCCGT_40 BC37 VCCGT_41 BC38 VCCGT_42 BD13 VCCGT_44 BD29 VCCGT_43 BD14 VCCGT_45 BD30 VCCGT_46 BD31 VCCGT_47 BD32 VCCGT_48 BD33 VCCGT_49 BD34 VCCGT_50 BD35 VCCGT_52 BE31 VCCGT_51 BD36 VCCGT_53 BE32 VCCGT_105 BE33 VCCGT_106 BE34 VCCGT_108 BE36 VCCGT_107 BE35 VCCGT_72 AY29 VCCGT_73 AY30 VCCGT_74 AY31 VCCGT_76 AY35 VCCGT_87 BA34 VCCGT_2 BG35 VCCGT_1 BG34 VCCGT_3 BG36 VCCGT_4 BH33 VCCGT_5 BH34 VCCGT_7 BH36 VCCGT_6 BH35 VCCGT_9 BH38 VCCGT_8 BH37 VCCGT_10 BJ37 VCCGT_12 BL36 VCCGT_11 BJ38 VCCGT_14 BM36 VCCGT_13 BL37 VCCGT_15 BM37 VCCGT_17 BN37 VCCGT_16 BN36 VCCGT_19 BP37 VCCGT_22 BT37 VCCGT_23 BE38 VCCGT_25 BF14 VCCGT_24 BF13 VCCGT_26 BF29 VCCGT_27 BF30 VCCGT_28 BF31 VCCGT_30 BF35 VCCGT_29 BF32 VCCGT_31 BF36 VCCGT_37 BG32 VCCGT_36 BG31 VCCGT_38 BG33 VCCGT_34 BG29 VCCGT_35 BG30 VCCGT_85 BA32 VCCGT_18 BN38 VCCGT_20 BP38 VCCGT_21 BR37 VCCGT_75 AY32 VCCGT_77 AY36 VCCGT_78 AY37 VCCGT_33 BF38 VCCGT_32 BF37 VCCGT_54 BE37 CH145 1U_0201_6.3V6K 1 2 CH203 1U_0201_6.3V6K 1 2 CH215 1U_0201_6.3V6K 1 2 CC99 10U_0402_6.3V6M 1 2 CH113 1U_0201_6.3V6K 1 2 CH102 1U_0201_6.3V6K 1 2 CH152 1U_0201_6.3V6K 1 2 CC109 10U_0402_6.3V6M 1 2 CC74 10U_0402_6.3V6M 1 2 CH157 1U_0201_6.3V6K @ 1 2 CH191 1U_0201_6.3V6K @ 1 2 CH167 1U_0201_6.3V6K 1 2 CH133 1U_0201_6.3V6K 1 2 CD76 33P_0402_50V8J RF_NS@ 1 2 CC86 10U_0402_6.3V6M 1 2 CH204 1U_0201_6.3V6K 1 2 CH180 1U_0201_6.3V6K 1 2 CH146 1U_0201_6.3V6K 1 2 CC101 10U_0402_6.3V6M 1 2 CH114 1U_0201_6.3V6K 1 2 CH103 1U_0201_6.3V6K @ 1 2 CH95 1U_0201_6.3V6K 1 2 CC110 10U_0402_6.3V6M 1 2 CH93 1U_0201_6.3V6K @ 1 2 CC75 10U_0402_6.3V6M 1 2 CH153 1U_0201_6.3V6K 1 2 CC131 10U_0402_6.3V6M 1 2 RC40 0_0402_5% 1 2 CH134 1U_0201_6.3V6K @ 1 2 CH192 1U_0201_6.3V6K 1 2 CH168 1U_0201_6.3V6K @ 1 2 CC89 10U_0402_6.3V6M 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A VCCIO_SENSE CRB place to CPU CRB place to CPU VCCSA_SENSE VDDQ DECOUPLING 1uF 3pcs 10uF 7pcs Near CPU MAX 2.8A MAX 11.1A MAX 5.5A 150mA 20mA 60mA 130mA For Merge VCCSA_SENSE_R VSSSA_SENSE_R VCCIO_SENSE_R VSSIO_SENSE_R VSSIO_SENSE_R VCCIO_SENSE_R VSSSA_SENSE_R VCCSA_SENSE_R VSS_IO_SEN 64 VCC_IO_SEN 64 VSSSA_SENSE 65 VCCSA_SENSE 65 +1.2V VCCSA VCCIO +1.2V VCCST VCCST +1.2V VCCSTG VCCIO VCCSA +1.2V VCCSA Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, BYPASS C 10 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, BYPASS C 10 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, BYPASS C 10 75 Friday, November 25, 2016 2015/02/26 2016/02/26 RC151 100_0402_1% 1 2 CD79 33P_0402_50V8J RF_NS@ 1 2 CC60 10U_0603_6.3V6M 1 2 CC137 10U_0603_6.3V6M 1 2 CH223 1U_0402_6.3V6K 1 2 CC63 22U_0603_6.3V6-M 1 2 TC54 PAD @ 1 CC58 10U_0603_6.3V6M 1 2 CC147 10U_0603_6.3V6M 1 2 TC74 PAD @ 1 CC54 10U_0603_6.3V6M 1 2 CH251 1U_0402_6.3V6K 1 2 CD80 33P_0402_50V8J RF_NS@ 1 2 CC139 10U_0603_6.3V6M 1 2 CH250 1U_0402_6.3V6K 1 2 TC53 PAD @ 1 TC58 PAD @ 1 RC155 100_0402_1% 1 2 CC138 10U_0603_6.3V6M 1 2 CC172 10U_0603_6.3V6M 1 2 CC65 22U_0603_6.3V6-M 1 2 RC150 0_0402_5% 1 2 CC148 10U_0603_6.3V6M 1 2 RC154 0_0402_5% @ 1 2 CC150 1U_0402_6.3V6K 1 2 CC141 10U_0603_6.3V6M 1 2 BGA1440 SKYLAKE_HALO 9 OF 14 UC1I SKYLAKE-H-CPU_BGA1440 @ VCCSTG_2 G30 VCCIO_19 J21 VCCIO_20 J26 VCCIO_21 J27 VCCIO_18 J20 VCCIO_16 J17 VCCIO_17 J19 VCCIO_14 J15 VCCIO_15 J16 VCCIO_13 H27 VCCIO_12 H26 VCCIO_11 H21 VCCIO_9 H19 VCCIO_10 H20 VCCIO_8 H17 VCCIO_7 H16 VCCIO_6 H15 VCCIO_4 G19 VCCIO_5 G21 VCCIO_3 G17 VCCIO_2 G15 VCCIO_1 AG12 VCCSA_20 M34 VCCSA_19 M33 VCCSA_18 M32 VCCSA_17 M31 VCCSA_16 M30 VCCSA_14 L38 VCCSA_15 M29 VCCSA_13 L37 VCCSA_12 L36 VCCSA_10 L32 VCCSA_11 L35 VCCSA_9 L31 VCCSA_8 K35 VCCSA_7 K34 VCCSA_2 K29 VCCSA_1 J30 VCCIO_SENSE H14 VSSIO_SENSE J14 VSSSA_SENSE M37 VCCSA_SENSE M38 VCCPLL_2 J28 VCCPLL_1 H28 VDDQ_7 AJ12 VDDQ_6 AG9 VDDQ_5 AG5 VDDQ_4 AF6 VDDQ_3 AF5 VDDQ_2 AE12 VDDQ_1 AA6 VDDQ_8 AL11 VDDQ_9 AP6 VDDQ_10 AP7 VDDQ_12 AR6 VDDQ_11 AR12 VCCSA_6 K33 VCCSA_5 K32 VCCSA_4 K31 VCCSA_3 K30 VDDQ_13 AT12 VDDQ_15 AY6 VDDQ_14 AW6 VDDQ_16 J5 VDDQ_17 J6 VDDQ_18 K12 VDDQ_19 K6 VDDQ_20 L12 VDDQ_21 L6 VDDQ_22 R6 VDDQ_23 T6 VDDQ_24 W6 VDDQC Y12 VCCPLL_OC_1 BH13 VCCST H30 VCCSTG_1 H29 VCCPLL_OC_2 G11 VCCSA_22 M36 VCCSA_21 M35 TC75 PAD @ 1 RC148 0_0402_5% 1 2 CC140 10U_0603_6.3V6M 1 2 CC149 10U_0603_6.3V6M 1 2 RC152 0_0402_5% @ 1 2 CC136 10U_0603_6.3V6M 1 2 TC76 PAD @ 1 CC59 10U_0603_6.3V6M 1 2 CC142 10U_0603_6.3V6M 1 2 TC45 PAD @ 1 BGA1440 SKYLAKE_HALO 10 OF 14 UC1J SKYLAKE-H-CPU_BGA1440 @ OPC_RCOMP BT29 VCCOPC_6 BK20 VCCOPC_7 BL16 VCCOPC_9 BL18 VCCOPC_8 BL17 VCCOPC_10 BL19 VCCOPC_13 BM17 VCCOPC_12 BL21 RSVD_3 BJ27 RSVD_4 BK23 RSVD_6 BK27 RSVD_7 BL23 RSVD_9 BL25 RSVD_12 BL28 RSVD_11 BL27 VCCEOPIO_1 BP15 VCCEOPIO_3 BT15 RSVD_18 BT16 RSVD_17 BR16 RSVD_16 BP16 RSVD_19 BP17 VSSEOPIO_SENSE BM15 VCCEOPIO_SENSE BN15 VCC_OPC_1P8_1 BM14 VCC_OPC_1P8_2 BL14 RSVD_20 BN16 RSVD_22 BJ36 RSVD_21 BJ35 ZVM# AT13 MSM# AW13 MSM2# AY13 ZVM2# AU13 OPCE_RCOMP BR25 OPCE_RCOMP2 BP25 RSVD_15 BM22 RSVD_14 BL22 VSSOPC_SENSE BM16 RSVD_13 BM24 VCCOPC_2 BJ19 VCCOPC_1 BJ17 VCCOPC_3 BJ20 VCCOPC_4 BK17 VCCOPC_5 BK19 VCCOPC_11 BL20 VCCOPC_14 BN17 RSVD_1 BJ23 RSVD_2 BJ26 RSVD_5 BK26 RSVD_8 BL24 RSVD_10 BL26 VCCOPC_SENSE BL15 VCCEOPIO_2 BR15 CC57 10U_0603_6.3V6M 1 2 CC66 22U_0603_6.3V6-M 1 2 RC149 100_0402_1% 1 2 TC47 PAD @ 1 CC56 10U_0603_6.3V6M 1 2 CC55 10U_0603_6.3V6M 1 2 TC49 PAD @ 1 CH252 1U_0402_6.3V6K 1 2 RC153 100_0402_1% 1 2 TC48 PAD @ 1 CC64 22U_0603_6.3V6-M 1 2 CC53 10U_0603_6.3V6M 1 2 CH221 1U_0402_6.3V6K 1 2 TC51 PAD @ 1 CC51 10U_0603_6.3V6M 1 2 CH242 1U_0402_6.3V6K 1 2 CC52 10U_0603_6.3V6M 1 2 CH249 1U_0402_6.3V6K 1 2 CH222 1U_0402_6.3V6K 1 2 TC52 PAD @ 1 TC56 PAD @ 1 WWW.AliSaler.Com
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, VSS C 11 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, VSS C 11 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, VSS C 11 75 Friday, November 25, 2016 2015/02/26 2016/02/26 SKYLAKE_HALO BGA1440 13 OF 14 UC1M SKYLAKE-H-CPU_BGA1440 @ VSS_300 BB4 VSS_301 BB3 VSS_302 BB2 VSS_303 BB1 VSS_304 BA38 VSS_305 BA37 VSS_306 BA12 VSS_307 BA11 VSS_308 BA10 VSS_309 BA9 VSS_310 BA8 VSS_311 BA7 VSS_312 BA6 NCTFVSS_8 B37 VSS_313 B9 NCTFVSS_9 B3 VSS_314 AY34 VSS_315 AY33 VSS_316 AY14 VSS_317 AY12 VSS_318 AW30 VSS_319 AW29 VSS_320 AW12 VSS_321 AW5 VSS_322 AW4 VSS_323 AW3 VSS_324 AW2 VSS_325 AW1 VSS_326 AV38 VSS_327 AV37 VSS_328 AU34 VSS_329 AU33 VSS_330 AU12 VSS_331 AU11 VSS_332 AU10 VSS_333 AU9 VSS_334 AU8 VSS_335 AU7 VSS_336 AU6 VSS_337 AT30 VSS_338 AT29 VSS_339 AT6 VSS_340 AR38 VSS_341 AR37 VSS_342 AR14 VSS_343 AR13 VSS_344 AR5 VSS_345 AR4 VSS_346 AR3 VSS_347 AR2 VSS_348 AR1 VSS_349 AP34 VSS_350 AP33 VSS_351 AP12 VSS_352 AP11 VSS_353 AP10 VSS_354 AP9 VSS_355 AP8 VSS_356 AN30 VSS_357 AN29 VSS_358 AN12 VSS_359 AN6 VSS_360 AN5 VSS_361 AM38 VSS_362 AM37 VSS_363 AM12 VSS_364 AM5 VSS_365 AM4 VSS_366 AM3 VSS_367 AM2 VSS_368 AM1 VSS_369 AL34 VSS_370 AL33 VSS_371 AL14 VSS_372 AL12 VSS_373 AL10 VSS_374 AL9 VSS_375 AL8 VSS_376 AL7 VSS_377 AL4 VSS_378 AK30 VSS_379 AK29 VSS_380 AK4 VSS_381 AJ38 VSS_382 AJ37 VSS_383 AJ6 VSS_384 AJ5 VSS_385 AJ4 VSS_386 AJ3 VSS_387 AJ2 VSS_388 AJ1 VSS_389 AH34 VSS_390 AH33 VSS_391 AH12 VSS_392 AH6 VSS_393 AG30 VSS_394 AG29 VSS_395 AG11 VSS_396 AG10 VSS_397 AG8 VSS_398 AG7 VSS_399 AG6 VSS_400 AF14 VSS_401 AF13 VSS_402 AF12 VSS_403 AF4 VSS_404 AF3 VSS_405 AF2 VSS_406 AF1 VSS_407 AE34 VSS_408 AE33 VSS_409 AE6 VSS_410 AD30 VSS_411 AD29 VSS_412 AD12 VSS_413 AD11 VSS_414 AD10 VSS_415 AD9 VSS_416 AD8 VSS_417 AD7 VSS_418 AD6 VSS_419 AC38 VSS_420 AC37 VSS_421 AC12 VSS_422 AC6 VSS_423 AC5 VSS_424 AC4 VSS_425 AC3 VSS_426 AC2 VSS_427 AC1 VSS_428 AB34 VSS_429 AB33 VSS_430 AB6 VSS_431 AA30 VSS_432 AA29 VSS_433 AA12 NCTFVSS_10 A34 VSS_434 A30 VSS_435 A28 VSS_436 A26 VSS_437 A24 VSS_438 A22 VSS_439 A20 VSS_440 A18 VSS_441 A16 VSS_442 A14 VSS_443 A12 VSS_444 A10 VSS_445 A9 VSS_446 A6 NCTFVSS_11 A4 NCTFVSS_12 A3 SKYLAKE_HALO BGA1440 6 OF 14 UC1F SKYLAKE-H-CPU_BGA1440 @ VSS_106 G9 VSS_111 F36 VSS_116 F23 VSS_122 F11 VSS_5 Y11 VSS_10 W34 VSS_20 V12 VSS_15 W3 VSS_24 T34 VSS_34 T5 VSS_29 T11 VSS_44 P12 VSS_39 R30 VSS_49 N11 VSS_59 N1 VSS_54 N6 VSS_65 L33 VSS_70 K10 VSS_77 K2 VSS_82 J25 VSS_87 J4 VSS_92 H18 VSS_107 G8 VSS_117 F21 VSS_123 F9 VSS_128 F2 VSS_142 D16 VSS_133 E4 VSS_147 D6 VSS_150 C31 VSS_139 D22 VSS_144 D12 VSS_130 E35 VSS_125 F5 VSS_120 F15 VSS_79 J36 VSS_72 K8 VSS_67 L29 VSS_61 M13 VSS_51 N9 VSS_56 N4 VSS_46 N34 VSS_41 R12 VSS_36 T3 VSS_26 T14 VSS_17 W1 VSS_153 U38 VSS_12 W12 VSS_2 Y37 VSS_7 Y9 VSS_146 D9 VSS_152 C27 VSS_91 H22 VSS_96 G26 VSS_101 G18 VSS_6 Y10 VSS_11 W33 VSS_1 Y38 VSS_16 W2 VSS_35 T4 VSS_30 T10 VSS_40 R29 VSS_45 P6 VSS_50 N10 VSS_60 M14 VSS_55 N5 VSS_78 K1 VSS_83 J22 VSS_88 H35 VSS_93 H12 VSS_98 G23 VSS_103 G14 VSS_108 G6 VSS_129 E38 VSS_134 D33 VSS_143 D14 VSS_148 D3 VSS_86 J7 VSS_64 L34 VSS_76 K3 VSS_81 J32 VSS_69 K11 VSS_58 N2 VSS_53 N7 VSS_48 N12 VSS_38 T1 VSS_43 P37 VSS_33 T7 VSS_23 U6 VSS_9 Y7 VSS_14 W4 VSS_4 Y13 VSS_140 D20 VSS_131 E34 VSS_151 C29 VSS_145 D10 VSS_126 F4 VSS_110 G4 VSS_105 G10 VSS_121 F13 VSS_115 F25 VSS_100 G20 VSS_85 J10 VSS_80 J33 VSS_95 G28 VSS_90 H25 VSS_74 K5 VSS_47 N33 VSS_52 N8 VSS_63 M6 VSS_68 K38 VSS_57 N3 VSS_22 U37 VSS_27 T13 VSS_37 T2 VSS_42 P38 VSS_32 T8 VSS_8 Y8 VSS_13 W5 VSS_18 V30 VSS_3 Y14 NCTFVSS_1 D38 VSS_119 F17 VSS_75 K4 VSS_62 M12 VSS_73 K7 VSS_149 C37 VSS_138 D24 VSS_137 D26 VSS_135 D30 VSS_136 D28 VSS_19 V29 VSS_28 T12 VSS_25 T33 VSS_21 V6 VSS_124 F8 VSS_118 F19 VSS_113 F29 VSS_66 L30 VSS_71 K9 VSS_97 G24 VSS_102 G16 VSS_112 F31 VSS_114 F27 VSS_109 G5 VSS_104 G12 VSS_99 G22 VSS_94 H11 VSS_89 H32 VSS_84 J18 VSS_31 T9 VSS_127 F3 VSS_132 E9 VSS_141 D18 SKYLAKE_HALO BGA1440 12 OF 14 UC1L SKYLAKE-H-CPU_BGA1440 @ VSS_239 C25 VSS_240 C23 VSS_241 C21 VSS_242 C19 VSS_154 C17 VSS_243 C15 VSS_155 C13 VSS_244 C11 VSS_156 C9 VSS_245 C8 VSS_246 C5 NCTFVSS_2 C2 NCTFVSS_3 BT36 NCTFVSS_4 BT35 VSS_157 BT32 VSS_158 BT26 VSS_159 BT24 VSS_160 BT21 VSS_161 BT18 VSS_162 BT14 VSS_163 BT12 VSS_164 BT9 VSS_165 BT5 NCTFVSS_5 BT4 NCTFVSS_6 BT3 NCTFVSS_7 BR38 VSS_166 BR36 VSS_167 BR34 VSS_168 BR29 VSS_169 BR26 VSS_170 BR24 VSS_171 BR21 VSS_172 BR18 VSS_173 BR14 VSS_174 BR12 VSS_175 BR7 VSS_176 BP34 VSS_177 BP33 VSS_178 BP29 VSS_179 BP26 VSS_180 BP24 VSS_181 BP21 VSS_182 BP18 VSS_183 BP14 VSS_184 BP12 VSS_185 BP7 VSS_186 BN34 VSS_187 BN31 VSS_188 BN30 VSS_189 BN29 VSS_190 BN24 VSS_191 BN21 VSS_192 BN20 VSS_193 BN19 VSS_194 BN18 VSS_195 BN14 VSS_196 BN12 VSS_197 BN9 VSS_198 BN7 VSS_199 BN4 VSS_200 BN2 VSS_201 BM38 VSS_202 BM35 VSS_247 BM29 VSS_203 BM28 VSS_204 BM27 VSS_205 BM26 VSS_248 BM25 VSS_206 BM23 VSS_207 BM21 VSS_249 BM18 VSS_208 BM13 VSS_209 BM12 VSS_250 BM11 VSS_210 BM9 VSS_251 BM8 VSS_252 BM7 VSS_211 BM6 VSS_253 BM5 VSS_254 BM3 VSS_212 BM2 VSS_255 BL38 VSS_256 BL35 VSS_213 BL29 VSS_257 BL13 VSS_258 BL6 VSS_214 BK29 VSS_259 BK25 VSS_260 BK22 VSS_215 BK15 VSS_216 BK14 VSS_261 BK13 VSS_262 BK6 VSS_217 BJ32 VSS_218 BJ31 VSS_263 BJ30 VSS_264 BJ29 VSS_219 BJ25 VSS_220 BJ22 VSS_265 BJ15 VSS_266 BJ12 VSS_221 BH14 VSS_222 BH12 VSS_267 BH11 VSS_268 BH10 VSS_223 BH9 VSS_224 BH8 VSS_269 BH7 VSS_270 BH6 VSS_225 BH5 VSS_226 BH4 VSS_271 BH3 VSS_272 BH2 VSS_227 BH1 VSS_228 BG38 VSS_273 BG37 VSS_274 BG14 VSS_229 BG13 VSS_230 BG12 VSS_275 BG6 VSS_276 BF34 VSS_231 BF33 VSS_232 BF12 VSS_277 BF6 VSS_278 BE30 VSS_233 BE29 VSS_234 BE6 VSS_279 BE5 VSS_280 BE4 VSS_281 BE3 VSS_282 BE2 VSS_283 BE1 VSS_284 BD38 VSS_285 BD37 VSS_286 BD12 VSS_287 BD11 VSS_288 BD10 VSS_235 BD9 VSS_289 BD8 VSS_290 BD7 VSS_291 BD6 VSS_236 BC34 VSS_292 BC33 VSS_293 BC14 VSS_294 BC13 VSS_237 BC12 VSS_295 BC6 VSS_296 BB30 VSS_297 BB29 VSS_238 BB12 VSS_298 BB6 VSS_299 BB5
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Layout Note: Place near DIMM Layout Note: Place near DIMM DDR4 SO-DIMM A Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket Change RD2 to 0ohm jump For EMC SPD Address = 0H Near JDDRL1 Change JDDRL1 from Foxconn to ARGOSY HLZ SDV 20160510 Change DDR4 220u to B2 HLZ SVD 0527 MAX 3A MAX 0.5A MAX 0.5A Change CD81 & CD82 from @ to stuff based on RF requirement HLZ SIT 0924 DDRA_CLK0 DDRA_CLK0# DDRA_CS0# DDRA_CS1# DDRA_CKE0 DDRA_ODT0 DDRA_ODT1 DDRA_MA1 DDRA_MA3 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA12 DDRA_MA11 DDRA_MA14_WE# DDRA_BG0 DDRA_BG1 DDRA_BA1 DDRA_ACT# DDRA_PARITY DDRA_DQS#0 DDRA_DQS0 DDRA_DQS#1 DDRA_DQS1 DDRA_DQS#2 DDRA_DQS2 DDRA_DQS3 DDRA_DQS#3 DDRA_DQS#4 DDRA_DQS4 DDRA_DQS6 DDRA_DQS#6 DDRA_DQ4 DDRA_DQ0 DDRA_DQ7 DDRA_DQ3 DDRA_DQ13 DDRA_DQ12 DDRA_DQ15 DDRA_DQ14 DDRA_DQ21 DDRA_DQ20 DDRA_DQ22 DDRA_DQ18 DDRA_DQ29 DDRA_DQ28 DDRA_DQ27 DDRA_DQ30 DDRA_DQ24 DDRA_DQ23 DDRA_DQ19 DDRA_DQ17 DDRA_DQ16 DDRA_DQ11 DDRA_DQ10 DDRA_DQ8 DDRA_DQ2 DDRA_DQ9 DDRA_DQ6 DDRA_DQ5 DDRA_DQ1 DDRA_DQ33 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ44 DDRA_DQ41 DDRA_DQ43 DDRA_DQ46 DDRA_DQ50 DDRA_DQ52 DDRA_DQ54 DDRA_DQ51 DDRA_DQ57 DDRA_DQ61 DDRA_DQ62 DDRA_DQ58 +VREF_CA_DIMMA PCH_DRAMRST# SMB_CLK_S3 DDRA_VDDSPD DDRA_SA0 DDRA_SA1 DDRA_SA2 DDRA_MA4 DDRA_MA5 DDRA_ALERT# DDRA_CKE1 DDRA_DQ25 DDRA_DQ26 DDRA_DQ31 +VREF_CA_DIMMA DDRA_MA13 DDRA_CLK1 DDRA_CLK1# DDRA_MA2 DDRA_MA0 DDRA_MA10_AP DDRA_MA16_RAS# DDRA_DQS#7 DDRA_DQS7 DDRA_DQ55 DDRA_DQ56 DDRA_DQ60 DDRA_DQ63 DDRA_DQ45 DDRA_DQ47 DDRA_DQ42 DDRA_DQ48 DDRA_DQ49 DDRA_DQ53 DDRA_DQ36 DDRA_DQ32 DDRA_DQ35 DDRA_DQ34 DDRA_DQ40 SMB_DATA_S3 DDRA_SA1 DDRA_SA0 DDRA_SA2 DDRA_BA0 DDRA_MA15_CAS# DDRA_DQ59 DDRA_DQS#5 DDRA_DQS5 DDRA_EVENT# DDRA_EVENT# DDRA_CLK0 7 DDRA_CLK0# 7 DDRA_CLK1 7 DDRA_CLK1# 7 DDRA_CS0# 7 DDRA_CS1# 7 DDRA_CKE0 7 DDRA_CKE1 7 DDRA_ODT0 7 DDRA_ODT1 7 DDRA_MA0 7 DDRA_MA1 7 DDRA_MA2 7 DDRA_MA3 7 DDRA_MA10_AP 7 DDRA_MA5 7 DDRA_MA4 7 DDRA_MA9 7 DDRA_MA8 7 DDRA_MA6 7 DDRA_MA7 7 DDRA_MA12 7 DDRA_MA11 7 DDRA_MA13 7 DDRA_MA14_WE# 7 DDRA_MA16_RAS# 7 DDRA_MA15_CAS# 7 DDRA_BG0 7 DDRA_BG1 7 DDRA_BA1 7 DDRA_BA0 7 DDRA_PARITY 7 DDRA_ALERT# 7 DDRA_DQS#0 7 DDRA_DQS0 7 DDRA_DQS#2 7 DDRA_DQS2 7 DDRA_DQS#1 7 DDRA_DQS1 7 DDRA_DQS#3 7 DDRA_DQS3 7 DDRA_DQS#5 7 DDRA_DQS5 7 DDRA_DQS#7 7 DDRA_DQS7 7 DDRA_DQS#6 7 DDRA_DQS6 7 DDRA_DQS#4 7 DDRA_DQS4 7 DDRA_DQ4 7 DDRA_DQ0 7 DDRA_DQ7 7 DDRA_DQ3 7 DDRA_DQ13 7 DDRA_DQ12 7 DDRA_DQ15 7 DDRA_DQ14 7 DDRA_DQ21 7 DDRA_DQ20 7 DDRA_DQ22 7 DDRA_DQ18 7 DDRA_DQ29 7 DDRA_DQ28 7 DDRA_DQ27 7 DDRA_DQ30 7 DDRA_DQ33 7 DDRA_DQ37 7 DDRA_DQ38 7 DDRA_DQ39 7 DDRA_DQ44 7 DDRA_DQ41 7 DDRA_DQ43 7 DDRA_DQ46 7 DDRA_DQ50 7 DDRA_DQ52 7 DDRA_DQ54 7 DDRA_DQ51 7 DDRA_DQ57 7 DDRA_DQ61 7 DDRA_DQ62 7 DDRA_DQ58 7 DDRA_DQ1 7 DDRA_DQ5 7 DDRA_DQ6 7 DDRA_DQ2 7 DDRA_DQ9 7 DDRA_DQ8 7 DDRA_DQ10 7 DDRA_DQ11 7 DDRA_DQ16 7 DDRA_DQ17 7 DDRA_DQ19 7 DDRA_DQ23 7 DDRA_DQ24 7 DDRA_DQ36 7 DDRA_DQ32 7 DDRA_DQ35 7 DDRA_DQ34 7 DDRA_DQ40 7 DDRA_DQ45 7 DDRA_DQ47 7 DDRA_DQ42 7 DDRA_DQ48 7 DDRA_DQ49 7 DDRA_DQ53 7 DDRA_DQ55 7 DDRA_DQ56 7 DDRA_DQ60 7 DDRA_DQ59 7 DDRA_DQ63 7 PCH_DRAMRST# 13,16 SMB_DATA_S3 13,16,45,50 SMB_CLK_S3 13,16,45,50 DDRA_ACT# 7 DDRA_DQ25 7 DDRA_DQ26 7 DDRA_DQ31 7 +0.6VS +1.2V +1.2V +VREF_CA_DIMMA_R +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +3VS +2.5V +2.5V +0.6VS +3VS +3VS +3VS +1.2V Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM A C 12 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM A C 12 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM A C 12 75 Friday, November 25, 2016 2015/02/26 2016/02/26 RD26 0_0402_5% @ 1 2 CD8 10U_0603_6.3V6M 1 2 CD16 1U_0402_6.3V6K 1 2 CD15 1U_0402_6.3V6K 1 2 RD1 1K_0402_1% 1 2 CD25 10U_0402_6.3V6M 1 2 CD68 1U_0402_6.3V6K 1 2 CD14 10U_0603_6.3V6M 1 2 CD28 .1U_0402_10V6-K 1 2 CD11 10U_0603_6.3V6M 1 2 CD10 10U_0603_6.3V6M 1 2 CD17 1U_0402_6.3V6K 1 2 CD3 .1U_0402_10V6-K 1 2 CD27 2.2U_0603_6.3V6K 1 2 RD5 240_0402_5% 1 2 CD7 10U_0603_6.3V6M 1 2 CD97 4.7U_0603_6.3V6K EMC_NS@ 1 2 CD18 1U_0402_6.3V6K 1 2 CD2 2.2U_0603_6.3V6K 1 2 RD20 0_0402_5% 1 2 CD81 33P_0402_50V8J RF@ 1 2 RD22 0_0402_5% @ 1 2 CD59 1U_0402_6.3V6K 1 2 CD1 0.022U_0402_16V7-K 1 2 CD82 33P_0402_50V8J RF@ 1 2 CD98 4.7U_0603_6.3V6K EMC_NS@ 1 2 CD96 0.1U_0402_10V7K EMC_NS@ 1 2 RD23 0_0402_5% 1 2 CD9 10U_0603_6.3V6M 1 2 RD3 1K_0402_1% 1 2 CD60 1U_0402_6.3V6K 1 2 CD13 10U_0603_6.3V6M 1 2 CD12 10U_0603_6.3V6M 1 2 CD21 .1U_0402_10V6-K 1 2 RD25 0_0402_5% 1 2 CD65 1U_0402_6.3V6K 1 2 RVS JDDRL1A ARGOS_D4AR0-26001-1P52 ME@ VSS_1 1 DQ5 3 VSS_3 5 DQ1 7 VSS_5 9 DQS0_C 11 DQS0_t 13 VSS_8 15 DQ7 17 VSS_10 19 DQ3 21 VSS_12 23 DQ13 25 VSS_14 27 DQ9 29 VSS_16 31 DM1_n/DBl1_n/NC 33 VSS_17 35 DQ15 37 VSS_19 39 DQ10 41 VSS_21 43 DQ21 45 VSS_23 47 DQ17 49 VSS_25 51 DQS2_c 53 DQS2_t 55 VSS_28 57 DQ23 59 VSS_30 61 DQ19 63 VSS_32 65 DQ29 67 VSS_34 69 DQ25 71 VSS_36 73 DM3_n/DBl3_n/NC 75 VSS_37 77 DQ30 79 VSS_39 81 VSS_2 2 DQ4 4 VSS_4 6 DQ0 8 VSS_6 10 DM0_n/DBI0_n/NC 12 VSS_7 14 DQ6 16 VSS_9 18 DQ2 20 VSS_11 22 DQ12 24 VSS_13 26 DQ8 28 VSS_15 30 DQS1_c 32 DQS1_t 34 VSS_18 36 DQ14 38 VSS_20 40 DQ11 42 VSS_22 44 DQ20 46 VSS_24 48 DQ16 50 VSS_26 52 DM2_n/DBl2_n/NC 54 VSS_27 56 DQ22 58 VSS_29 60 DQ18 62 VSS_31 64 DQ28 66 VSS_33 68 DQ24 70 VSS_35 72 DQS3_c 74 DQS3_t 76 VSS_38 78 DQ31 80 VSS_40 82 DQ26 83 VSS_41 85 CB5/NC 87 VSS_43 89 CB1/NC 91 VSS_45 93 DQS8_c 95 DQS8_t 97 VSS_48 99 CB2/NC 101 VSS_50 103 CB3/NC 105 VSS_52 107 CKE0 109 VDD_1 111 BG1 113 BG0 115 VDD_3 117 A12 119 A9 121 VDD_5 123 A8 125 A6 127 VDD_7 129 DQ27 84 VSS_42 86 CB4/NC 88 VSS_44 90 CB0/NC 92 VSS_46 94 DBI8_n/DBI_n/NC 96 VSS_47 98 CB6/NC 100 VSS_49 102 CB7/NC 104 VSS_51 106 RESET_n 108 CKE1 110 VDD_2 112 ACT_n 114 ALERT_n 116 VDD_4 118 A11 120 A7 122 VDD_6 124 A5 126 A4 128 VDD_8 130 CD57 10U_0402_6.3V6M 1 2 CD95 0.1U_0402_10V7K EMC_NS@ 1 2 RD27 0_0402_5% 1 2 CD66 1U_0402_6.3V6K 1 2 CD58 10U_0402_6.3V6M 1 2 RVS JDDRL1B ARGOS_D4AR0-26001-1P52 ME@ A3 131 A1 133 VDD_9 135 CK0_t 137 CK0_c 139 VDD_11 141 Parity 143 BA1 145 VDD_13 147 CS0_n 149 WE_n/A14 151 VDD_15 153 ODT0 155 CS1_n 157 VDD_17 159 ODT1 161 VDD_19 163 C1/CS3_n/NC 165 VSS_53 167 DQ37 169 VSS_55 171 DQ33 173 VSS_57 175 DQS4_c 177 DQS4_t 179 VSS_60 181 DQ38 183 VSS_62 185 DQ34 187 VSS_64 189 DQ44 191 VSS_66 193 DQ40 195 VSS_68 197 DM5_n/DBl5_n/NC 199 VSS_69 201 DQ46 203 VSS_71 205 DQ42 207 VSS_73 209 DQ52 211 VSS_75 213 DQ49 215 VSS_77 217 DQS6_c 219 DQS6_t 221 VSS_80 223 DQ55 225 VSS_82 227 DQ51 229 VSS_84 231 DQ61 233 VSS_86 235 DQ56 237 VSS_88 239 DM7_n/DBl7_n/NC 241 VSS_89 243 DQ62 245 VSS_91 247 DQ58 249 VSS_93 251 SCL 253 VDDSPD 255 VPP_1 257 VPP_2 259 A2 132 EVENT_n/NF 134 VDD_10 136 CK1_t/NF 138 CK1_c/NF 140 VDD_12 142 A0 144 A10/AP 146 VDD_14 148 BA0 150 RAS_n/A16 152 VDD_16 154 CAS_n/A15 156 A13 158 VDD_18 160 C0/CS2_n/NC 162 VREFCA 164 SA2 166 VSS_54 168 DQ36 170 VSS_56 172 DQ32 174 VSS_58 176 DM4_n/DBl4_n/NC 178 VSS_59 180 DQ39 182 VSS_61 184 DQ35 186 VSS_63 188 DQ45 190 VSS_65 192 DQ41 194 VSS_67 196 DQS5_c 198 DQS5_t 200 DQ47 204 VSS_70 202 DQ43 208 VSS_72 206 VSS_74 210 DQ53 212 VSS_76 214 DQ48 216 VSS_78 218 DQ54 224 VSS_79 222 DQ50 228 VSS_81 226 DQ60 232 VSS_83 230 DQ57 236 DM6_n/DBl6_n/NC 220 VSS_85 234 DQ63 246 VSS_87 238 DQ59 250 VSS_92 248 DQS7_c 240 DQS7_t 242 VSS_90 244 VSS_94 252 SDA 254 SA0 256 SA1 260 Vtt 258 GND_1 261 GND_2 262 RD18 0_0402_5% 1 2 CD23 1U_0402_6.3V6K 1 2 RD24 0_0402_5% @ 1 2 CD24 10U_0402_6.3V6M 1 2 + CD19 220U_B2_6.3VM_R25M @ 1 2 RD2 2_0402_5% 1 2 CD69 0.1U_0402_10V7K @ 1 2 CD67 1U_0402_6.3V6K 1 2 RD4 24.9_0402_1% 1 2 WWW.AliSaler.Com
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Layout Note: Place near DIMM Layout Note: Place near DIMM Change RD12 to 0ohm jump For EMC CAD Note: Trace width= 20 mil, Spcing=20 mils DDR4 SO-DIMM B SPD Address = 2H Near JDDRH1 Change JDDRH1 from Foxconn to ARGOSY and RVS to STD HLZ SDV 20160510 MAX 3A MAX 0.5A MAX 0.5A Change CD83 & CD84 from @ to stuff based on RF requirement HLZ SIT 0924 Add CD4 based on RF requirement HLZ SIT 0924 DDRB_CLK0 DDRB_CLK0# DDRB_CS0# DDRB_CS1# DDRB_CKE0 DDRB_CKE1 DDRB_ODT0 DDRB_ODT1 DDRB_MA1 DDRB_MA3 DDRB_BA1 DDRB_MA6 DDRB_MA8 DDRB_MA9 DDRB_MA12 DDRB_BG1 DDRB_BG0 DDRB_MA4 DDRB_MA5 DDRB_MA7 DDRB_MA11 DDRB_ACT# DDRB_MA14_WE# DDRB_PARITY DDRB_ALERT# DDRB_DQS0 DDRB_DQS#0 DDRB_DQS#1 DDRB_DQS1 DDRB_DQS#2 DDRB_DQS2 DDRB_DQS#3 DDRB_DQS3 DDRB_DQS#4 DDRB_DQS4 DDRB_DQS#6 DDRB_DQS6 DDRB_DQ2 DDRB_DQ5 DDRB_DQ4 DDRB_DQ0 DDRB_DQ6 DDRB_DQ3 DDRB_DQ10 DDRB_DQ14 DDRB_DQ12 DDRB_DQ22 DDRB_DQ18 DDRB_DQ20 DDRB_DQ19 DDRB_DQ27 DDRB_DQ31 DDRB_DQ30 DDRB_DQ24 DDRB_DQ1 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ11 DDRB_DQ15 DDRB_DQ17 DDRB_DQ16 DDRB_DQ23 DDRB_DQ21 DDRB_DQ28 DDRB_DQ25 DDRB_DQ26 DDRB_DQ29 DDRB_DQ38 DDRB_DQ35 DDRB_DQ33 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ46 DDRB_DQ52 DDRB_DQ48 DDRB_DQ50 DDRB_DQ51 DDRB_DQ57 DDRB_DQ61 DDRB_DQ56 DDRB_DQ60 DDRB_DQ32 +VREF_CA_DIMMB PCH_DRAMRST# SMB_CLK_S3 DDRB_SA0 DDRB_SA1 DDRB_SA2 DDRB_DQ13 DDRB_VDDSPD DDRB_CLK1 DDRB_CLK1# DDRB_MA13 DDRB_MA15_CAS# DDRB_MA16_RAS# DDRB_MA10_AP DDRB_MA0 DDRB_BA0 DDRB_DQS#5 DDRB_DQS5 DDRB_DQS7 DDRB_DQS#7 DDRB_DQ34 DDRB_DQ55 DDRB_DQ47 DDRB_DQ45 DDRB_DQ44 DDRB_DQ37 DDRB_DQ36 DDRB_DQ39 DDRB_DQ63 DDRB_DQ58 DDRB_DQ62 DDRB_DQ59 DDRB_DQ49 DDRB_DQ53 +VREF_CA_DIMMB SMB_DATA_S3 DDRB_SA2 DDRB_SA1 DDRB_SA0 DDRB_DQ43 DDRB_DQ54 DDRB_MA2 DDRB_EVENT# DDRB_EVENT# DDRB_CLK0 7 DDRB_CLK0# 7 DDRB_CLK1 7 DDRB_CLK1# 7 DDRB_CS0# 7 DDRB_CS1# 7 DDRB_CKE0 7 DDRB_CKE1 7 DDRB_ODT0 7 DDRB_ODT1 7 DDRB_MA2 7 DDRB_MA0 7 DDRB_MA10_AP 7 DDRB_MA16_RAS# 7 DDRB_MA15_CAS# 7 DDRB_MA1 7 DDRB_MA3 7 DDRB_BA1 7 DDRB_BG1 7 DDRB_BG0 7 DDRB_MA12 7 DDRB_MA9 7 DDRB_MA8 7 DDRB_MA6 7 DDRB_MA11 7 DDRB_MA7 7 DDRB_MA5 7 DDRB_MA4 7 DDRB_ACT# 7 DDRB_BA0 7 DDRB_MA14_WE# 7 DDRB_PARITY 7 DDRB_ALERT# 7 DDRB_DQS#0 7 DDRB_DQS0 7 DDRB_DQS#2 7 DDRB_DQS2 7 DDRB_DQS#4 7 DDRB_DQS4 7 DDRB_DQS#6 7 DDRB_DQS6 7 DDRB_DQS#1 7 DDRB_DQS1 7 DDRB_DQS#3 7 DDRB_DQS3 7 DDRB_DQS#5 7 DDRB_DQS5 7 DDRB_DQS#7 7 DDRB_DQS7 7 DDRB_DQ2 7 DDRB_DQ5 7 DDRB_DQ6 7 DDRB_DQ3 7 DDRB_DQ10 7 DDRB_DQ14 7 DDRB_DQ12 7 DDRB_DQ13 7 DDRB_DQ22 7 DDRB_DQ18 7 DDRB_DQ20 7 DDRB_DQ19 7 DDRB_DQ27 7 DDRB_DQ31 7 DDRB_DQ30 7 DDRB_DQ24 7 DDRB_DQ4 7 DDRB_DQ0 7 DDRB_DQ1 7 DDRB_DQ7 7 DDRB_DQ8 7 DDRB_DQ9 7 DDRB_DQ11 7 DDRB_DQ15 7 DDRB_DQ17 7 DDRB_DQ16 7 DDRB_DQ23 7 DDRB_DQ21 7 DDRB_DQ28 7 DDRB_DQ25 7 DDRB_DQ26 7 DDRB_DQ29 7 DDRB_DQ38 7 DDRB_DQ35 7 DDRB_DQ33 7 DDRB_DQ32 7 DDRB_DQ40 7 DDRB_DQ41 7 DDRB_DQ42 7 DDRB_DQ46 7 DDRB_DQ52 7 DDRB_DQ48 7 DDRB_DQ50 7 DDRB_DQ51 7 DDRB_DQ57 7 DDRB_DQ61 7 DDRB_DQ56 7 DDRB_DQ60 7 DDRB_DQ34 7 DDRB_MA13 7 DDRB_DQ39 7 DDRB_DQ36 7 DDRB_DQ37 7 DDRB_DQ44 7 DDRB_DQ45 7 DDRB_DQ47 7 DDRB_DQ43 7 DDRB_DQ54 7 DDRB_DQ55 7 DDRB_DQ53 7 DDRB_DQ49 7 DDRB_DQ59 7 DDRB_DQ62 7 DDRB_DQ63 7 DDRB_DQ58 7 PCH_DRAMRST# 12,16 SMB_DATA_S3 12,16,45,50 SMB_CLK_S3 12,16,45,50 +0.6VS +1.2V +1.2V +VREF_DQ_DIMMB_R +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +2.5V +3VS +2.5V +0.6VS +3VS +3VS +3VS +1.2V Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM B C 13 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM B C 13 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM B C 13 75 Friday, November 25, 2016 2015/02/26 2016/02/26 CD64 10U_0402_6.3V6M 1 2 RD32 0_0402_5% 1 2 CD46 1U_0402_6.3V6K 1 2 RD6 240_0402_5% 1 2 STD JDDRH1B ARGOS_D4AS0-26001-1P52 ME@ A3 131 A1 133 VDD_9 135 CK0_t 137 CK0_c 139 VDD_11 141 Parity 143 BA1 145 VDD_13 147 CS0_n 149 WE_n/A14 151 VDD_15 153 ODT0 155 CS1_n 157 VDD_17 159 ODT1 161 VDD_19 163 C1/CS3_n/NC 165 VSS_53 167 DQ37 169 VSS_55 171 DQ33 173 VSS_57 175 DQS4_c 177 DQS4_t 179 VSS_60 181 DQ38 183 VSS_62 185 DQ34 187 VSS_64 189 DQ44 191 VSS_66 193 DQ40 195 VSS_68 197 DM5_n/DBl5_n 199 VSS_69 201 DQ46 203 VSS_71 205 DQ42 207 VSS_73 209 DQ52 211 VSS_75 213 DQ49 215 VSS_77 217 DQS6_c 219 DQS6_t 221 VSS_80 223 DQ55 225 VSS_82 227 DQ51 229 VSS_84 231 DQ61 233 VSS_86 235 DQ56 237 VSS_88 239 DM7_n/DBl7_n/NC 241 VSS_89 243 DQ62 245 VSS_91 247 DQ58 249 VSS_93 251 SCL 253 VDDSPD 255 VPP_1 257 VPP_2 259 A2 132 EVENT_n/NF 134 VDD_10 136 CK1_t/NF 138 CK1_c/NF 140 VDD_12 142 A0 144 A10/AP 146 VDD_14 148 BA0 150 RAS_n/A16 152 VDD_16 154 CAS_n/A15 156 A13 158 VDD_18 160 C0/CS2_n/NC 162 VREFCA 164 SA2 166 VSS_54 168 DQ36 170 VSS_56 172 DQ32 174 VSS_58 176 DM4_n/DBl4_n/NC 178 VSS_59 180 DQ39 182 VSS_61 184 DQ35 186 VSS_63 188 DQ45 190 VSS_65 192 DQ41 194 VSS_67 196 DQS5_c 198 DQS5_t 200 DQ47 204 VSS_70 202 DQ43 208 VSS_72 206 VSS_74 210 DQ53 212 VSS_76 214 DQ48 216 VSS_78 218 DQ54 224 VSS_79 222 DQ50 228 VSS_81 226 DQ60 232 VSS_83 230 DQ57 236 DM6_n/DBl6_n/NC 220 VSS_85 234 DQ63 246 VSS_87 238 DQ59 250 VSS_92 248 DQS7_c 240 DQS7_t 242 VSS_90 244 VSS_94 252 SDA 254 SA0 256 SA1 260 Vtt 258 GND_1 261 GND_2 262 CD71 1U_0402_6.3V6K 1 2 CD50 10U_0402_6.3V6M 1 2 CD4 33P_0402_50V8J RF@ 1 2 RD29 0_0402_5% 1 2 RD19 0_0402_5% 1 2 CD61 1U_0402_6.3V6K 1 2 CD72 1U_0402_6.3V6K 1 2 CD47 .1U_0402_10V6-K 1 2 RD13 1K_0402_1% 1 2 CD51 10U_0402_6.3V6M 1 2 CD54 .1U_0402_10V6-K 1 2 CD62 1U_0402_6.3V6K 1 2 CD73 1U_0402_6.3V6K 1 2 CD31 .1U_0402_10V6-K 1 2 CD35 10U_0603_6.3V6M 1 2 RD11 1K_0402_1% 1 2 CD36 10U_0603_6.3V6M 1 2 CD30 2.2U_0603_6.3V6K 1 2 CD53 2.2U_0603_6.3V6K 1 2 CD74 1U_0402_6.3V6K 1 2 CD37 10U_0603_6.3V6M 1 2 RD28 0_0402_5% @ 1 2 CD49 1U_0402_6.3V6K 1 2 RD30 0_0402_5% 1 2 STD JDDRH1A ARGOS_D4AS0-26001-1P52 ME@ VSS_1 1 DQ5 3 VSS_3 5 DQ1 7 VSS_5 9 DQS0_C 11 DQS0_t 13 VSS_8 15 DQ7 17 VSS_10 19 DQ3 21 VSS_12 23 DQ13 25 VSS_14 27 DQ9 29 VSS_16 31 DM1_n/DBl1_n/NC 33 VSS_17 35 DQ15 37 VSS_19 39 DQ10 41 VSS_21 43 DQ21 45 VSS_23 47 DQ17 49 VSS_25 51 DQS2_c 53 DQS2_t 55 VSS_28 57 DQ23 59 VSS_30 61 DQ19 63 VSS_32 65 DQ29 67 VSS_34 69 DQ25 71 VSS_36 73 DM3_n/DBl3_n/NC 75 VSS_37 77 DQ30 79 VSS_39 81 VSS_2 2 DQ4 4 VSS_4 6 DQ0 8 VSS_6 10 DM0_n/DBI0_n/NC 12 VSS_7 14 DQ6 16 VSS_9 18 DQ2 20 VSS_11 22 DQ12 24 VSS_13 26 DQ8 28 VSS_15 30 DQS1_c 32 DQS1_t 34 VSS_18 36 DQ14 38 VSS_20 40 DQ11 42 VSS_22 44 DQ20 46 VSS_24 48 DQ16 50 VSS_26 52 DM2_n/DBl2_n/NC 54 VSS_27 56 DQ22 58 VSS_29 60 DQ18 62 VSS_31 64 DQ28 66 VSS_33 68 DQ24 70 VSS_35 72 DQS3_c 74 DQS3_t 76 VSS_38 78 DQ31 80 VSS_40 82 DQ26 83 VSS_41 85 CB5/NC 87 VSS_43 89 CB1/NC 91 VSS_45 93 DQS8_c 95 DQS8_t 97 VSS_48 99 CB2/NC 101 VSS_50 103 CB3/NC 105 VSS_52 107 CKE0 109 VDD_1 111 BG1 113 BG0 115 VDD_3 117 A12 119 A9 121 VDD_5 123 A8 125 A6 127 VDD_7 129 DQ27 84 VSS_42 86 CB4/NC 88 VSS_44 90 CB0/NC 92 VSS_46 94 DBI8_n/DBI_n/NC 96 VSS_47 98 CB6/NC 100 VSS_49 102 CB7/NC 104 VSS_51 106 RESET_n 108 CKE1 110 VDD_2 112 ACT_n 114 ALERT_n 116 VDD_4 118 A11 120 A7 122 VDD_6 124 A5 126 A4 128 VDD_8 130 CD44 1U_0402_6.3V6K 1 2 CD39 10U_0603_6.3V6M 1 2 RD14 24.9_0402_1% 1 2 RD12 2_0402_5% 1 2 CD43 1U_0402_6.3V6K 1 2 CD83 33P_0402_50V8J RF@ 1 2 CD41 10U_0603_6.3V6M 1 2 CD29 0.022U_0402_16V7-K 1 2 CD38 10U_0603_6.3V6M 1 2 CD63 10U_0402_6.3V6M 1 2 CD45 1U_0402_6.3V6K 1 2 RD21 0_0402_5% 1 2 CD70 0.1U_0402_10V7K @ 1 2 RD33 0_0402_5% @ 1 2 RD31 0_0402_5% @ 1 2 CD40 10U_0603_6.3V6M 1 2 CD84 33P_0402_50V8J RF@ 1 2 CD42 10U_0603_6.3V6M 1 2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A NGFF SSD HDD NGFF SSD NGFF SSD NGFF SSD HDD Cable Add Reserved HDD cable HLZ SDV 20160510 Change RH35 from 43 to 12.1 due to follow DG&CRB HLZ SDV 0601 Reserved Cap HLZ SDV 0616 Add RH781_@ for PCH PECI HLZ SIV 0811 Delete HDD Cable SATA signal HLZ SDV 20160510 EC_SCI# SSD_DET# PCIE_SATA_PRX_DTX_N9 PCIE_SATA_PRX_DTX_P9 PCIE_SATA_PTX_DRX_N9 PCIE_SATA_PTX_DRX_P9 PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12 PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12 PCH_THRMTRIP#_R CPU_PLTRST# PCH_PECI H_PM_SYNC_R H_PM_DOWN PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10 SATA_LED# H_PM_DOWN PCH_PECI CPU_PLTRST# EC_SCI# 20,49 SSD_DET# 45 PCIE_SATA_PRX_DTX_N9 45 PCIE_SATA_PRX_DTX_P9 45 PCIE_SATA_PTX_DRX_N9 45 PCIE_SATA_PTX_DRX_P9 45 PCIE_PTX_DRX_P11 45 PCIE_PTX_DRX_N11 45 PCIE_PRX_DTX_P11 45 PCIE_PRX_DTX_N11 45 PCIE_PTX_DRX_P12 45 PCIE_PTX_DRX_N12 45 PCIE_PRX_DTX_P12 45 PCIE_PRX_DTX_N12 45 H_THRMTRIP# 6,24 CPU_PLTRST# 6 H_PM_SYNC 6 H_PM_DOWN 6 EC_PECI 6,49 PCH_EDP_ENVDD 35 PCH_EDP_ENBKL 35 PCH_EDP_PWM 35 PCIE_PRX_DTX_N10 45 PCIE_PRX_DTX_P10 45 PCIE_PTX_DRX_N10 45 PCIE_PTX_DRX_P10 45 SATA_PRX_DTX_P2 46 SATA_PRX_DTX_N2 46 SATA_PTX_DRX_N2 46 SATA_PTX_DRX_P2 46 +3VS +3VS Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (1/9) PCIe/SATA/GPPFG Custom 14 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (1/9) PCIe/SATA/GPPFG Custom 14 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (1/9) PCIe/SATA/GPPFG Custom 14 75 Friday, November 25, 2016 2015/02/26 2016/02/26 RH34 620_0402_5% 1 2 CH7 .1U_0402_10V6-K @ 1 2 CLINK FAN PCIe/SATA HOST SPT-H_PCH 3 OF 12 UH1C SKYLAKE-H-PCH_FCBGA837 @ CL_CLK AV2 CL_DATA AV3 CL_RST# AW2 GPP_G8/FAN_PWM_0 R44 GPP_G9/FAN_PWM_1 R43 GPP_G10/FAN_PWM_2 U39 GPP_G11/FAN_PWM_3 N42 GPP_G0/FAN_TACH_0 U43 GPP_G1/FAN_TACH_1 U42 GPP_G2/FAN_TACH_2 U41 GPP_G3/FAN_TACH_3 M44 GPP_G4/FAN_TACH_4 U36 GPP_G5/FAN_TACH_5 P44 GPP_G6/FAN_TACH_6 T45 GPP_G7/FAN_TACH_7 T44 PCIE11_TXP B33 PCIE11_TXN C33 PCIE11_RXP K31 PCIE11_RXN L31 GPP_F10/SCLOCK AB33 GPP_F11/SLOAD AB35 GPP_F13/SDATAOUT0 AA44 GPP_F12/SDATAOUT1 AA45 PCIE14_TXN/SATA1B_TXN B38 PCIE14_TXP/SATA1B_TXP C38 PCIE14_RXN/SATA1B_RXN D39 PCIE14_RXP/SATA1B_RXP E37 PCIE13_TXN/SATA0B_TXN C36 PCIE13_TXP/SATA0B_TXP B36 PCIE13_RXN/SATA0B_RXN G35 PCIE13_RXP/SATA0B_RXP E35 PCIE12_TXP A35 PCIE12_TXN B35 PCIE12_RXP H33 PCIE12_RXN G33 PCIE20_TXP/SATA7_TXP J45 PCIE20_TXN/SATA7_TXN K44 PCIE20_RXP/SATA7_RXP N38 PCIE20_RXN/SATA7_RXN N39 PCIE19_TXP/SATA6_TXP H44 PCIE19_TXN/SATA6_TXN H43 PCIE19_RXP/SATA6_RXP L39 PCIE19_RXN/SATA6_RXN L37 PCIE9_RXN/SATA0A_RXN G31 PCIE9_RXP/SATA0A_RXP H31 PCIE9_TXN/SATA0A_TXN C31 PCIE9_TXP/SATA0A_TXP B31 PCIE10_RXN/SATA1A_RXN G29 PCIE10_RXP/SATA1A_RXP E29 PCIE10_TXN/SATA1A_TXN C32 PCIE10_TXP/SATA1A_TXP B32 PCIE15_RXN/SATA2_RXN F41 PCIE15_RXP/SATA2_RXP E41 PCIE15_TXN/SATA2_TXN B39 PCIE15_TXP/SATA2_TXP A39 PCIE16_RXN/SATA3_RXN D43 PCIE16_RXP/SATA3_RXP E42 PCIE16_TXN/SATA3_TXN A41 PCIE16_TXP/SATA3_TXP A40 PCIE17_RXN/SATA4_RXN H42 PCIE17_RXP/SATA4_RXP H40 PCIE17_TXN/SATA4_TXN E45 PCIE17_TXP/SATA4_TXP F45 PCIE18_RXN/SATA5_RXN K37 PCIE18_RXP/SATA5_RXP G37 PCIE18_TXN/SATA5_TXN G45 PCIE18_TXP/SATA5_TXP G44 GPP_E8/SATALED# AD44 GPP_E0/SATAXPCIE0/SATAGP0 AG36 GPP_E1/SATAXPCIE1/SATAGP1 AG35 GPP_E2/SATAXPCIE2/SATAGP2 AG39 GPP_F0/SATAXPCIE3/SATAGP3 AD35 GPP_F1/SATAXPCIE4/SATAGP4 AD31 GPP_F2/SATAXPCIE5/SATAGP5 AD38 GPP_F3/SATAXPCIE6/SATAGP6 AC43 GPP_F4/SATAXPCIE7/SATAGP7 AB44 GPP_F21/EDP_BKLTCTL W36 GPP_F20/EDP_BKLTEN W35 GPP_F19/EDP_VDDEN W42 THERMTRIP# AJ3 PECI AL3 PM_SYNC AJ4 PLTRST_PROC# AK2 PM_DOWN AH2 RH35 13_0402_5% 1 2 RH13 30_0402_1% 1 2 RH133 10K_0402_5% 1 2 RH15 10K_0402_5% 1 2 RH781 0_0402_5% @ 1 2 RH95 0_0402_5% 1 2 CH263 0.1U_0402_25V6 EMC_NS@ 1 2 CH6 .1U_0402_10V6-K @ 1 2 WWW.AliSaler.Com
5 5 4 4 3 3 2 2 1 1 D D C C B B A A LEFT USB (3.0) LEFT USB (3.0) DDPB_CTRLDATA The signal has a weak internal pull-down. H Port B is detected. L Port B is not detected. * NGFF SSD HDMI DDPC_CTRLDATA The signal has a weak internal pull-down. H Port C is detected. L Port C is not detected. (Default) DDPD_CTRLDATA The signal has a weak internal pull-down. H Port D is detected. L Port D is not detected. (Default) * * 3D Camera Different to Y710 HLZ SDV 20160510 Add Port C/D strap HLZ SDV 20160510 Delete 3D camera HLZ SDV 20160510 Type C USB3.0 Add TypeC USB3 HLZ SDV 20160510 LPC_AD2 LPC_AD0 LPC_AD3 LPC_AD1 USB30_RX_N1 USB30_TX_N1 USB30_TX_P1 USB30_RX_P1 CLK_PCI_EC_R CLK_PCI_TPM_R CLK_PCI_EC PCH_SMI# KBRST# PCH_SMI# DDPB_CLK DDPB_DATA SERIRQ DEVSLP0_R DDPB_CLK DDPB_DATA PCH_EDP_HPD USB30_RX_N2 USB30_TX_N2 USB30_RX_P2 USB30_TX_P2 KBRST# LPC_FRAME# SERIRQ CLK_PCI_TPM DDPC_DATA DDPD_DATA DDPD_DATA DDPC_DATA TYPE-C_USB3_TX_N3 TYPE-C_USB3_TX_P3 TYPE-C_USB3_RX_N3 TYPE-C_USB3_RX_P3 DDPC_CLK DDPD_CLK LPC_AD3 49,50 LPC_AD2 49,50 LPC_AD1 49,50 LPC_AD0 49,50 USB30_TX_N1 47 USB30_RX_P1 47 USB30_RX_N1 47 USB30_TX_P1 47 CLK_PCI_EC 49 CLK_PCI_TPM 50 HDMI_HPD 36 DEVSLP0_R 45 DDPB_CLK 36 DDPB_DATA 36 PCH_EDP_HPD 35 USB30_RX_N2 47 USB30_RX_P2 47 USB30_TX_N2 47 USB30_TX_P2 47 KBRST# 49 SERIRQ 49,50 LPC_FRAME# 49,50 TYPE-C_DP_HPD 37 TYPE-C_USB3_RX_N3 38 TYPE-C_USB3_RX_P3 38 TYPE-C_USB3_TX_N3 38 TYPE-C_USB3_TX_P3 38 +3VS +3VS +3VS +3VS Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (2/9) USB3/GPPAEFGHI Custom 15 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (2/9) USB3/GPPAEFGHI Custom 15 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (2/9) USB3/GPPAEFGHI Custom 15 75 Friday, November 25, 2016 2015/02/26 2016/02/26 USB SATA LPC/eSPI SPT-H_PCH 6 OF 12 UH1F SKYLAKE-H-PCH_FCBGA837 @ USB3_1_TXN C11 USB3_1_TXP B11 USB3_1_RXN B7 USB3_1_RXP A7 USB3_2_TXN/SSIC_1_TXN B12 USB3_2_TXP/SSIC_1_TXP A12 USB3_2_RXN/SSIC_1_RXN C8 USB3_2_RXP/SSIC_1_RXP B8 USB3_6_TXN B15 USB3_6_TXP C15 USB3_6_RXN K15 USB3_6_RXP K13 USB3_5_TXN B14 USB3_5_TXP C14 USB3_5_RXN G13 USB3_5_RXP H13 USB3_3_TXP/SSIC_2_TXP D13 USB3_3_TXN/SSIC_2_TXN C13 USB3_3_RXP/SSIC_2_RXP A9 USB3_3_RXN/SSIC_2_RXN B10 USB3_4_TXP B13 USB3_4_TXN A14 USB3_4_RXP G11 USB3_4_RXN E11 GPP_A1/LAD0/ESPI_IO0 AT22 GPP_A2/LAD1/ESPI_IO1 AV22 GPP_A3/LAD2/ESPI_IO2 AT19 GPP_A4/LAD3/ESPI_IO3 BD16 GPP_A5/LFRAME#/ESPI_CS0# BE16 GPP_A6/SERIRQ/ESPI_CS1# BA17 GPP_A7/PIRQA#/ESPI_ALERT0# AW17 GPP_A0/RCIN#/ESPI_ALERT1# AT17 GPP_A14/SUS_STAT#/ESPI_RESET# BC18 GPP_A9/CLKOUT_LPC0/ESPI_CLK BC17 GPP_A10/CLKOUT_LPC1 AV19 GPP_G19/SMI# M45 GPP_G18/NMI# N43 GPP_E6/DEVSLP2 AE45 GPP_E5/DEVSLP1 AG43 GPP_E4/DEVSLP0 AG42 GPP_F9/DEVSLP7 AB39 GPP_F8/DEVSLP6 AB36 GPP_F7/DEVSLP5 AB43 GPP_F6/DEVSLP4 AB42 GPP_F5/DEVSLP3 AB41 RH8 2.2K_0402_5% 1 2 RH104 10K_0402_5% 1 2 RH10 2.2K_0402_5% @ 1 2 RH84 22_0402_5% 1 2 RH32 2.2K_0402_5% 1 2 RH113 10K_0402_5% 1 2 CH265 10P_0402_50V8J EMC_NS@ 1 2 RH87 22_0402_5% TPM@ 1 2 TC110 PAD @ 1 RH33 2.2K_0402_5% 1 2 RH129 10K_0402_5% @ 1 2 CH266 10P_0402_50V8J EMC_NS@ 1 2 IT28 PAD @ 1 IT36 PAD @ 1 SPT-H_PCH 5 OF 12 UH1E SKYLAKE-H-PCH_FCBGA837 @ GPP_I0/DDPB_HPD0 AW4 GPP_I1/DDPC_HPD1 AY2 GPP_I2/DDPD_HPD2 AV4 GPP_I3/DDPE_HPD3 BA4 GPP_I4/EDP_HPD BD7 GPP_I7/DDPC_CTRLCLK BB3 GPP_I8/DDPC_CTRLDATA BD6 GPP_I5/DDPB_CTRLCLK BA5 GPP_I6/DDPB_CTRLDATA BC4 GPP_I9/DDPD_CTRLCLK BE5 GPP_I10/DDPD_CTRLDATA BE6 GPP_F14 Y44 GPP_F23 V44 GPP_F22 W39 GPP_G23 L43 GPP_G22 L44 GPP_G21 U35 GPP_G20 R35 GPP_H23 BD36
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
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NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
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NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
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NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf
NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf

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NM-B191 Y520_MB_N17P_SVT_20161125-1430.pdf

  • 1. A A B B C C D D E E 1 1 2 2 3 3 4 4 Intel Kabylake H-Processor with DDR4 + NV N17P-G0/G1 GPU DY512 M/B Schematics Document 2016-11-25 REV:1.0 LCFC Confidential MB NM-B191 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Cover Page Custom 1 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Cover Page Custom 1 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Cover Page Custom 1 75 Friday, November 25, 2016 2015/02/26 2016/02/26
  • 2. A A B B C C D D E E 1 1 2 2 3 3 4 4 PCIE 4x Gen3 SSD BH611FJ1LN Codec 8MB IO Board (RJ45/USB2.0/Aduio combo jack) Sub-board SPK Conn. NV N17P-G0 40W GDDR5*4 4GB/2GB VRAM 256/128*32 EC ITE IT8226-LQFP Touch Pad Int.KBD Thermal Sensor Fintek F75303M HDMI Conn. USB Right USB 2.0 2x 480Mbps USB Left USB 3.0 2x 5Gbps NGFF Card WLAN&BT SATA Gen3 6Gbps SATA HDD Realtek ALC3248 HD Audio(24MHz) HP&Mic Combo Conn. SPI ROM SPI BUS(17/33/48MHz) PCIe 1x Gne1 250MGB/s CardReader SD/MMC Memory BUS (DDR4 non-ECC) Dual Channel 1.2V DDR4 2400 MT/s 19.2GB/s *2 Total 38.4GB/s USB 3.0 Port1 TMDS 2.97Gbps IO Board IO Board eDP x2 Lane eDP Conn SATA Port2 PCIe Port2 USB2.0 Port1 USB2.0 Port11 PCIe Port3 Page 24~29 Page 30~33 Page 35 Page 42 Page 41 Page 39 Page 39 Page 43 Page 44 Page 41 Page 18 Page 46 Page 46 Page 45 Page 40 Page 14~22 Page 43 USB 3.0 Port2 USB 2.0 Port2 USB 2.0 Port3 SPI ROM 4MB Page 18 PCI-Express 8x Gen3 BGA-1440 42mm*28mm Intel CPU Kaby Lake-H 45W Intel PCH Kaby Lake-H FCBGA 23mm*23mm DMI *4 1GB/s * 4 Total 4GB/s PCIe Port4 LPC(24MHz) TPM Z32H320TC Page 46 FHD : 15"1920*1080 HDMI level shift PS8203 Optane memory One M.2 CONN RTL8111GUL(1000M) LAN Realtek RJ45 Conn. Dual DMIC USB2.0 1x 480Mbps Int. Camera DMIC Page 5~11 Page 35 Page 34 Page 34 RTS5400 Page 36~37 USB 3.0 1x 5Gbps USB2.0 1x 480Mbps DP x4Lane Typec CONN Page 37 PCIe Port9~12 Type C controller UP TO 8G x 2 DDR4-SO-DIMM X2 Page 12,13 TP BUTTON Board (Only for Provence‐5R) 1GB/s * 8 Total 8GB/s 1GB/s * 4 Total 4GB/s USB 2.0 1x 480Mbps PCIe 1x Gne1 250MGB/s USB 2.0 1x 480Mbps PCIe 1x Gne1 250MGB/s 2.7Gb/s * 2 Total 5.4Gb/s 5.4Gb/s * 4 Total 21.6Gb/s DP Redriver PS8330B NV N17P-G1 50W CPU FAN GPU FAN Page 40 Battery Page 58 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Block Diagram C 2 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Block Diagram C 2 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Block Diagram C 2 75 Friday, November 25, 2016 2015/02/26 2016/02/26 WWW.AliSaler.Com
  • 3. A A B B C C D D E E 1 1 2 2 3 3 4 4 STATE SIGNAL Full ON S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF) SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock Voltage Rails ON ON ON ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH +3VS +5VS CPU_CORE Power Plane O State +1.8V_AON VCCIO NVVDD +0.6VS +1.35VGS NVVDDS BTO Item BOM Structure BOM Structure Table S0 S3 S5 S4/AC Only S5 S4 Battery only S5 S4 AC & Battery don't exist B+ +3VALW +5VALW +1.2V O O O O O O O O O X X X X X X X X X ( O --> Means ON , X --> Means OFF ) +3VALW_PCH S3 Battery only O X O O O X X X O O Not stuff @ O +0.95VGS ME@ OPT@ ME part(connector, hole) For GPU part CD@ Cost down part TPM@ For support TPM sku part +2.5V +1.0VALW +1.8V_MAIN GFX VCCSTG VCCST VCCSA EMC@ EMC_NS@ EMC part stuff EMC part Not stuff RF@ RF_NS@ RF part stuff RF part Not stuff N16@ N17@ For N16 GPU part For N17 GPU part USB2.0 Port table Port Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Right USB2 Left USB3 Left USB3 TypeC USB2 Camera BT HSIO port Table Port Description 8 1 2 3 4 11 12 5 6 7 14 9 10 13 Left USB3 15 16 17 18 19 20 21 22 23 24 25 26 Left USB3 TypeC USB3 Function USB3#1 USB3#2 USB3#3 USB3#4 USB3#5 USB3#6 USB3#7 / PCIE#1 USB3#8 / PCIE#2 USB3#9 / PCIE#3 USB3#10 / PCIE#4 PCIE#5 PCIE#6 PCIE#7 PCIE#8 PCIE#9 / SATA#0 PCIE#10 / SATA#1 PCIE#11 PCIE#12 PCIE#13 / SATA#0 PCIE#14 / SATA#1 PCIE#15 / SATA#2 PCIE#16 / SATA#3 PCIE#17 / SATA#4 PCIE#18 / SATA#5 PCIE#19 / SATA#6 PCIE#20 / SATA#6 CarderReader(PCIE) WLAN(PCIE) LAN(PCIE) PCIe x4 SSD HDD(SATA3.0) HDD cable(SATA3.0) Reserved Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Notes List Custom 3 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Notes List Custom 3 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Notes List Custom 3 75 Friday, November 25, 2016 2015/02/26 2016/02/26
  • 4. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A EC IT8226 Battery JBATT2 EC_SMB_CK1 EC_SMB_DA1 Change IC PU102 BQ24780SRUYR +3VALW_R 2.2K 2.2K +3VS Dual MOS EC_SMB_CK2 EC_SMB_DA2 Thermal sensor U1 F75303M Dual MOS +3VS_AON Control +3VS Control PCH( UH1 ) +3VALW_PCH 2.2K NV GPU( UV1 ) +3VS_AON 2.2K VGA_SMB_CK2 VGA_SMB_DA2 SML1CLK SML1DATA VGA V X X SODIMM BATT IT8586E PCH Thermal Sensor WLAN WiMAX PCH IT8226 +3VS V +3VALW_PCH X +3VGS V EC_SMB_DA2 EC_SMB_CK2 V PCH_SMB_CLK SMBUS Control Table +3VALW_PCH V V X TP Module V X X X X X X X X X X +3VS +3VS +3VALW_PCH X +3VS +3VS PCH 0001 0010 b Charger Rsvd WLAN need to update 0x41(default) VGA 0xD4 RTS5400 X PCH_SMB_DATA +3VALW V V charger V X EC_SMB_DA1 EC_SMB_CK1 IT8226 SOURCE +3VALW PCH SM Bus address 1010 010Xb DDR DIMMB 1010 000Xb DDR DIMMA Device EC SM Bus1 address 1001_100xb Thermal Sensor F75303M 0X16 Smart Battery Device EC SM Bus2 address Address Address Device +3VALW_PCH 2.2K PCH_SMBCLK PCH_SMBDATA +3VS DDR1 2.2K VGA_SMB_CK2 VGA_SMB_DA2 PCH +3VS Control Dual MOS DDR2 WLAN TP EC_SMB_CK0 EC_SMB_DA0 +3VALW Control RTS5400 Dual MOS +3.3V_LDO_RTS5400 2.2K RTS5400_SM_SCL RTS5400_SM_SDA 2.2K +3VALW Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Blank4 Custom 4 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Blank4 Custom 4 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 Blank4 Custom 4 75 Friday, November 25, 2016 2015/02/26 2016/02/26 WWW.AliSaler.Com
  • 5. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils. I7 : SA00007HB20 I5 : SA00007HS10 Change PEG from X16 to X8 HLZ SDV 20160510 Change PEG from X16 to X8 HLZ SDV 20160510 PEG_COMP DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 DMI_CTX_PRX_N0 DMI_CTX_PRX_N3 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CTX_PRX_P0 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3 DMI_CRX_PTX_P2 DMI_CRX_PTX_P1 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_P0 PEG_COMP PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P7 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N[0..7] 24 PCIE_CRX_GTX_P[0..7] 24 PCIE_CTX_C_GRX_N[0..7] 24 PCIE_CTX_C_GRX_P[0..7] 24 DMI_CTX_PRX_N0 19 DMI_CTX_PRX_N1 19 DMI_CTX_PRX_N2 19 DMI_CTX_PRX_N3 19 DMI_CTX_PRX_P0 19 DMI_CTX_PRX_P1 19 DMI_CTX_PRX_P2 19 DMI_CTX_PRX_P3 19 DMI_CRX_PTX_N0 19 DMI_CRX_PTX_N1 19 DMI_CRX_PTX_N2 19 DMI_CRX_PTX_N3 19 DMI_CRX_PTX_P0 19 DMI_CRX_PTX_P1 19 DMI_CRX_PTX_P2 19 DMI_CRX_PTX_P3 19 VCCIO Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (1/7) DMI,PEG Custom 5 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (1/7) DMI,PEG Custom 5 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (1/7) DMI,PEG Custom 5 75 Friday, November 25, 2016 2015/02/26 2016/02/26 CC24 0.22U_0402_10V6K OPT@ 1 2 CC7 0.22U_0402_10V6K OPT@ 1 2 CC22 0.22U_0402_10V6K OPT@ 1 2 CC5 0.22U_0402_10V6K OPT@ 1 2 RC1 24.9_0402_1% 1 2 CC20 0.22U_0402_10V6K OPT@ 1 2 CC8 0.22U_0402_10V6K OPT@ 1 2 CC19 0.22U_0402_10V6K OPT@ 1 2 CC23 0.22U_0402_10V6K OPT@ 1 2 CC18 0.22U_0402_10V6K OPT@ 1 2 CC6 0.22U_0402_10V6K OPT@ 1 2 CC21 0.22U_0402_10V6K OPT@ 1 2 CC4 0.22U_0402_10V6K OPT@ 1 2 CC3 0.22U_0402_10V6K OPT@ 1 2 CC2 0.22U_0402_10V6K OPT@ 1 2 SKYLAKE_HALO BGA1440 3 OF 14 UC1C SKYLAKE-H-CPU_BGA1440 @ PEG_RXN[0] D25 PEG_RXN[2] D23 PEG_RXP[2] E23 PEG_RXN[1] F24 PEG_RXP[13] F12 DMI_TXN[3] B4 DMI_TXP[3] D4 DMI_TXN[2] A5 DMI_TXP[2] B5 DMI_TXP[1] C6 DMI_TXN[1] B6 DMI_TXN[0] A8 DMI_TXP[0] B8 DMI_RXP[3] J8 DMI_RXN[3] J9 DMI_RXN[2] E5 DMI_RXP[2] D5 DMI_RXP[1] E6 DMI_RXN[1] F6 DMI_RXP[0] D8 DMI_RXN[0] E8 PEG_RCOMP G2 PEG_RXP[15] F10 PEG_RXP[14] D11 PEG_RXN[15] E10 PEG_RXP[8] D17 PEG_RXN[7] F18 PEG_RXP[7] E18 PEG_RXN[3] F22 PEG_RXP[1] E24 PEG_RXP[3] E22 PEG_RXP[4] E21 PEG_RXN[4] D21 PEG_RXP[5] E20 PEG_RXP[6] E19 PEG_RXP[10] D15 PEG_RXN[10] E15 PEG_RXP[11] F14 PEG_RXN[11] E14 PEG_RXP[12] D13 PEG_RXN[13] E12 PEG_RXN[14] E11 PEG_TXP[0] B25 PEG_TXN[0] A25 PEG_TXP[1] B24 PEG_TXN[1] C24 PEG_TXN[2] A23 PEG_TXP[2] B23 PEG_TXN[3] C22 PEG_TXP[3] B22 PEG_TXP[4] B21 PEG_TXN[5] C20 PEG_TXN[4] A21 PEG_TXP[5] B20 PEG_TXN[6] A19 PEG_TXP[6] B19 PEG_TXP[7] B18 PEG_TXP[8] A17 PEG_TXN[10] B15 PEG_TXP[10] A15 PEG_TXN[9] B16 PEG_TXP[11] C14 PEG_TXN[11] B14 PEG_TXN[12] B13 PEG_TXP[12] A13 PEG_TXN[13] B12 PEG_TXP[13] C12 PEG_TXN[14] B11 PEG_TXP[14] A11 PEG_TXP[15] C10 PEG_TXN[15] B10 PEG_RXN[12] E13 PEG_RXN[9] E16 PEG_RXN[8] E17 PEG_TXP[9] C16 PEG_TXN[8] B17 PEG_RXP[9] F16 PEG_TXN[7] C18 PEG_RXN[5] F20 PEG_RXN[6] D19 PEG_RXP[0] E25 CC1 0.22U_0402_10V6K OPT@ 1 2 CC17 0.22U_0402_10V6K OPT@ 1 2
  • 6. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A CFG STRAPS for CPU(Internal PH) R e s e r v e d c o n f i g u r a t i o n l a n e . CFG1 e D P e n a b l e 1 = Disabled. CFG4 P E G T r a i n i n g CFG7 1 = (default) PEG Train immediately following RESET# deassertion. 0 = PEG Wait for BIOS for training. 10 = 2 x8 PCI Express* 00 = 1 x8, 2 x4 PCI Express* 11 = 1 x16 PCI Express* 01 = reserved P C I E x p r e s s * B i f u r c a t i o n CFG[6:5] S t a l l r e s e t s e q u e n c e a f t e r P C U P L L l o c k u n t i l d e - a s s e r t e d 0 = Stall. 1 = (Default) Normal Operation; No stall. CFG0 P C I E x p r e s s * S t a t i c x 1 6 L a n e N u m b e r i n g R e v e r s a l . 1 = Normal operation CFG2 R e s e r v e d c o n f i g u r a t i o n l a n e . CFG3 N/A N/A R e s e r v e d c o n f i g u r a t i o n l a n e . CFG[19:8] N/A 20150527_Mount RC176 to enable DCI function Reserved Cap HLZ SDV 0616 0 = Lane reserval 0 = Enable Change C52&C127 from @ to stuff HLZ SIV 0811 Add C929 HLZ SIV 0811 Add RC184 HLZ SIV 0811 EC_PECI VCCST_PWRGD H_THRMTRIP#_R H_PM_SYNC VCCPWRGOOD_0_R H_PROCHOT#_R CPU_BCLK CPU_PCIBCLK# CPU_PCIBCLK CPU_NSSC_CLK# CPU_NSSC_CLK VR_SVID_ALRT#_R VR_SVID_CLK VR_SVID_DAT VR_SVID_ALRT#_R BUF_CPU_RST# DDR_PG_CTRL H_PM_DOWN_R CPU_TRIGOUT CPU_TRIGIN PCH_TRIGIN XDP_PREQ# CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG0 CFG1 CFG2 CFG0 CFG4 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG5 CFG6 CFG7 H_CATERR# CFG1 H_THRMTRIP#_R H_CATERR# SM_PG_CTRL CPU_BCLK# VR_SVID_DAT VR_SVID_CLK H_PROCHOT#_R H_CPUPWRGD H_THRMTRIP# BUF_CPU_RST# H_PM_SYNC CPU_TRIGIN DDR_PG_CTRL VCCST_PWRGD H_PM_SYNC 14 H_CPUPWRGD 16 H_PROCHOT# 49,65 PCH_CPU_BCLK# 17 PCH_CPU_BCLK 17 PCH_CPU_PCIBCLK# 17 PCH_CPU_PCIBCLK 17 PCH_CPU_NSSC_CLK# 17 PCH_CPU_NSSC_CLK 17 SVID_ALERT# 65 SVID_CLK 65 SVID_DATA 65 CPU_PLTRST# 14 H_PM_DOWN 14 H_THRMTRIP# 14,24 PCH_TRIGIN 22 CPU_TRIGIN 22 XDP_TDO 42 XDP_PRDY# 42 EC_PECI 14,49 CFG3 42 XDP_TDI 42 XDP_TMS 42 XDP_TCK 42 XDP_TRST# 42 XDP_PREQ# 42 SM_PG_CTRL 61 CPUCORE_ON 49,65 VCCST VCCST VCCST VCCIO VCCST +3VALW +1.2V +3VS +3VALW VCCST +3VS Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (2/7) PM, XDP, CLK, CFG C 6 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (2/7) PM, XDP, CLK, CFG C 6 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (2/7) PM, XDP, CLK, CFG C 6 75 Friday, November 25, 2016 2015/02/26 2016/02/26 TC29 PAD @ 1 C128 .1U_0402_10V6-K @ 1 2 C925 .1U_0402_10V6-K @ 1 2 RC4 30_0402_1% 1 2 RC50 60.4_0402_1% 1 2 TC105 PAD @ 1 TC100 PAD @ 1 TC89 PAD @ 1 TC95 PAD @ 1 TC82 PAD @ 1 TC91 PAD @ 1 RC52 1K_0402_5% @ 1 2 RC32 0_0402_5% 1 2 TC77 PAD @ 1 RC75 1K_0402_5% 1 2 RC179 10K_0402_5% @ 1 2 RC142 1K_0402_5% @ 1 2 TC42 PAD @ 1 RC140 1K_0402_5% @ 1 2 RC3 0_0402_5% 1 2 RC28 0_0402_5% 1 2 R292 10K_0402_5% @ 1 2 RC34 0_0402_5% 1 2 RC7 1K_0402_5% 1 2 TC101 PAD @ 1 TC96 PAD @ 1 TC92 PAD @ 1 RC29 0_0402_5% 1 2 TC78 PAD @ 1 RC14 0_0402_5% 1 2 RC22 0_0402_5% 1 2 RC54 1K_0402_5% 1 2 G D S Q1 2N7002KW_SOT323-3 2 1 3 RC177 100K_0402_5% @ 1 2 RC11 1K_0402_5% 1 2 RC15 0_0402_5% 1 2 C929 330P_0402_50V8J 1 2 RC53 1K_0402_5% 1 2 RC33 20_0402_1% 1 2 RC174 10K_0402_5% @ 1 2 RC13 0_0402_5% 1 2 C126 .1U_0402_10V6-K @ 1 2 TC102 PAD @ 1 TC97 PAD @ 1 TC83 PAD @ 1 TC79 PAD @ 1 TC86 PAD @ 1 RC76 56.2_0402_1% 1 2 RC143 1K_0402_5% @ 1 2 RC17 0_0402_5% 1 2 RC146 1K_0402_5% @ 1 2 E B C QC1 MMBT3904WH_SOT323-3 2 3 1 G D S Q2 2N7002KW_SOT323-3 2 1 3 RC56 1K_0402_5% @ 1 2 RC184 1K_0402_5% 1 2 RC66 100_0402_1% 1 2 RC16 0_0402_5% 1 2 RC55 1K_0402_5% @ 1 2 RC65 220_0402_5% 1 2 TC103 PAD @ 1 RC57 1K_0402_1% @ 1 2 TC98 PAD @ 1 TC93 PAD @ 1 TC84 PAD @ 1 RC178 100K_0402_5% 1 2 TC80 PAD @ 1 TC87 PAD @ 1 C133 .1U_0402_10V6-K @ 1 2 C120 .1U_0402_10V6-K @ 1 2 RC141 1K_0402_5% @ 1 2 TC27 PAD @ 1 RC175 49.9_0402_1% 1 2 RC139 1K_0402_5% @ 1 2 R291 10K_0402_5% 1 2 C52 .1U_0402_10V6-K 1 2 TC104 PAD @ 1 RC51 1K_0402_5% @ 1 2 TC99 PAD @ 1 TC94 PAD @ 1 TC28 PAD @ 1 TC90 PAD @ 1 RC144 1K_0402_5% @ 1 2 TC85 PAD @ 1 TC81 PAD @ 1 TC88 PAD @ 1 SKYLAKE_HALO BGA1440 5 OF 14 UC1E SKYLAKE-H-CPU_BGA1440 @ PROC_SELECT# BN1 CATERR# BM30 SKTOCC# BR33 PM_DOWN BP31 PM_SYNC BM34 RESET# BP35 PROCPWRGD BT31 VCCST_PWRGD H13 CFG[17] BN23 CFG[15] BT19 CFG[16] BP23 CFG[11] BT22 CFG[12] BM19 CFG[10] BT23 CFG[9] BR22 CLK24N D31 CFG[1] BN27 CFG[3] BN28 CFG[18] BN22 PROC_TDI BL32 CFG[0] BN25 CFG[2] BN26 CFG[4] BR20 CFG[6] BT20 CFG[5] BM20 CFG[7] BP20 CFG[8] BR23 CFG[13] BR19 CFG[14] BP19 CFG[19] BP22 PROC_PREQ# BL30 PROC_PRDY# BP27 VIDSCK BH32 PROC_TDO BT28 CLK24P E31 PCI_BCLKN C36 PCI_BCLKP D35 BCLKN A32 VIDSOUT BH29 PROCHOT# BR30 DDR_VTT_CNTL BT13 CFG_RCOMP BT25 PROC_TRST# BP30 PROC_TCK BR28 PROC_TMS BP28 VIDALERT# BH31 THERMTRIP# J31 PECI BT34 BCLKP B31 BPM#[0] BR27 BPM#[1] BT27 BPM#[2] BM31 BPM#[3] BT30 BGA1440 SKYLAKE_HALO 11 OF 14 UC1K SKYLAKE-H-CPU_BGA1440 @ RSVD_47 BT17 RSVD_48 BR17 RSVD_44 BJ28 RSVD_43 BK28 RSVD_TP_12 BK16 RSVD_TP_11 BJ16 VSS_447 BJ18 RSVD_27 BL34 RSVD_26 BN33 RSVD_TP_10 BJ13 RSVD_31 AA14 RSVD_30 AE29 RSVD_TP_6 BT2 RSVD_23 BN35 RSVD_24 J24 RSVD_TP_3 E3 RSVD_TP_4 E2 RSVD_TP_5 BR1 RSVD_32 A36 NCTF_6 C38 NCTF_5 C1 NCTF_4 BR2 NCTF_3 BP1 NCTF_1 B2 NCTF_2 B38 PROC_TRIGOUT J23 PROC_TRIGIN H23 RSVD_33 A37 RSVD_29 R14 RSVD_28 N29 RSVD_25 H24 RSVD_TP_9 BJ14 RSVD_50 AJ8 RSVD_TP_1 D1 RSVD_TP_2 E1 RSVD_TP_7 BM33 RSVD_TP_8 BL33 RSVD_TP_13 BK24 RSVD_TP_14 BJ24 RSVD_45 BK21 RSVD_46 BJ21 VSS_448 BK18 RSVD_TP_15 BJ34 RSVD_TP_16 BJ33 RSVD_49 G13 RSVD_51 BL31 RSVD_34 F30 RSVD_35 E30 RSVD_36 B30 RSVD_37 C30 RSVD_38 G3 RSVD_39 J3 RSVD_40 BR35 RSVD_41 BR31 RSVD_42 BH30 RC176 51_0402_1% 1 2 RC9 499_0402_1% 1 2 C127 .1U_0402_10V6-K 1 2 WWW.AliSaler.Com
  • 7. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR4 COMPENSATION SIGNALS CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil CAD Note: Trace width= 20 mil, Spcing=20 mils DDR_VREF_CA : Connected to VREF_CA on DIMM CH-A DDR0_VREF_DQ : NC DDR1_VREF_DQ : Connected to VREF_CA on DIMM CH-B DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10_AP DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_BG1 DDRA_ACT# DDRA_DQS0 DDRA_DQS1 DDRA_DQS2 DDRA_DQS3 DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63 +VREF_DQ_DIMM_R +V_DDR_REF_R +V_DDR_REFB_R DDRA_DQS#0 DDRA_DQS#1 DDRA_DQS#2 DDRA_DQS#3 DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10_AP DDRB_MA11 DDRB_MA12 DDRB_MA13 DDRB_BG1 DDRB_ACT# DDRB_DQS#0 DDRB_DQS#1 DDRB_DQS#2 DDRB_DQS#3 DDRB_DQS#4 DDRB_DQS#5 DDRB_DQS#6 DDRB_DQS#7 DDRB_DQS0 DDRB_DQS1 DDRB_DQS2 DDRB_DQS3 DDRB_DQS4 DDRB_DQS5 DDRB_DQS6 DDRB_DQS7 SM_RCOMP1 SM_RCOMP2 SM_RCOMP0 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 +V_DDR_REFA_R DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 DDRA_PARITY DDRA_ALERT# DDRB_PARITY DDRB_ALERT# DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS7 DDRA_DQS#4 DDRA_DQS#5 DDRA_DQS#6 DDRA_DQS#7 DDRA_DQ[0..63] 12 DDRA_CLK0# 12 DDRA_CS0# 12 DDRA_BA0 12 DDRA_MA16_RAS# 12 DDRA_MA14_WE# 12 DDRA_MA15_CAS# 12 DDRA_CLK0 12 DDRA_CKE0 12 DDRA_CLK1 12 DDRA_CLK1# 12 DDRA_CKE1 12 DDRA_CS1# 12 DDRA_BA1 12 DDRA_BG0 12 DDRA_MA[0..9] 12 DDRB_DQ[0..63] 13 DDRB_CLK0# 13 DDRB_CLK0 13 DDRB_CKE0 13 DDRB_CLK1 13 DDRB_CLK1# 13 DDRB_CKE1 13 DDRB_CS0# 13 DDRB_CS1# 13 DDRB_MA16_RAS# 13 DDRB_MA14_WE# 13 DDRB_MA15_CAS# 13 DDRB_MA[0..9] 13 DDRB_DQS#[0..7] 13 DDRB_DQS[0..7] 13 DDRB_BA0 13 DDRB_BA1 13 DDRB_BG0 13 DDRA_ODT0 12 DDRA_ODT1 12 DDRB_ODT0 13 DDRB_ODT1 13 DDRB_MA10_AP 13 DDRB_MA11 13 DDRB_MA12 13 DDRB_MA13 13 DDRB_BG1 13 DDRB_ACT# 13 DDRA_MA10_AP 12 DDRA_MA11 12 DDRA_MA12 12 DDRA_MA13 12 DDRA_BG1 12 DDRA_ALERT# 12 DDRA_PARITY 12 DDRB_ALERT# 13 DDRB_PARITY 13 DDRA_DQS#[0..7] 12 DDRA_DQS[0..7] 12 DDRA_ACT# 12 +VREF_DQ_DIMMB_R +VREF_CA_DIMMA_R Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (3/7) DDRVI C 7 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (3/7) DDRVI C 7 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (3/7) DDRVI C 7 75 Friday, November 25, 2016 2015/02/26 2016/02/26 RC6 75_0402_1% 1 2 RC147 0_0402_5% 1 2 RC36 0_0402_5% @ 1 2 RC37 0_0402_5% 1 2 RC8 100_0402_1% 1 2 TC109 PAD @ 1 DDR CHANNEL A SKYLAKE_HALO BGA1440 1 OF 14 UC1A SKYLAKE-H-CPU_BGA1440 @ DDR0_DQ[36]/DDR1_DQ[4] AB5 DDR0_DQ[35]/DDR1_DQ[3] AA5 DDR0_DQ[34]/DDR1_DQ[2] AA4 DDR0_DQ[32]/DDR1_DQ[0] AB1 DDR0_DQ[31]/DDR0_DQ[47] BC2 DDR0_DQ[30]/DDR0_DQ[46] BC1 DDR0_DQ[45]/DDR1_DQ[13] V4 DDR0_ECC[6] AY1 DDR0_DQ[63]/DDR1_DQ[47] L1 DDR0_DQ[54]/DDR1_DQ[38] R1 DDR0_DQ[55]/DDR1_DQ[39] P1 DDR0_DQ[43]/DDR1_DQ[11] U2 DDR0_DQ[28]/DDR0_DQ[44] BD5 DDR0_DQ[20]/DDR0_DQ[36] BG2 DDR0_DQ[19]/DDR0_DQ[35] BF5 DDR0_DQ[16]/DDR0_DQ[32] BG4 DDR0_ECC[4] BA5 DDR0_DQ[60]/DDR1_DQ[44] M5 DDR0_DQ[4] BN5 DDR0_DQ[2] BP3 DDR0_DQ[3] BR3 DDR0_DQ[5] BP6 DDR0_DQ[6] BP2 DDR0_DQ[7] BN3 DDR0_DQ[8] BL4 DDR0_DQ[9] BL5 DDR0_DQ[10] BL2 DDR0_DQ[11] BM1 DDR0_DQ[13] BK5 DDR0_DQ[14] BK1 DDR0_DQ[18]/DDR0_DQ[34] BF4 DDR0_DQ[21]/DDR0_DQ[37] BG1 DDR0_DQ[23]/DDR0_DQ[39] BF2 DDR0_DQ[25]/DDR0_DQ[41] BD1 DDR0_DQ[27]/DDR0_DQ[43] BC5 DDR0_DQ[29]/DDR0_DQ[45] BD4 DDR0_DQ[12] BK4 DDR0_DQ[17]/DDR0_DQ[33] BG5 DDR0_DQ[15] BK2 DDR0_CKP[0] AG1 DDR0_DQ[42]/DDR1_DQ[10] U1 DDR0_DQ[41]/DDR1_DQ[9] V2 DDR0_DQ[40]/DDR1_DQ[8] V5 DDR0_DQ[37]/DDR1_DQ[5] AB4 DDR0_DQ[33]/DDR1_DQ[1] AB2 DDR0_DQ[26]/DDR0_DQ[42] BC4 DDR0_DQ[22]/DDR0_DQ[38] BF1 DDR0_ECC[3] AY5 DDR0_DQ[58]/DDR1_DQ[42] L4 DDR0_DQ[52]/DDR1_DQ[36] R5 DDR0_DQ[47]/DDR1_DQ[15] U4 DDR0_DQ[44]/DDR1_DQ[12] V1 DDR0_DQ[39]/DDR1_DQ[7] AA1 DDR0_DQSP[8] AY3 DDR0_DQSN[8] BA3 DDR0_DQSN[7]/DDR1_DQSN[5] L3 DDR0_DQSN[6]/DDR1_DQSN[4] P3 DDR0_DQSN[5]/DDR1_DQSN[1] U3 DDR0_DQSN[4]/DDR1_DQSN[0] AA3 DDR0_DQSP[3]/DDR0_DQSP[5] BC3 DDR0_DQSP[2]/DDR0_DQSP[4] BF3 DDR0_DQSP[1] BK3 DDR0_DQSP[0] BP5 DDR0_DQSP[7]/DDR1_DQSP[5] M3 DDR0_DQSP[5]/DDR1_DQSP[1] V3 DDR0_DQSP[6]/DDR1_DQSP[4] R3 DDR0_DQSN[3]/DDR0_DQSN[5] BD3 DDR0_DQSP[4]/DDR1_DQSP[0] AB3 DDR0_DQSN[1] BL3 DDR0_DQSN[2]/DDR0_DQSN[4] BG3 DDR0_DQSN[0] BR5 DDR0_PAR AG3 DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU2 DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AU3 DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AE3 DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AU4 DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] AN2 DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AN3 DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AT4 DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AH2 DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AP3 DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AN1 DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AP1 DDR0_MA[4] AP2 DDR0_MA[3] AP5 DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AN4 DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AP4 DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AH3 DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AD1 DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AG4 DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AH4 DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AU1 DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AH1 DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AH5 DDR0_ODT[3] AD4 DDR0_ODT[2] AE1 DDR0_ODT[1] AE4 DDR0_CS#[3] AE5 DDR0_ODT[0] AD3 DDR0_CS#[2] AD2 DDR0_CS#[1] AE2 DDR0_CKE[3] AT5 DDR0_CS#[0] AD5 DDR0_CKE[1] AT2 DDR0_CKE[2] AT3 DDR0_CKE[0] AT1 DDR0_CLKN[3] AL1 DDR0_CLKN[2] AK3 DDR0_CLKP[3] AL2 DDR0_CLKP[2] AL3 DDR0_CKP[1] AK2 DDR0_CKN[1] AK1 DDR0_CKN[0] AG2 DDR0_ECC[7] AY2 DDR0_ECC[5] BA4 DDR0_ECC[2] AY4 DDR0_ECC[1] BA1 DDR0_ECC[0] BA2 DDR0_DQ[62]/DDR1_DQ[46] L5 DDR0_DQ[61]/DDR1_DQ[45] M2 DDR0_DQ[59]/DDR1_DQ[43] L2 DDR0_DQ[56]/DDR1_DQ[40] M4 DDR0_DQ[57]/DDR1_DQ[41] M1 DDR0_DQ[53]/DDR1_DQ[37] P2 DDR0_DQ[51]/DDR1_DQ[35] P4 DDR0_DQ[50]/DDR1_DQ[34] R4 DDR0_DQ[49]/DDR1_DQ[33] P5 DDR0_DQ[48]/DDR1_DQ[32] R2 DDR0_DQ[46]/DDR1_DQ[14] U5 DDR0_DQ[38]/DDR1_DQ[6] AA2 DDR0_DQ[24]/DDR0_DQ[40] BD2 DDR0_ALERT# AU5 DDR0_DQ[1] BT6 DDR0_DQ[0] BR6 RC5 121_0402_1% 1 2 DDR CHANNEL B BGA1440 SKYLAKE_HALO 2 OF 14 UC1B SKYLAKE-H-CPU_BGA1440 @ DDR1_DQ[0]/DDR0_DQ[16] BT11 DDR1_DQ[3]/DDR0_DQ[19] BR8 DDR1_DQ[4]/DDR0_DQ[20] BP11 DDR1_DQ[5]/DDR0_DQ[21] BN11 DDR1_DQ[6]/DDR0_DQ[22] BP8 DDR1_DQ[7]/DDR0_DQ[23] BN8 DDR1_DQ[8]/DDR0_DQ[24] BL12 DDR1_DQ[9]/DDR0_DQ[25] BL11 DDR1_DQ[11]/DDR0_DQ[27] BJ8 DDR1_DQ[12]/DDR0_DQ[28] BJ11 DDR1_DQ[14]/DDR0_DQ[30] BL7 DDR1_DQ[15]/DDR0_DQ[31] BJ7 DDR1_DQ[2]/DDR0_DQ[18] BT8 DDR1_DQ[1]/DDR0_DQ[17] BR11 DDR1_ECC[3] AW8 DDR1_ECC[4] AY10 DDR1_ECC[5] AW10 DDR1_ECC[6] AY7 DDR1_ECC[7] AW7 DDR1_DQ[61] M10 DDR1_DQ[60] L10 DDR1_DQ[59] M8 DDR1_DQ[58] L7 DDR1_DQ[57] M11 DDR1_DQ[56] L11 DDR1_DQ[55] P8 DDR1_DQ[54] R7 DDR1_DQ[53] P10 DDR1_ODT[0] AF7 DDR1_CS#[3] AE10 DDR1_CS#[2] AF10 DDR1_ODT[1] AE8 DDR1_ODT[2] AE9 DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] AH10 DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AH9 DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] AJ9 DDR1_DQSN[6] R9 DDR0_VREF_DQ BP13 DDR_VREF_CA BN13 DDR1_DQSN[5]/DDR1_DQSN[3] W9 DDR1_PAR AJ7 DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AT9 DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] AR7 DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AF9 DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN11 DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AR10 DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AH7 DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AN8 DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AR11 DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN10 DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN7 DDR1_MA[3] AL5 DDR1_MA[4] AL6 DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AM6 DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AK5 DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AK6 DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AR9 DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AH8 DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AH11 DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AF8 DDR1_ODT[3] AE11 DDR1_CS#[1] AE7 DDR1_CKE[3] AT11 DDR1_CS#[0] AF11 DDR1_CKE[2] AT7 DDR1_CKE[1] AT10 DDR1_CKE[0] AT8 DDR1_CLKN[3] AJ11 DDR1_CLKP[3] AJ10 DDR1_CLKN[2] AM10 DDR1_CLKP[2] AM11 DDR1_CKP[1] AM7 DDR1_CKN[1] AM8 DDR1_CKP[0] AM9 DDR1_CKN[0] AN9 DDR1_ECC[2] AY8 DDR1_ECC[1] AY11 DDR1_ECC[0] AW11 DDR1_DQ[63] L8 DDR1_DQ[62] M7 DDR1_DQ[51] R8 DDR1_DQ[52] R10 DDR1_DQ[50] P7 DDR1_DQ[49] P11 DDR1_DQ[48] R11 DDR1_DQ[46]/DDR1_DQ[30] V7 DDR1_DQ[47]/DDR1_DQ[31] V8 DDR1_DQ[45]/DDR1_DQ[29] W10 DDR1_DQ[43]/DDR1_DQ[27] V11 DDR1_DQ[44]/DDR1_DQ[28] W11 DDR1_DQ[40]/DDR1_DQ[24] W8 DDR1_DQ[42]/DDR1_DQ[26] V10 DDR1_DQ[41]/DDR1_DQ[25] W7 DDR1_DQ[39]/DDR1_DQ[23] AC7 DDR1_DQ[38]/DDR1_DQ[22] AC8 DDR1_DQ[37]/DDR1_DQ[21] AA8 DDR1_DQ[29]/DDR0_DQ[61] BB10 DDR1_DQ[23]/DDR0_DQ[55] BF7 DDR1_DQ[20]/DDR0_DQ[52] BF11 DDR1_DQ[21]/DDR0_DQ[53] BF10 DDR1_DQ[17]/DDR0_DQ[49] BG10 DDR1_DQ[18]/DDR0_DQ[50] BG8 DDR1_DQ[16]/DDR0_DQ[48] BG11 DDR1_DQ[13]/DDR0_DQ[29] BJ10 DDR1_DQ[10]/DDR0_DQ[26] BL8 DDR1_DQ[19]/DDR0_DQ[51] BF8 DDR1_DQ[26]/DDR0_DQ[58] BB8 DDR1_VREF_DQ BR13 DDR1_DQSN[8] AY9 DDR1_DQSP[8] AW9 DDR1_DQSP[7] L9 DDR1_DQSP[6] P9 DDR1_DQSP[5]/DDR1_DQSP[3] V9 DDR1_DQSP[4]/DDR1_DQSP[2] AA9 DDR1_DQSP[3]/DDR0_DQSP[7] BB9 DDR1_DQSP[2]/DDR0_DQSP[6] BF9 DDR1_DQSP[1]/DDR0_DQSP[3] BJ9 DDR1_DQSP[0]/DDR0_DQSP[2] BR9 DDR1_DQSN[7] M9 DDR1_DQSN[4]/DDR1_DQSN[2] AC9 DDR1_DQSN[3]/DDR0_DQSN[7] BC9 DDR1_DQSN[2]/DDR0_DQSN[6] BG9 DDR1_DQSN[1]/DDR0_DQSN[3] BL9 DDR1_DQSN[0]/DDR0_DQSN[2] BP9 DDR1_ALERT# AR8 DDR1_DQ[36]/DDR1_DQ[20] AA7 DDR1_DQ[35]/DDR1_DQ[19] AC10 DDR1_DQ[34]/DDR1_DQ[18] AC11 DDR1_DQ[33]/DDR1_DQ[17] AA10 DDR1_DQ[32]/DDR1_DQ[16] AA11 DDR1_DQ[31]/DDR0_DQ[63] BB7 DDR1_DQ[30]/DDR0_DQ[62] BC7 DDR1_DQ[28]/DDR0_DQ[60] BC10 DDR1_DQ[27]/DDR0_DQ[59] BC8 DDR1_DQ[25]/DDR0_DQ[57] BC11 DDR1_DQ[24]/DDR0_DQ[56] BB11 DDR1_DQ[22]/DDR0_DQ[54] BG7 DDR_RCOMP[0] G1 DDR_RCOMP[1] H1 DDR_RCOMP[2] J2
  • 8. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A COMPENSATION PU FOR eDP CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils. Need create 5% P/N Place near CPU. Delete eDP Lane2&3 HLZ SDV 20160510 HDMI D1 HDMI D0 HDMI CLK HDMI D2 Type C DP Different to Y710 HLZ SDV 20160510 Reserved Cap HLZ SDV 0616 CPU_EDP_AUX# CPU_EDP_AUX EDP_COMP CPU_EDP_TX0- CPU_EDP_TX0+ CPU_EDP_TX1- CPU_EDP_TX1+ PROC_AUDIO_SDO_CPU PROC_AUDIO_SDI_CPU_R PROC_AUDIO_CLK_CPU TYPE-C_DP_TXN2 TYPE-C_DP_TXN1 TYPE-C_DP_TXN3 TYPE-C_DP_TXP3 TYPE-C_DP_TXN0 TYPE-C_DP_AUXN TYPE-C_DP_AUXP TYPE-C_DP_TXP2 TYPE-C_DP_TXP1 TYPE-C_DP_TXP0 HDMI_TXC+ HDMI_TXC- HDMI_TX0+ HDMI_TX1+ HDMI_TX2+ HDMI_TX2- HDMI_TX0- HDMI_TX1- PROC_AUDIO_SDO_CPU CPU_EDP_AUX# 35 CPU_EDP_AUX 35 CPU_EDP_TX0- 35 CPU_EDP_TX0+ 35 CPU_EDP_TX1- 35 CPU_EDP_TX1+ 35 PROC_AUDIO_SDI_CPU 16 PROC_AUDIO_CLK_CPU 16 PROC_AUDIO_SDO_CPU 16 TYPE-C_DP_AUXP 37 TYPE-C_DP_AUXN 37 TYPE-C_DP_TXN3 37 TYPE-C_DP_TXP3 37 TYPE-C_DP_TXN2 37 TYPE-C_DP_TXP2 37 TYPE-C_DP_TXN1 37 TYPE-C_DP_TXP1 37 TYPE-C_DP_TXP0 37 TYPE-C_DP_TXN0 37 HDMI_TX2+ 36 HDMI_TX2- 36 HDMI_TX1+ 36 HDMI_TX1- 36 HDMI_TX0+ 36 HDMI_TX0- 36 HDMI_TXC+ 36 HDMI_TXC- 36 VCCIO Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (4/7) eDP, DDI Custom 8 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (4/7) eDP, DDI Custom 8 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (4/7) eDP, DDI Custom 8 75 Friday, November 25, 2016 2015/02/26 2016/02/26 CH14 10P_0402_50V8J @ 1 2 RC49 24.9_0402_1% 1 2 RC180 20_0402_1% 1 2 RH762 33_0402_5% @ 1 2 SKYLAKE_HALO BGA1440 4 OF 14 UC1D SKYLAKE-H-CPU_BGA1440 @ DDI1_TXN[3] J38 EDP_TXN[1] E28 EDP_TXN[2] B29 EDP_TXP[2] A29 DDI1_TXN[2] H36 DDI1_TXP[3] J37 EDP_TXP[0] D29 EDP_TXN[0] E29 EDP_TXP[1] F28 EDP_TXN[3] B28 EDP_TXP[3] C28 EDP_AUXP C26 EDP_AUXN B26 EDP_DISP_UTIL A33 EDP_RCOMP D37 PROC_AUDIO_CLK G27 PROC_AUDIO_SDI G25 PROC_AUDIO_SDO G29 DDI1_AUXP D27 DDI2_TXN[2] F35 DDI2_TXP[3] E37 DDI2_TXP[2] F34 DDI2_TXN[1] G38 DDI2_TXP[1] F37 DDI2_TXN[0] H33 DDI2_TXP[0] H34 DDI1_AUXN E27 DDI2_TXN[3] E36 DDI2_AUXN E26 DDI2_AUXP F26 DDI3_TXP[0] C34 DDI3_TXN[0] D34 DDI3_TXP[1] B36 DDI3_TXN[1] B34 DDI3_TXP[2] F33 DDI3_TXN[2] E33 DDI3_TXP[3] C33 DDI3_TXN[3] B33 DDI3_AUXN B27 DDI3_AUXP A27 DDI1_TXP[0] K36 DDI1_TXN[0] K37 DDI1_TXP[1] J35 DDI1_TXN[1] J34 DDI1_TXP[2] H37 CH264 10P_0402_50V8J @ 1 2 WWW.AliSaler.Com
  • 9. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A VCC_SENSE CAD Note: RC39 SHOULD BE PLACED CLOSE TO CPU CAD Note: RC38 SHOULD BE PLACED CLOSE TO CPU VCCGT_SENSE CRB place to CPU CRB place to CPU 10uF 28pcs 1uF 64pcs 10uF 35pcs 1uF 68pcs Near CPU Near CPU MAX 68A MAX 55A SDV Cost down list: 10U 10Pcs 1U 28Pcs Cost down list: 10U 5Pcs 1U 19Pcs SIV Cost down list: 10U 9Pcs 1U 19Pcs Change CH109&CH110&CH135&CH140 from stuff to@ Change CH93&CH122&CH105&CH150 from @ to stuff HLZ SIV 0811 VSSSENSE_R VCCSENSE_R VCCGT_SENSE_R VSSGT_SENSE_R VCCSENSE_R VSSSENSE_R VSSGT_SENSE_R VCCGT_SENSE_R VSSCORE_SENSE 65 VCCCORE_SENSE 65 VSSGT_SENSE 65 VCCGT_SENSE 65 VCCCPUCORE VCCCPUCORE VCCCPUCORE VCCCPUCORE VCCGFXCORE VCCGFXCORE VCCGFXCORE VCCGFXCORE VCCGFXCORE VCCGFXCORE Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (5/7) PWR, BYPASS D 9 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (5/7) PWR, BYPASS D 9 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (5/7) PWR, BYPASS D 9 75 Friday, November 25, 2016 2015/02/26 2016/02/26 CH147 1U_0201_6.3V6K 1 2 CH205 1U_0201_6.3V6K 1 2 CH115 1U_0201_6.3V6K 1 2 RC63 100_0402_1% 1 2 CH104 1U_0201_6.3V6K @ 1 2 CH122 1U_0201_6.3V6K @ 1 2 CC113 10U_0402_6.3V6M 1 2 CH154 1U_0201_6.3V6K 1 2 CH235 1U_0201_6.3V6K 1 2 CC76 10U_0402_6.3V6M 1 2 CD77 33P_0402_50V8J RF_NS@ 1 2 RC59 100_0402_1% 1 2 CC132 10U_0402_6.3V6M @ 1 2 CH135 1U_0201_6.3V6K 1 2 CC88 10U_0402_6.3V6M @ 1 2 CC111 10U_0402_6.3V6M 1 2 CH206 1U_0201_6.3V6K 1 2 CH182 1U_0201_6.3V6K @ 1 2 CH148 1U_0201_6.3V6K 1 2 CH116 1U_0201_6.3V6K 1 2 CH218 1U_0201_6.3V6K 1 2 CH105 1U_0201_6.3V6K @ 1 2 CH123 1U_0201_6.3V6K 1 2 CC77 10U_0402_6.3V6M 1 2 CH155 1U_0201_6.3V6K 1 2 CH136 1U_0201_6.3V6K 1 2 TC60 PAD @ 1 CH194 1U_0201_6.3V6K @ 1 2 CH170 1U_0201_6.3V6K @ 1 2 SKYLAKE_HALO BGA1440 14 OF 14 UC1N SKYLAKE-H-CPU_BGA1440 @ VCCGT_189 AU38 VCCGT_188 AU37 VCCGT_187 AU36 VCCGT_186 AU35 VCCGT_185 AU32 VCCGT_184 AU31 VCCGT_183 AU30 VCCGT_182 AU29 VCCGT_181 AU14 VCCGT_180 AT38 VCCGT_179 AT37 VCCGT_178 AT36 VCCGT_177 AT35 VCCGT_176 AT34 VCCGT_175 AT33 VCCGT_174 AT32 VCCGT_173 AT31 VCCGT_172 AT14 VCCGT_171 AR36 VCCGT_170 AR35 VCCGT_169 AR34 VCCGT_168 AR33 VCCGT_167 AR32 VCCGT_166 AR31 VCCGT_165 AR30 VCCGT_164 AR29 VCCGT_163 AP38 VCCGT_162 AP37 VCCGT_161 AP36 VCCGT_160 AP35 VCCGT_159 AP32 VCCGT_158 AP31 VCCGT_157 AP30 VCCGT_156 AP29 VCCGT_155 AP14 VCCGT_154 AP13 VCCGT_153 AN38 VCCGT_152 AN37 VCCGT_151 AN36 VCCGT_150 AN35 VCCGT_149 AN34 VCCGT_148 AN33 VCCGT_147 AN32 VCCGT_146 AN31 VCCGT_145 AN14 VCCGT_144 AN13 VCCGT_143 AM36 VCCGT_142 AM35 VCCGT_141 AM34 VCCGT_140 AM33 VCCGT_139 AM32 VCCGT_138 AM31 VCCGT_137 AM30 VCCGT_136 AM29 VCCGT_135 AM14 VCCGT_134 AM13 VCCGT_133 AL38 VCCGT_132 AL37 VCCGT_131 AL36 VCCGT_130 AL35 VCCGT_129 AL32 VCCGT_128 AL31 VCCGT_127 AL30 VCCGT_126 AL29 VCCGT_125 AL13 VCCGT_124 AK38 VCCGT_123 AK37 VCCGT_122 AK36 VCCGT_121 AK35 VCCGT_120 AK34 VCCGT_119 AK33 VCCGT_118 AK32 VCCGT_117 AK31 VCCGT_116 AJ36 VCCGT_115 AJ35 VCCGT_114 AJ34 VCCGT_113 AJ33 VCCGT_112 AJ32 VCCGT_111 AJ31 VCCGT_110 AJ30 VCCGT_109 AJ29 VCCGTX_22 AJ14 VCCGTX_21 AJ13 VCCGT_SENSE AH38 VSSGT_SENSE AH37 VCCGTX_SENSE AH36 VSSGTX_SENSE AH35 VCCGTX_20 AH32 VCCGTX_19 AH31 VCCGTX_18 AH30 VCCGTX_17 AH29 VCCGTX_16 AH14 VCCGTX_15 AH13 VCCGTX_14 AG36 VCCGTX_13 AG35 VCCGTX_12 AG34 VCCGTX_11 AG33 VCCGTX_10 AG32 VCCGTX_9 AG31 VCCGTX_8 AG14 VCCGTX_7 AG13 VCCGTX_6 AF34 VCCGTX_5 AF33 VCCGTX_4 AF32 VCCGTX_3 AF31 VCCGTX_2 AF30 VCCGTX_1 AF29 CC90 10U_0402_6.3V6M @ 1 2 CH96 1U_0201_6.3V6K 1 2 CC112 10U_0402_6.3V6M @ 1 2 CH106 1U_0201_6.3V6K 1 2 CH158 1U_0201_6.3V6K @ 1 2 CH124 1U_0201_6.3V6K 1 2 CC115 10U_0402_6.3V6M 1 2 CD78 33P_0402_50V8J RF_NS@ 1 2 CH156 1U_0201_6.3V6K 1 2 CC78 10U_0402_6.3V6M 1 2 CC134 10U_0402_6.3V6M 1 2 CH195 1U_0201_6.3V6K @ 1 2 RC62 100_0402_1% 1 2 CH137 1U_0201_6.3V6K 1 2 CC91 10U_0402_6.3V6M 1 2 CH208 1U_0201_6.3V6K 1 2 CH184 1U_0201_6.3V6K @ 1 2 RC41 0_0402_5% 1 2 RC60 100_0402_1% 1 2 CH220 1U_0201_6.3V6K @ 1 2 CH107 1U_0201_6.3V6K 1 2 CH159 1U_0201_6.3V6K @ 1 2 CH125 1U_0201_6.3V6K @ 1 2 CC116 10U_0402_6.3V6M @ 1 2 CC79 10U_0402_6.3V6M @ 1 2 CH138 1U_0201_6.3V6K 1 2 CH117 1U_0201_6.3V6K 1 2 CH196 1U_0201_6.3V6K @ 1 2 CH172 1U_0201_6.3V6K @ 1 2 CC92 10U_0402_6.3V6M 1 2 CH185 1U_0201_6.3V6K 1 2 CH160 1U_0201_6.3V6K @ 1 2 CH126 1U_0201_6.3V6K @ 1 2 CH108 1U_0201_6.3V6K 1 2 CH97 1U_0201_6.3V6K 1 2 CC80 10U_0402_6.3V6M 1 2 CH197 1U_0201_6.3V6K @ 1 2 CH173 1U_0201_6.3V6K 1 2 CH139 1U_0201_6.3V6K 1 2 CC123 10U_0402_6.3V6M 1 2 CH118 1U_0201_6.3V6K 1 2 CC103 10U_0402_6.3V6M 1 2 CC93 10U_0402_6.3V6M @ 1 2 CH210 1U_0201_6.3V6K @ 1 2 CH161 1U_0201_6.3V6K 1 2 CH127 1U_0201_6.3V6K 1 2 CC118 10U_0402_6.3V6M 1 2 CC81 10U_0402_6.3V6M 1 2 CH98 1U_0201_6.3V6K @ 1 2 CH119 1U_0201_6.3V6K @ 1 2 CH140 1U_0201_6.3V6K 1 2 CC124 10U_0402_6.3V6M 1 2 CC95 10U_0402_6.3V6M @ 1 2 CC102 10U_0402_6.3V6M @ 1 2 CC104 10U_0402_6.3V6M @ 1 2 CH186 1U_0201_6.3V6K @ 1 2 CH128 1U_0201_6.3V6K 1 2 CC119 10U_0402_6.3V6M 1 2 CH99 1U_0201_6.3V6K @ 1 2 CC82 10U_0402_6.3V6M 1 2 CH141 1U_0201_6.3V6K 1 2 CC125 10U_0402_6.3V6M 1 2 CH120 1U_0201_6.3V6K @ 1 2 CH109 1U_0201_6.3V6K 1 2 CC94 10U_0402_6.3V6M 1 2 RC38 0_0402_5% 1 2 CH187 1U_0201_6.3V6K 1 2 CH129 1U_0201_6.3V6K @ 1 2 CC120 10U_0402_6.3V6M 1 2 CC83 10U_0402_6.3V6M 1 2 CH100 1U_0201_6.3V6K 1 2 CH200 1U_0201_6.3V6K 1 2 CH142 1U_0201_6.3V6K 1 2 CC97 10U_0402_6.3V6M 1 2 CH110 1U_0201_6.3V6K 1 2 CC106 10U_0402_6.3V6M 1 2 CH149 1U_0201_6.3V6K 1 2 CH164 1U_0201_6.3V6K @ 1 2 CH130 1U_0201_6.3V6K 1 2 CC121 10U_0402_6.3V6M @ 1 2 CH188 1U_0201_6.3V6K 1 2 CC84 10U_0402_6.3V6M 1 2 CH143 1U_0201_6.3V6K @ 1 2 CC127 10U_0402_6.3V6M @ 1 2 TC62 PAD @ 1 CH201 1U_0201_6.3V6K 1 2 CH213 1U_0201_6.3V6K 1 2 CC173 10U_0402_6.3V6M 1 2 CH111 1U_0201_6.3V6K @ 1 2 CH150 1U_0201_6.3V6K @ 1 2 CC107 10U_0402_6.3V6M @ 1 2 CH121 1U_0201_6.3V6K 1 2 CH165 1U_0201_6.3V6K @ 1 2 CH131 1U_0201_6.3V6K 1 2 CC85 10U_0402_6.3V6M 1 2 CH94 1U_0201_6.3V6K 1 2 CH202 1U_0201_6.3V6K 1 2 CD75 33P_0402_50V8J RF_NS@ 1 2 CH144 1U_0201_6.3V6K 1 2 CC128 10U_0402_6.3V6M @ 1 2 CC100 10U_0402_6.3V6M 1 2 CH112 1U_0201_6.3V6K 1 2 CH101 1U_0201_6.3V6K @ 1 2 CC108 10U_0402_6.3V6M 1 2 CC62 10U_0402_6.3V6M 1 2 CH151 1U_0201_6.3V6K @ 1 2 CH132 1U_0201_6.3V6K @ 1 2 BGA1440 SKYLAKE_HALO 7 OF 14 UC1G SKYLAKE-H-CPU_BGA1440 @ VCC_126 P14 VCC_125 V31 VCC_123 V13 VCC_124 V14 VCC_122 U36 VCC_118 U32 VCC_117 U31 VCC_119 U33 VCC_120 U34 VCC_121 U35 VCC_113 T37 VCC_112 T36 VCC_116 U30 VCC_115 U29 VCC_107 T29 VCC_111 T35 VCC_110 T32 VCC_106 R38 VCC_103 R35 VCC_104 R36 VCC_102 R34 VCC_105 R37 VCC_101 R33 VCC_99 R31 VCC_98 R13 VCC_97 P36 VCC_100 R32 VCC_92 P31 VCC_91 P30 VCC_90 P29 VCC_82 Y30 VCC_83 Y31 VCC_81 Y29 VCC_78 W36 VCC_77 W35 VCC_76 W32 VCC_80 W38 VCC_73 W29 VCC_75 W31 VCC_74 W30 VCC_67 V35 VCC_68 V36 VCC_63 P13 VCC_61 N37 VCC_62 N38 VCC_60 N36 VCC_59 N35 VCC_58 N32 VCC_57 N31 VCC_56 N30 VCC_55 N14 VCC_54 N13 VCC_53 L13 VCC_50 AF38 VCC_51 K13 VCC_52 K14 VCC_49 AF37 VCC_48 AF36 VCC_47 AF35 VCC_46 AE38 VCC_45 AE37 VCC_31 AD32 VSS_SENSE AG38 VCC_SENSE AG37 VCC_27 AC36 VCC_28 AD13 VCC_29 AD14 VCC_30 AD31 VCC_32 AD33 VCC_33 AD34 VCC_34 AD35 VCC_35 AD36 VCC_36 AD37 VCC_37 AD38 VCC_38 AE13 VCC_39 AE14 VCC_40 AE30 VCC_41 AE31 VCC_42 AE32 VCC_44 AE36 VCC_43 AE35 VCC_109 T31 VCC_108 T30 VCC_89 L14 VCC_84 Y32 VCC_85 Y33 VCC_86 Y34 VCC_87 Y35 VCC_88 Y36 VCC_93 P32 VCC_94 P33 VCC_95 P34 VCC_96 P35 VCC_66 V34 VCC_64 V32 VCC_114 T38 VCC_79 W37 VCC_65 V33 VCC_72 W14 VCC_12 AB31 VCC_13 AB32 VCC_21 AC30 VCC_23 AC32 VCC_24 AC33 VCC_25 AC34 VCC_26 AC35 VCC_16 AB37 VCC_17 AB38 VCC_18 AC13 VCC_19 AC14 VCC_20 AC29 VCC_22 AC31 VCC_70 V38 VCC_69 V37 VCC_71 W13 VCC_11 AB30 VCC_10 AB29 VCC_9 AA38 VCC_8 AA37 VCC_6 AA35 VCC_5 AA34 VCC_4 AA33 VCC_3 AA32 VCC_2 AA31 VCC_1 AA13 VCC_7 AA36 VCC_15 AB36 VCC_14 AB35 CH190 1U_0201_6.3V6K 1 2 CC87 10U_0402_6.3V6M 1 2 RC39 0_0402_5% 1 2 BGA1440 SKYLAKE_HALO 8 OF 14 UC1H SKYLAKE-H-CPU_BGA1440 @ VCCGT_98 BB37 VCCGT_96 BB35 VCCGT_95 BB34 VCCGT_93 BB32 VCCGT_84 BA31 VCCGT_83 BA30 VCCGT_82 BA29 VCCGT_81 BA14 VCCGT_56 AV30 VCCGT_55 AV29 VCCGT_57 AV31 VCCGT_58 AV32 VCCGT_59 AV33 VCCGT_61 AV35 VCCGT_60 AV34 VCCGT_62 AV36 VCCGT_63 AW14 VCCGT_64 AW31 VCCGT_66 AW33 VCCGT_65 AW32 VCCGT_67 AW34 VCCGT_68 AW35 VCCGT_69 AW36 VCCGT_70 AW37 VCCGT_71 AW38 VCCGT_79 AY38 VCCGT_80 BA13 VCCGT_86 BA33 VCCGT_88 BA35 VCCGT_89 BA36 VCCGT_90 BB13 VCCGT_92 BB31 VCCGT_91 BB14 VCCGT_94 BB33 VCCGT_97 BB36 VCCGT_100 BC29 VCCGT_99 BB38 VCCGT_101 BC30 VCCGT_102 BC31 VCCGT_103 BC32 VCCGT_104 BC35 VCCGT_39 BC36 VCCGT_40 BC37 VCCGT_41 BC38 VCCGT_42 BD13 VCCGT_44 BD29 VCCGT_43 BD14 VCCGT_45 BD30 VCCGT_46 BD31 VCCGT_47 BD32 VCCGT_48 BD33 VCCGT_49 BD34 VCCGT_50 BD35 VCCGT_52 BE31 VCCGT_51 BD36 VCCGT_53 BE32 VCCGT_105 BE33 VCCGT_106 BE34 VCCGT_108 BE36 VCCGT_107 BE35 VCCGT_72 AY29 VCCGT_73 AY30 VCCGT_74 AY31 VCCGT_76 AY35 VCCGT_87 BA34 VCCGT_2 BG35 VCCGT_1 BG34 VCCGT_3 BG36 VCCGT_4 BH33 VCCGT_5 BH34 VCCGT_7 BH36 VCCGT_6 BH35 VCCGT_9 BH38 VCCGT_8 BH37 VCCGT_10 BJ37 VCCGT_12 BL36 VCCGT_11 BJ38 VCCGT_14 BM36 VCCGT_13 BL37 VCCGT_15 BM37 VCCGT_17 BN37 VCCGT_16 BN36 VCCGT_19 BP37 VCCGT_22 BT37 VCCGT_23 BE38 VCCGT_25 BF14 VCCGT_24 BF13 VCCGT_26 BF29 VCCGT_27 BF30 VCCGT_28 BF31 VCCGT_30 BF35 VCCGT_29 BF32 VCCGT_31 BF36 VCCGT_37 BG32 VCCGT_36 BG31 VCCGT_38 BG33 VCCGT_34 BG29 VCCGT_35 BG30 VCCGT_85 BA32 VCCGT_18 BN38 VCCGT_20 BP38 VCCGT_21 BR37 VCCGT_75 AY32 VCCGT_77 AY36 VCCGT_78 AY37 VCCGT_33 BF38 VCCGT_32 BF37 VCCGT_54 BE37 CH145 1U_0201_6.3V6K 1 2 CH203 1U_0201_6.3V6K 1 2 CH215 1U_0201_6.3V6K 1 2 CC99 10U_0402_6.3V6M 1 2 CH113 1U_0201_6.3V6K 1 2 CH102 1U_0201_6.3V6K 1 2 CH152 1U_0201_6.3V6K 1 2 CC109 10U_0402_6.3V6M 1 2 CC74 10U_0402_6.3V6M 1 2 CH157 1U_0201_6.3V6K @ 1 2 CH191 1U_0201_6.3V6K @ 1 2 CH167 1U_0201_6.3V6K 1 2 CH133 1U_0201_6.3V6K 1 2 CD76 33P_0402_50V8J RF_NS@ 1 2 CC86 10U_0402_6.3V6M 1 2 CH204 1U_0201_6.3V6K 1 2 CH180 1U_0201_6.3V6K 1 2 CH146 1U_0201_6.3V6K 1 2 CC101 10U_0402_6.3V6M 1 2 CH114 1U_0201_6.3V6K 1 2 CH103 1U_0201_6.3V6K @ 1 2 CH95 1U_0201_6.3V6K 1 2 CC110 10U_0402_6.3V6M 1 2 CH93 1U_0201_6.3V6K @ 1 2 CC75 10U_0402_6.3V6M 1 2 CH153 1U_0201_6.3V6K 1 2 CC131 10U_0402_6.3V6M 1 2 RC40 0_0402_5% 1 2 CH134 1U_0201_6.3V6K @ 1 2 CH192 1U_0201_6.3V6K 1 2 CH168 1U_0201_6.3V6K @ 1 2 CC89 10U_0402_6.3V6M 1 2
  • 10. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A VCCIO_SENSE CRB place to CPU CRB place to CPU VCCSA_SENSE VDDQ DECOUPLING 1uF 3pcs 10uF 7pcs Near CPU MAX 2.8A MAX 11.1A MAX 5.5A 150mA 20mA 60mA 130mA For Merge VCCSA_SENSE_R VSSSA_SENSE_R VCCIO_SENSE_R VSSIO_SENSE_R VSSIO_SENSE_R VCCIO_SENSE_R VSSSA_SENSE_R VCCSA_SENSE_R VSS_IO_SEN 64 VCC_IO_SEN 64 VSSSA_SENSE 65 VCCSA_SENSE 65 +1.2V VCCSA VCCIO +1.2V VCCST VCCST +1.2V VCCSTG VCCIO VCCSA +1.2V VCCSA Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, BYPASS C 10 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, BYPASS C 10 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, BYPASS C 10 75 Friday, November 25, 2016 2015/02/26 2016/02/26 RC151 100_0402_1% 1 2 CD79 33P_0402_50V8J RF_NS@ 1 2 CC60 10U_0603_6.3V6M 1 2 CC137 10U_0603_6.3V6M 1 2 CH223 1U_0402_6.3V6K 1 2 CC63 22U_0603_6.3V6-M 1 2 TC54 PAD @ 1 CC58 10U_0603_6.3V6M 1 2 CC147 10U_0603_6.3V6M 1 2 TC74 PAD @ 1 CC54 10U_0603_6.3V6M 1 2 CH251 1U_0402_6.3V6K 1 2 CD80 33P_0402_50V8J RF_NS@ 1 2 CC139 10U_0603_6.3V6M 1 2 CH250 1U_0402_6.3V6K 1 2 TC53 PAD @ 1 TC58 PAD @ 1 RC155 100_0402_1% 1 2 CC138 10U_0603_6.3V6M 1 2 CC172 10U_0603_6.3V6M 1 2 CC65 22U_0603_6.3V6-M 1 2 RC150 0_0402_5% 1 2 CC148 10U_0603_6.3V6M 1 2 RC154 0_0402_5% @ 1 2 CC150 1U_0402_6.3V6K 1 2 CC141 10U_0603_6.3V6M 1 2 BGA1440 SKYLAKE_HALO 9 OF 14 UC1I SKYLAKE-H-CPU_BGA1440 @ VCCSTG_2 G30 VCCIO_19 J21 VCCIO_20 J26 VCCIO_21 J27 VCCIO_18 J20 VCCIO_16 J17 VCCIO_17 J19 VCCIO_14 J15 VCCIO_15 J16 VCCIO_13 H27 VCCIO_12 H26 VCCIO_11 H21 VCCIO_9 H19 VCCIO_10 H20 VCCIO_8 H17 VCCIO_7 H16 VCCIO_6 H15 VCCIO_4 G19 VCCIO_5 G21 VCCIO_3 G17 VCCIO_2 G15 VCCIO_1 AG12 VCCSA_20 M34 VCCSA_19 M33 VCCSA_18 M32 VCCSA_17 M31 VCCSA_16 M30 VCCSA_14 L38 VCCSA_15 M29 VCCSA_13 L37 VCCSA_12 L36 VCCSA_10 L32 VCCSA_11 L35 VCCSA_9 L31 VCCSA_8 K35 VCCSA_7 K34 VCCSA_2 K29 VCCSA_1 J30 VCCIO_SENSE H14 VSSIO_SENSE J14 VSSSA_SENSE M37 VCCSA_SENSE M38 VCCPLL_2 J28 VCCPLL_1 H28 VDDQ_7 AJ12 VDDQ_6 AG9 VDDQ_5 AG5 VDDQ_4 AF6 VDDQ_3 AF5 VDDQ_2 AE12 VDDQ_1 AA6 VDDQ_8 AL11 VDDQ_9 AP6 VDDQ_10 AP7 VDDQ_12 AR6 VDDQ_11 AR12 VCCSA_6 K33 VCCSA_5 K32 VCCSA_4 K31 VCCSA_3 K30 VDDQ_13 AT12 VDDQ_15 AY6 VDDQ_14 AW6 VDDQ_16 J5 VDDQ_17 J6 VDDQ_18 K12 VDDQ_19 K6 VDDQ_20 L12 VDDQ_21 L6 VDDQ_22 R6 VDDQ_23 T6 VDDQ_24 W6 VDDQC Y12 VCCPLL_OC_1 BH13 VCCST H30 VCCSTG_1 H29 VCCPLL_OC_2 G11 VCCSA_22 M36 VCCSA_21 M35 TC75 PAD @ 1 RC148 0_0402_5% 1 2 CC140 10U_0603_6.3V6M 1 2 CC149 10U_0603_6.3V6M 1 2 RC152 0_0402_5% @ 1 2 CC136 10U_0603_6.3V6M 1 2 TC76 PAD @ 1 CC59 10U_0603_6.3V6M 1 2 CC142 10U_0603_6.3V6M 1 2 TC45 PAD @ 1 BGA1440 SKYLAKE_HALO 10 OF 14 UC1J SKYLAKE-H-CPU_BGA1440 @ OPC_RCOMP BT29 VCCOPC_6 BK20 VCCOPC_7 BL16 VCCOPC_9 BL18 VCCOPC_8 BL17 VCCOPC_10 BL19 VCCOPC_13 BM17 VCCOPC_12 BL21 RSVD_3 BJ27 RSVD_4 BK23 RSVD_6 BK27 RSVD_7 BL23 RSVD_9 BL25 RSVD_12 BL28 RSVD_11 BL27 VCCEOPIO_1 BP15 VCCEOPIO_3 BT15 RSVD_18 BT16 RSVD_17 BR16 RSVD_16 BP16 RSVD_19 BP17 VSSEOPIO_SENSE BM15 VCCEOPIO_SENSE BN15 VCC_OPC_1P8_1 BM14 VCC_OPC_1P8_2 BL14 RSVD_20 BN16 RSVD_22 BJ36 RSVD_21 BJ35 ZVM# AT13 MSM# AW13 MSM2# AY13 ZVM2# AU13 OPCE_RCOMP BR25 OPCE_RCOMP2 BP25 RSVD_15 BM22 RSVD_14 BL22 VSSOPC_SENSE BM16 RSVD_13 BM24 VCCOPC_2 BJ19 VCCOPC_1 BJ17 VCCOPC_3 BJ20 VCCOPC_4 BK17 VCCOPC_5 BK19 VCCOPC_11 BL20 VCCOPC_14 BN17 RSVD_1 BJ23 RSVD_2 BJ26 RSVD_5 BK26 RSVD_8 BL24 RSVD_10 BL26 VCCOPC_SENSE BL15 VCCEOPIO_2 BR15 CC57 10U_0603_6.3V6M 1 2 CC66 22U_0603_6.3V6-M 1 2 RC149 100_0402_1% 1 2 TC47 PAD @ 1 CC56 10U_0603_6.3V6M 1 2 CC55 10U_0603_6.3V6M 1 2 TC49 PAD @ 1 CH252 1U_0402_6.3V6K 1 2 RC153 100_0402_1% 1 2 TC48 PAD @ 1 CC64 22U_0603_6.3V6-M 1 2 CC53 10U_0603_6.3V6M 1 2 CH221 1U_0402_6.3V6K 1 2 TC51 PAD @ 1 CC51 10U_0603_6.3V6M 1 2 CH242 1U_0402_6.3V6K 1 2 CC52 10U_0603_6.3V6M 1 2 CH249 1U_0402_6.3V6K 1 2 CH222 1U_0402_6.3V6K 1 2 TC52 PAD @ 1 TC56 PAD @ 1 WWW.AliSaler.Com
  • 11. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, VSS C 11 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, VSS C 11 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 CPU (6/7) PWR, VSS C 11 75 Friday, November 25, 2016 2015/02/26 2016/02/26 SKYLAKE_HALO BGA1440 13 OF 14 UC1M SKYLAKE-H-CPU_BGA1440 @ VSS_300 BB4 VSS_301 BB3 VSS_302 BB2 VSS_303 BB1 VSS_304 BA38 VSS_305 BA37 VSS_306 BA12 VSS_307 BA11 VSS_308 BA10 VSS_309 BA9 VSS_310 BA8 VSS_311 BA7 VSS_312 BA6 NCTFVSS_8 B37 VSS_313 B9 NCTFVSS_9 B3 VSS_314 AY34 VSS_315 AY33 VSS_316 AY14 VSS_317 AY12 VSS_318 AW30 VSS_319 AW29 VSS_320 AW12 VSS_321 AW5 VSS_322 AW4 VSS_323 AW3 VSS_324 AW2 VSS_325 AW1 VSS_326 AV38 VSS_327 AV37 VSS_328 AU34 VSS_329 AU33 VSS_330 AU12 VSS_331 AU11 VSS_332 AU10 VSS_333 AU9 VSS_334 AU8 VSS_335 AU7 VSS_336 AU6 VSS_337 AT30 VSS_338 AT29 VSS_339 AT6 VSS_340 AR38 VSS_341 AR37 VSS_342 AR14 VSS_343 AR13 VSS_344 AR5 VSS_345 AR4 VSS_346 AR3 VSS_347 AR2 VSS_348 AR1 VSS_349 AP34 VSS_350 AP33 VSS_351 AP12 VSS_352 AP11 VSS_353 AP10 VSS_354 AP9 VSS_355 AP8 VSS_356 AN30 VSS_357 AN29 VSS_358 AN12 VSS_359 AN6 VSS_360 AN5 VSS_361 AM38 VSS_362 AM37 VSS_363 AM12 VSS_364 AM5 VSS_365 AM4 VSS_366 AM3 VSS_367 AM2 VSS_368 AM1 VSS_369 AL34 VSS_370 AL33 VSS_371 AL14 VSS_372 AL12 VSS_373 AL10 VSS_374 AL9 VSS_375 AL8 VSS_376 AL7 VSS_377 AL4 VSS_378 AK30 VSS_379 AK29 VSS_380 AK4 VSS_381 AJ38 VSS_382 AJ37 VSS_383 AJ6 VSS_384 AJ5 VSS_385 AJ4 VSS_386 AJ3 VSS_387 AJ2 VSS_388 AJ1 VSS_389 AH34 VSS_390 AH33 VSS_391 AH12 VSS_392 AH6 VSS_393 AG30 VSS_394 AG29 VSS_395 AG11 VSS_396 AG10 VSS_397 AG8 VSS_398 AG7 VSS_399 AG6 VSS_400 AF14 VSS_401 AF13 VSS_402 AF12 VSS_403 AF4 VSS_404 AF3 VSS_405 AF2 VSS_406 AF1 VSS_407 AE34 VSS_408 AE33 VSS_409 AE6 VSS_410 AD30 VSS_411 AD29 VSS_412 AD12 VSS_413 AD11 VSS_414 AD10 VSS_415 AD9 VSS_416 AD8 VSS_417 AD7 VSS_418 AD6 VSS_419 AC38 VSS_420 AC37 VSS_421 AC12 VSS_422 AC6 VSS_423 AC5 VSS_424 AC4 VSS_425 AC3 VSS_426 AC2 VSS_427 AC1 VSS_428 AB34 VSS_429 AB33 VSS_430 AB6 VSS_431 AA30 VSS_432 AA29 VSS_433 AA12 NCTFVSS_10 A34 VSS_434 A30 VSS_435 A28 VSS_436 A26 VSS_437 A24 VSS_438 A22 VSS_439 A20 VSS_440 A18 VSS_441 A16 VSS_442 A14 VSS_443 A12 VSS_444 A10 VSS_445 A9 VSS_446 A6 NCTFVSS_11 A4 NCTFVSS_12 A3 SKYLAKE_HALO BGA1440 6 OF 14 UC1F SKYLAKE-H-CPU_BGA1440 @ VSS_106 G9 VSS_111 F36 VSS_116 F23 VSS_122 F11 VSS_5 Y11 VSS_10 W34 VSS_20 V12 VSS_15 W3 VSS_24 T34 VSS_34 T5 VSS_29 T11 VSS_44 P12 VSS_39 R30 VSS_49 N11 VSS_59 N1 VSS_54 N6 VSS_65 L33 VSS_70 K10 VSS_77 K2 VSS_82 J25 VSS_87 J4 VSS_92 H18 VSS_107 G8 VSS_117 F21 VSS_123 F9 VSS_128 F2 VSS_142 D16 VSS_133 E4 VSS_147 D6 VSS_150 C31 VSS_139 D22 VSS_144 D12 VSS_130 E35 VSS_125 F5 VSS_120 F15 VSS_79 J36 VSS_72 K8 VSS_67 L29 VSS_61 M13 VSS_51 N9 VSS_56 N4 VSS_46 N34 VSS_41 R12 VSS_36 T3 VSS_26 T14 VSS_17 W1 VSS_153 U38 VSS_12 W12 VSS_2 Y37 VSS_7 Y9 VSS_146 D9 VSS_152 C27 VSS_91 H22 VSS_96 G26 VSS_101 G18 VSS_6 Y10 VSS_11 W33 VSS_1 Y38 VSS_16 W2 VSS_35 T4 VSS_30 T10 VSS_40 R29 VSS_45 P6 VSS_50 N10 VSS_60 M14 VSS_55 N5 VSS_78 K1 VSS_83 J22 VSS_88 H35 VSS_93 H12 VSS_98 G23 VSS_103 G14 VSS_108 G6 VSS_129 E38 VSS_134 D33 VSS_143 D14 VSS_148 D3 VSS_86 J7 VSS_64 L34 VSS_76 K3 VSS_81 J32 VSS_69 K11 VSS_58 N2 VSS_53 N7 VSS_48 N12 VSS_38 T1 VSS_43 P37 VSS_33 T7 VSS_23 U6 VSS_9 Y7 VSS_14 W4 VSS_4 Y13 VSS_140 D20 VSS_131 E34 VSS_151 C29 VSS_145 D10 VSS_126 F4 VSS_110 G4 VSS_105 G10 VSS_121 F13 VSS_115 F25 VSS_100 G20 VSS_85 J10 VSS_80 J33 VSS_95 G28 VSS_90 H25 VSS_74 K5 VSS_47 N33 VSS_52 N8 VSS_63 M6 VSS_68 K38 VSS_57 N3 VSS_22 U37 VSS_27 T13 VSS_37 T2 VSS_42 P38 VSS_32 T8 VSS_8 Y8 VSS_13 W5 VSS_18 V30 VSS_3 Y14 NCTFVSS_1 D38 VSS_119 F17 VSS_75 K4 VSS_62 M12 VSS_73 K7 VSS_149 C37 VSS_138 D24 VSS_137 D26 VSS_135 D30 VSS_136 D28 VSS_19 V29 VSS_28 T12 VSS_25 T33 VSS_21 V6 VSS_124 F8 VSS_118 F19 VSS_113 F29 VSS_66 L30 VSS_71 K9 VSS_97 G24 VSS_102 G16 VSS_112 F31 VSS_114 F27 VSS_109 G5 VSS_104 G12 VSS_99 G22 VSS_94 H11 VSS_89 H32 VSS_84 J18 VSS_31 T9 VSS_127 F3 VSS_132 E9 VSS_141 D18 SKYLAKE_HALO BGA1440 12 OF 14 UC1L SKYLAKE-H-CPU_BGA1440 @ VSS_239 C25 VSS_240 C23 VSS_241 C21 VSS_242 C19 VSS_154 C17 VSS_243 C15 VSS_155 C13 VSS_244 C11 VSS_156 C9 VSS_245 C8 VSS_246 C5 NCTFVSS_2 C2 NCTFVSS_3 BT36 NCTFVSS_4 BT35 VSS_157 BT32 VSS_158 BT26 VSS_159 BT24 VSS_160 BT21 VSS_161 BT18 VSS_162 BT14 VSS_163 BT12 VSS_164 BT9 VSS_165 BT5 NCTFVSS_5 BT4 NCTFVSS_6 BT3 NCTFVSS_7 BR38 VSS_166 BR36 VSS_167 BR34 VSS_168 BR29 VSS_169 BR26 VSS_170 BR24 VSS_171 BR21 VSS_172 BR18 VSS_173 BR14 VSS_174 BR12 VSS_175 BR7 VSS_176 BP34 VSS_177 BP33 VSS_178 BP29 VSS_179 BP26 VSS_180 BP24 VSS_181 BP21 VSS_182 BP18 VSS_183 BP14 VSS_184 BP12 VSS_185 BP7 VSS_186 BN34 VSS_187 BN31 VSS_188 BN30 VSS_189 BN29 VSS_190 BN24 VSS_191 BN21 VSS_192 BN20 VSS_193 BN19 VSS_194 BN18 VSS_195 BN14 VSS_196 BN12 VSS_197 BN9 VSS_198 BN7 VSS_199 BN4 VSS_200 BN2 VSS_201 BM38 VSS_202 BM35 VSS_247 BM29 VSS_203 BM28 VSS_204 BM27 VSS_205 BM26 VSS_248 BM25 VSS_206 BM23 VSS_207 BM21 VSS_249 BM18 VSS_208 BM13 VSS_209 BM12 VSS_250 BM11 VSS_210 BM9 VSS_251 BM8 VSS_252 BM7 VSS_211 BM6 VSS_253 BM5 VSS_254 BM3 VSS_212 BM2 VSS_255 BL38 VSS_256 BL35 VSS_213 BL29 VSS_257 BL13 VSS_258 BL6 VSS_214 BK29 VSS_259 BK25 VSS_260 BK22 VSS_215 BK15 VSS_216 BK14 VSS_261 BK13 VSS_262 BK6 VSS_217 BJ32 VSS_218 BJ31 VSS_263 BJ30 VSS_264 BJ29 VSS_219 BJ25 VSS_220 BJ22 VSS_265 BJ15 VSS_266 BJ12 VSS_221 BH14 VSS_222 BH12 VSS_267 BH11 VSS_268 BH10 VSS_223 BH9 VSS_224 BH8 VSS_269 BH7 VSS_270 BH6 VSS_225 BH5 VSS_226 BH4 VSS_271 BH3 VSS_272 BH2 VSS_227 BH1 VSS_228 BG38 VSS_273 BG37 VSS_274 BG14 VSS_229 BG13 VSS_230 BG12 VSS_275 BG6 VSS_276 BF34 VSS_231 BF33 VSS_232 BF12 VSS_277 BF6 VSS_278 BE30 VSS_233 BE29 VSS_234 BE6 VSS_279 BE5 VSS_280 BE4 VSS_281 BE3 VSS_282 BE2 VSS_283 BE1 VSS_284 BD38 VSS_285 BD37 VSS_286 BD12 VSS_287 BD11 VSS_288 BD10 VSS_235 BD9 VSS_289 BD8 VSS_290 BD7 VSS_291 BD6 VSS_236 BC34 VSS_292 BC33 VSS_293 BC14 VSS_294 BC13 VSS_237 BC12 VSS_295 BC6 VSS_296 BB30 VSS_297 BB29 VSS_238 BB12 VSS_298 BB6 VSS_299 BB5
  • 12. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Layout Note: Place near DIMM Layout Note: Place near DIMM DDR4 SO-DIMM A Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket Change RD2 to 0ohm jump For EMC SPD Address = 0H Near JDDRL1 Change JDDRL1 from Foxconn to ARGOSY HLZ SDV 20160510 Change DDR4 220u to B2 HLZ SVD 0527 MAX 3A MAX 0.5A MAX 0.5A Change CD81 & CD82 from @ to stuff based on RF requirement HLZ SIT 0924 DDRA_CLK0 DDRA_CLK0# DDRA_CS0# DDRA_CS1# DDRA_CKE0 DDRA_ODT0 DDRA_ODT1 DDRA_MA1 DDRA_MA3 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA12 DDRA_MA11 DDRA_MA14_WE# DDRA_BG0 DDRA_BG1 DDRA_BA1 DDRA_ACT# DDRA_PARITY DDRA_DQS#0 DDRA_DQS0 DDRA_DQS#1 DDRA_DQS1 DDRA_DQS#2 DDRA_DQS2 DDRA_DQS3 DDRA_DQS#3 DDRA_DQS#4 DDRA_DQS4 DDRA_DQS6 DDRA_DQS#6 DDRA_DQ4 DDRA_DQ0 DDRA_DQ7 DDRA_DQ3 DDRA_DQ13 DDRA_DQ12 DDRA_DQ15 DDRA_DQ14 DDRA_DQ21 DDRA_DQ20 DDRA_DQ22 DDRA_DQ18 DDRA_DQ29 DDRA_DQ28 DDRA_DQ27 DDRA_DQ30 DDRA_DQ24 DDRA_DQ23 DDRA_DQ19 DDRA_DQ17 DDRA_DQ16 DDRA_DQ11 DDRA_DQ10 DDRA_DQ8 DDRA_DQ2 DDRA_DQ9 DDRA_DQ6 DDRA_DQ5 DDRA_DQ1 DDRA_DQ33 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ44 DDRA_DQ41 DDRA_DQ43 DDRA_DQ46 DDRA_DQ50 DDRA_DQ52 DDRA_DQ54 DDRA_DQ51 DDRA_DQ57 DDRA_DQ61 DDRA_DQ62 DDRA_DQ58 +VREF_CA_DIMMA PCH_DRAMRST# SMB_CLK_S3 DDRA_VDDSPD DDRA_SA0 DDRA_SA1 DDRA_SA2 DDRA_MA4 DDRA_MA5 DDRA_ALERT# DDRA_CKE1 DDRA_DQ25 DDRA_DQ26 DDRA_DQ31 +VREF_CA_DIMMA DDRA_MA13 DDRA_CLK1 DDRA_CLK1# DDRA_MA2 DDRA_MA0 DDRA_MA10_AP DDRA_MA16_RAS# DDRA_DQS#7 DDRA_DQS7 DDRA_DQ55 DDRA_DQ56 DDRA_DQ60 DDRA_DQ63 DDRA_DQ45 DDRA_DQ47 DDRA_DQ42 DDRA_DQ48 DDRA_DQ49 DDRA_DQ53 DDRA_DQ36 DDRA_DQ32 DDRA_DQ35 DDRA_DQ34 DDRA_DQ40 SMB_DATA_S3 DDRA_SA1 DDRA_SA0 DDRA_SA2 DDRA_BA0 DDRA_MA15_CAS# DDRA_DQ59 DDRA_DQS#5 DDRA_DQS5 DDRA_EVENT# DDRA_EVENT# DDRA_CLK0 7 DDRA_CLK0# 7 DDRA_CLK1 7 DDRA_CLK1# 7 DDRA_CS0# 7 DDRA_CS1# 7 DDRA_CKE0 7 DDRA_CKE1 7 DDRA_ODT0 7 DDRA_ODT1 7 DDRA_MA0 7 DDRA_MA1 7 DDRA_MA2 7 DDRA_MA3 7 DDRA_MA10_AP 7 DDRA_MA5 7 DDRA_MA4 7 DDRA_MA9 7 DDRA_MA8 7 DDRA_MA6 7 DDRA_MA7 7 DDRA_MA12 7 DDRA_MA11 7 DDRA_MA13 7 DDRA_MA14_WE# 7 DDRA_MA16_RAS# 7 DDRA_MA15_CAS# 7 DDRA_BG0 7 DDRA_BG1 7 DDRA_BA1 7 DDRA_BA0 7 DDRA_PARITY 7 DDRA_ALERT# 7 DDRA_DQS#0 7 DDRA_DQS0 7 DDRA_DQS#2 7 DDRA_DQS2 7 DDRA_DQS#1 7 DDRA_DQS1 7 DDRA_DQS#3 7 DDRA_DQS3 7 DDRA_DQS#5 7 DDRA_DQS5 7 DDRA_DQS#7 7 DDRA_DQS7 7 DDRA_DQS#6 7 DDRA_DQS6 7 DDRA_DQS#4 7 DDRA_DQS4 7 DDRA_DQ4 7 DDRA_DQ0 7 DDRA_DQ7 7 DDRA_DQ3 7 DDRA_DQ13 7 DDRA_DQ12 7 DDRA_DQ15 7 DDRA_DQ14 7 DDRA_DQ21 7 DDRA_DQ20 7 DDRA_DQ22 7 DDRA_DQ18 7 DDRA_DQ29 7 DDRA_DQ28 7 DDRA_DQ27 7 DDRA_DQ30 7 DDRA_DQ33 7 DDRA_DQ37 7 DDRA_DQ38 7 DDRA_DQ39 7 DDRA_DQ44 7 DDRA_DQ41 7 DDRA_DQ43 7 DDRA_DQ46 7 DDRA_DQ50 7 DDRA_DQ52 7 DDRA_DQ54 7 DDRA_DQ51 7 DDRA_DQ57 7 DDRA_DQ61 7 DDRA_DQ62 7 DDRA_DQ58 7 DDRA_DQ1 7 DDRA_DQ5 7 DDRA_DQ6 7 DDRA_DQ2 7 DDRA_DQ9 7 DDRA_DQ8 7 DDRA_DQ10 7 DDRA_DQ11 7 DDRA_DQ16 7 DDRA_DQ17 7 DDRA_DQ19 7 DDRA_DQ23 7 DDRA_DQ24 7 DDRA_DQ36 7 DDRA_DQ32 7 DDRA_DQ35 7 DDRA_DQ34 7 DDRA_DQ40 7 DDRA_DQ45 7 DDRA_DQ47 7 DDRA_DQ42 7 DDRA_DQ48 7 DDRA_DQ49 7 DDRA_DQ53 7 DDRA_DQ55 7 DDRA_DQ56 7 DDRA_DQ60 7 DDRA_DQ59 7 DDRA_DQ63 7 PCH_DRAMRST# 13,16 SMB_DATA_S3 13,16,45,50 SMB_CLK_S3 13,16,45,50 DDRA_ACT# 7 DDRA_DQ25 7 DDRA_DQ26 7 DDRA_DQ31 7 +0.6VS +1.2V +1.2V +VREF_CA_DIMMA_R +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +3VS +2.5V +2.5V +0.6VS +3VS +3VS +3VS +1.2V Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM A C 12 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM A C 12 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM A C 12 75 Friday, November 25, 2016 2015/02/26 2016/02/26 RD26 0_0402_5% @ 1 2 CD8 10U_0603_6.3V6M 1 2 CD16 1U_0402_6.3V6K 1 2 CD15 1U_0402_6.3V6K 1 2 RD1 1K_0402_1% 1 2 CD25 10U_0402_6.3V6M 1 2 CD68 1U_0402_6.3V6K 1 2 CD14 10U_0603_6.3V6M 1 2 CD28 .1U_0402_10V6-K 1 2 CD11 10U_0603_6.3V6M 1 2 CD10 10U_0603_6.3V6M 1 2 CD17 1U_0402_6.3V6K 1 2 CD3 .1U_0402_10V6-K 1 2 CD27 2.2U_0603_6.3V6K 1 2 RD5 240_0402_5% 1 2 CD7 10U_0603_6.3V6M 1 2 CD97 4.7U_0603_6.3V6K EMC_NS@ 1 2 CD18 1U_0402_6.3V6K 1 2 CD2 2.2U_0603_6.3V6K 1 2 RD20 0_0402_5% 1 2 CD81 33P_0402_50V8J RF@ 1 2 RD22 0_0402_5% @ 1 2 CD59 1U_0402_6.3V6K 1 2 CD1 0.022U_0402_16V7-K 1 2 CD82 33P_0402_50V8J RF@ 1 2 CD98 4.7U_0603_6.3V6K EMC_NS@ 1 2 CD96 0.1U_0402_10V7K EMC_NS@ 1 2 RD23 0_0402_5% 1 2 CD9 10U_0603_6.3V6M 1 2 RD3 1K_0402_1% 1 2 CD60 1U_0402_6.3V6K 1 2 CD13 10U_0603_6.3V6M 1 2 CD12 10U_0603_6.3V6M 1 2 CD21 .1U_0402_10V6-K 1 2 RD25 0_0402_5% 1 2 CD65 1U_0402_6.3V6K 1 2 RVS JDDRL1A ARGOS_D4AR0-26001-1P52 ME@ VSS_1 1 DQ5 3 VSS_3 5 DQ1 7 VSS_5 9 DQS0_C 11 DQS0_t 13 VSS_8 15 DQ7 17 VSS_10 19 DQ3 21 VSS_12 23 DQ13 25 VSS_14 27 DQ9 29 VSS_16 31 DM1_n/DBl1_n/NC 33 VSS_17 35 DQ15 37 VSS_19 39 DQ10 41 VSS_21 43 DQ21 45 VSS_23 47 DQ17 49 VSS_25 51 DQS2_c 53 DQS2_t 55 VSS_28 57 DQ23 59 VSS_30 61 DQ19 63 VSS_32 65 DQ29 67 VSS_34 69 DQ25 71 VSS_36 73 DM3_n/DBl3_n/NC 75 VSS_37 77 DQ30 79 VSS_39 81 VSS_2 2 DQ4 4 VSS_4 6 DQ0 8 VSS_6 10 DM0_n/DBI0_n/NC 12 VSS_7 14 DQ6 16 VSS_9 18 DQ2 20 VSS_11 22 DQ12 24 VSS_13 26 DQ8 28 VSS_15 30 DQS1_c 32 DQS1_t 34 VSS_18 36 DQ14 38 VSS_20 40 DQ11 42 VSS_22 44 DQ20 46 VSS_24 48 DQ16 50 VSS_26 52 DM2_n/DBl2_n/NC 54 VSS_27 56 DQ22 58 VSS_29 60 DQ18 62 VSS_31 64 DQ28 66 VSS_33 68 DQ24 70 VSS_35 72 DQS3_c 74 DQS3_t 76 VSS_38 78 DQ31 80 VSS_40 82 DQ26 83 VSS_41 85 CB5/NC 87 VSS_43 89 CB1/NC 91 VSS_45 93 DQS8_c 95 DQS8_t 97 VSS_48 99 CB2/NC 101 VSS_50 103 CB3/NC 105 VSS_52 107 CKE0 109 VDD_1 111 BG1 113 BG0 115 VDD_3 117 A12 119 A9 121 VDD_5 123 A8 125 A6 127 VDD_7 129 DQ27 84 VSS_42 86 CB4/NC 88 VSS_44 90 CB0/NC 92 VSS_46 94 DBI8_n/DBI_n/NC 96 VSS_47 98 CB6/NC 100 VSS_49 102 CB7/NC 104 VSS_51 106 RESET_n 108 CKE1 110 VDD_2 112 ACT_n 114 ALERT_n 116 VDD_4 118 A11 120 A7 122 VDD_6 124 A5 126 A4 128 VDD_8 130 CD57 10U_0402_6.3V6M 1 2 CD95 0.1U_0402_10V7K EMC_NS@ 1 2 RD27 0_0402_5% 1 2 CD66 1U_0402_6.3V6K 1 2 CD58 10U_0402_6.3V6M 1 2 RVS JDDRL1B ARGOS_D4AR0-26001-1P52 ME@ A3 131 A1 133 VDD_9 135 CK0_t 137 CK0_c 139 VDD_11 141 Parity 143 BA1 145 VDD_13 147 CS0_n 149 WE_n/A14 151 VDD_15 153 ODT0 155 CS1_n 157 VDD_17 159 ODT1 161 VDD_19 163 C1/CS3_n/NC 165 VSS_53 167 DQ37 169 VSS_55 171 DQ33 173 VSS_57 175 DQS4_c 177 DQS4_t 179 VSS_60 181 DQ38 183 VSS_62 185 DQ34 187 VSS_64 189 DQ44 191 VSS_66 193 DQ40 195 VSS_68 197 DM5_n/DBl5_n/NC 199 VSS_69 201 DQ46 203 VSS_71 205 DQ42 207 VSS_73 209 DQ52 211 VSS_75 213 DQ49 215 VSS_77 217 DQS6_c 219 DQS6_t 221 VSS_80 223 DQ55 225 VSS_82 227 DQ51 229 VSS_84 231 DQ61 233 VSS_86 235 DQ56 237 VSS_88 239 DM7_n/DBl7_n/NC 241 VSS_89 243 DQ62 245 VSS_91 247 DQ58 249 VSS_93 251 SCL 253 VDDSPD 255 VPP_1 257 VPP_2 259 A2 132 EVENT_n/NF 134 VDD_10 136 CK1_t/NF 138 CK1_c/NF 140 VDD_12 142 A0 144 A10/AP 146 VDD_14 148 BA0 150 RAS_n/A16 152 VDD_16 154 CAS_n/A15 156 A13 158 VDD_18 160 C0/CS2_n/NC 162 VREFCA 164 SA2 166 VSS_54 168 DQ36 170 VSS_56 172 DQ32 174 VSS_58 176 DM4_n/DBl4_n/NC 178 VSS_59 180 DQ39 182 VSS_61 184 DQ35 186 VSS_63 188 DQ45 190 VSS_65 192 DQ41 194 VSS_67 196 DQS5_c 198 DQS5_t 200 DQ47 204 VSS_70 202 DQ43 208 VSS_72 206 VSS_74 210 DQ53 212 VSS_76 214 DQ48 216 VSS_78 218 DQ54 224 VSS_79 222 DQ50 228 VSS_81 226 DQ60 232 VSS_83 230 DQ57 236 DM6_n/DBl6_n/NC 220 VSS_85 234 DQ63 246 VSS_87 238 DQ59 250 VSS_92 248 DQS7_c 240 DQS7_t 242 VSS_90 244 VSS_94 252 SDA 254 SA0 256 SA1 260 Vtt 258 GND_1 261 GND_2 262 RD18 0_0402_5% 1 2 CD23 1U_0402_6.3V6K 1 2 RD24 0_0402_5% @ 1 2 CD24 10U_0402_6.3V6M 1 2 + CD19 220U_B2_6.3VM_R25M @ 1 2 RD2 2_0402_5% 1 2 CD69 0.1U_0402_10V7K @ 1 2 CD67 1U_0402_6.3V6K 1 2 RD4 24.9_0402_1% 1 2 WWW.AliSaler.Com
  • 13. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Layout Note: Place near DIMM Layout Note: Place near DIMM Change RD12 to 0ohm jump For EMC CAD Note: Trace width= 20 mil, Spcing=20 mils DDR4 SO-DIMM B SPD Address = 2H Near JDDRH1 Change JDDRH1 from Foxconn to ARGOSY and RVS to STD HLZ SDV 20160510 MAX 3A MAX 0.5A MAX 0.5A Change CD83 & CD84 from @ to stuff based on RF requirement HLZ SIT 0924 Add CD4 based on RF requirement HLZ SIT 0924 DDRB_CLK0 DDRB_CLK0# DDRB_CS0# DDRB_CS1# DDRB_CKE0 DDRB_CKE1 DDRB_ODT0 DDRB_ODT1 DDRB_MA1 DDRB_MA3 DDRB_BA1 DDRB_MA6 DDRB_MA8 DDRB_MA9 DDRB_MA12 DDRB_BG1 DDRB_BG0 DDRB_MA4 DDRB_MA5 DDRB_MA7 DDRB_MA11 DDRB_ACT# DDRB_MA14_WE# DDRB_PARITY DDRB_ALERT# DDRB_DQS0 DDRB_DQS#0 DDRB_DQS#1 DDRB_DQS1 DDRB_DQS#2 DDRB_DQS2 DDRB_DQS#3 DDRB_DQS3 DDRB_DQS#4 DDRB_DQS4 DDRB_DQS#6 DDRB_DQS6 DDRB_DQ2 DDRB_DQ5 DDRB_DQ4 DDRB_DQ0 DDRB_DQ6 DDRB_DQ3 DDRB_DQ10 DDRB_DQ14 DDRB_DQ12 DDRB_DQ22 DDRB_DQ18 DDRB_DQ20 DDRB_DQ19 DDRB_DQ27 DDRB_DQ31 DDRB_DQ30 DDRB_DQ24 DDRB_DQ1 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ11 DDRB_DQ15 DDRB_DQ17 DDRB_DQ16 DDRB_DQ23 DDRB_DQ21 DDRB_DQ28 DDRB_DQ25 DDRB_DQ26 DDRB_DQ29 DDRB_DQ38 DDRB_DQ35 DDRB_DQ33 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ46 DDRB_DQ52 DDRB_DQ48 DDRB_DQ50 DDRB_DQ51 DDRB_DQ57 DDRB_DQ61 DDRB_DQ56 DDRB_DQ60 DDRB_DQ32 +VREF_CA_DIMMB PCH_DRAMRST# SMB_CLK_S3 DDRB_SA0 DDRB_SA1 DDRB_SA2 DDRB_DQ13 DDRB_VDDSPD DDRB_CLK1 DDRB_CLK1# DDRB_MA13 DDRB_MA15_CAS# DDRB_MA16_RAS# DDRB_MA10_AP DDRB_MA0 DDRB_BA0 DDRB_DQS#5 DDRB_DQS5 DDRB_DQS7 DDRB_DQS#7 DDRB_DQ34 DDRB_DQ55 DDRB_DQ47 DDRB_DQ45 DDRB_DQ44 DDRB_DQ37 DDRB_DQ36 DDRB_DQ39 DDRB_DQ63 DDRB_DQ58 DDRB_DQ62 DDRB_DQ59 DDRB_DQ49 DDRB_DQ53 +VREF_CA_DIMMB SMB_DATA_S3 DDRB_SA2 DDRB_SA1 DDRB_SA0 DDRB_DQ43 DDRB_DQ54 DDRB_MA2 DDRB_EVENT# DDRB_EVENT# DDRB_CLK0 7 DDRB_CLK0# 7 DDRB_CLK1 7 DDRB_CLK1# 7 DDRB_CS0# 7 DDRB_CS1# 7 DDRB_CKE0 7 DDRB_CKE1 7 DDRB_ODT0 7 DDRB_ODT1 7 DDRB_MA2 7 DDRB_MA0 7 DDRB_MA10_AP 7 DDRB_MA16_RAS# 7 DDRB_MA15_CAS# 7 DDRB_MA1 7 DDRB_MA3 7 DDRB_BA1 7 DDRB_BG1 7 DDRB_BG0 7 DDRB_MA12 7 DDRB_MA9 7 DDRB_MA8 7 DDRB_MA6 7 DDRB_MA11 7 DDRB_MA7 7 DDRB_MA5 7 DDRB_MA4 7 DDRB_ACT# 7 DDRB_BA0 7 DDRB_MA14_WE# 7 DDRB_PARITY 7 DDRB_ALERT# 7 DDRB_DQS#0 7 DDRB_DQS0 7 DDRB_DQS#2 7 DDRB_DQS2 7 DDRB_DQS#4 7 DDRB_DQS4 7 DDRB_DQS#6 7 DDRB_DQS6 7 DDRB_DQS#1 7 DDRB_DQS1 7 DDRB_DQS#3 7 DDRB_DQS3 7 DDRB_DQS#5 7 DDRB_DQS5 7 DDRB_DQS#7 7 DDRB_DQS7 7 DDRB_DQ2 7 DDRB_DQ5 7 DDRB_DQ6 7 DDRB_DQ3 7 DDRB_DQ10 7 DDRB_DQ14 7 DDRB_DQ12 7 DDRB_DQ13 7 DDRB_DQ22 7 DDRB_DQ18 7 DDRB_DQ20 7 DDRB_DQ19 7 DDRB_DQ27 7 DDRB_DQ31 7 DDRB_DQ30 7 DDRB_DQ24 7 DDRB_DQ4 7 DDRB_DQ0 7 DDRB_DQ1 7 DDRB_DQ7 7 DDRB_DQ8 7 DDRB_DQ9 7 DDRB_DQ11 7 DDRB_DQ15 7 DDRB_DQ17 7 DDRB_DQ16 7 DDRB_DQ23 7 DDRB_DQ21 7 DDRB_DQ28 7 DDRB_DQ25 7 DDRB_DQ26 7 DDRB_DQ29 7 DDRB_DQ38 7 DDRB_DQ35 7 DDRB_DQ33 7 DDRB_DQ32 7 DDRB_DQ40 7 DDRB_DQ41 7 DDRB_DQ42 7 DDRB_DQ46 7 DDRB_DQ52 7 DDRB_DQ48 7 DDRB_DQ50 7 DDRB_DQ51 7 DDRB_DQ57 7 DDRB_DQ61 7 DDRB_DQ56 7 DDRB_DQ60 7 DDRB_DQ34 7 DDRB_MA13 7 DDRB_DQ39 7 DDRB_DQ36 7 DDRB_DQ37 7 DDRB_DQ44 7 DDRB_DQ45 7 DDRB_DQ47 7 DDRB_DQ43 7 DDRB_DQ54 7 DDRB_DQ55 7 DDRB_DQ53 7 DDRB_DQ49 7 DDRB_DQ59 7 DDRB_DQ62 7 DDRB_DQ63 7 DDRB_DQ58 7 PCH_DRAMRST# 12,16 SMB_DATA_S3 12,16,45,50 SMB_CLK_S3 12,16,45,50 +0.6VS +1.2V +1.2V +VREF_DQ_DIMMB_R +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +2.5V +3VS +2.5V +0.6VS +3VS +3VS +3VS +1.2V Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM B C 13 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM B C 13 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 DDRVI SO-DIMM B C 13 75 Friday, November 25, 2016 2015/02/26 2016/02/26 CD64 10U_0402_6.3V6M 1 2 RD32 0_0402_5% 1 2 CD46 1U_0402_6.3V6K 1 2 RD6 240_0402_5% 1 2 STD JDDRH1B ARGOS_D4AS0-26001-1P52 ME@ A3 131 A1 133 VDD_9 135 CK0_t 137 CK0_c 139 VDD_11 141 Parity 143 BA1 145 VDD_13 147 CS0_n 149 WE_n/A14 151 VDD_15 153 ODT0 155 CS1_n 157 VDD_17 159 ODT1 161 VDD_19 163 C1/CS3_n/NC 165 VSS_53 167 DQ37 169 VSS_55 171 DQ33 173 VSS_57 175 DQS4_c 177 DQS4_t 179 VSS_60 181 DQ38 183 VSS_62 185 DQ34 187 VSS_64 189 DQ44 191 VSS_66 193 DQ40 195 VSS_68 197 DM5_n/DBl5_n 199 VSS_69 201 DQ46 203 VSS_71 205 DQ42 207 VSS_73 209 DQ52 211 VSS_75 213 DQ49 215 VSS_77 217 DQS6_c 219 DQS6_t 221 VSS_80 223 DQ55 225 VSS_82 227 DQ51 229 VSS_84 231 DQ61 233 VSS_86 235 DQ56 237 VSS_88 239 DM7_n/DBl7_n/NC 241 VSS_89 243 DQ62 245 VSS_91 247 DQ58 249 VSS_93 251 SCL 253 VDDSPD 255 VPP_1 257 VPP_2 259 A2 132 EVENT_n/NF 134 VDD_10 136 CK1_t/NF 138 CK1_c/NF 140 VDD_12 142 A0 144 A10/AP 146 VDD_14 148 BA0 150 RAS_n/A16 152 VDD_16 154 CAS_n/A15 156 A13 158 VDD_18 160 C0/CS2_n/NC 162 VREFCA 164 SA2 166 VSS_54 168 DQ36 170 VSS_56 172 DQ32 174 VSS_58 176 DM4_n/DBl4_n/NC 178 VSS_59 180 DQ39 182 VSS_61 184 DQ35 186 VSS_63 188 DQ45 190 VSS_65 192 DQ41 194 VSS_67 196 DQS5_c 198 DQS5_t 200 DQ47 204 VSS_70 202 DQ43 208 VSS_72 206 VSS_74 210 DQ53 212 VSS_76 214 DQ48 216 VSS_78 218 DQ54 224 VSS_79 222 DQ50 228 VSS_81 226 DQ60 232 VSS_83 230 DQ57 236 DM6_n/DBl6_n/NC 220 VSS_85 234 DQ63 246 VSS_87 238 DQ59 250 VSS_92 248 DQS7_c 240 DQS7_t 242 VSS_90 244 VSS_94 252 SDA 254 SA0 256 SA1 260 Vtt 258 GND_1 261 GND_2 262 CD71 1U_0402_6.3V6K 1 2 CD50 10U_0402_6.3V6M 1 2 CD4 33P_0402_50V8J RF@ 1 2 RD29 0_0402_5% 1 2 RD19 0_0402_5% 1 2 CD61 1U_0402_6.3V6K 1 2 CD72 1U_0402_6.3V6K 1 2 CD47 .1U_0402_10V6-K 1 2 RD13 1K_0402_1% 1 2 CD51 10U_0402_6.3V6M 1 2 CD54 .1U_0402_10V6-K 1 2 CD62 1U_0402_6.3V6K 1 2 CD73 1U_0402_6.3V6K 1 2 CD31 .1U_0402_10V6-K 1 2 CD35 10U_0603_6.3V6M 1 2 RD11 1K_0402_1% 1 2 CD36 10U_0603_6.3V6M 1 2 CD30 2.2U_0603_6.3V6K 1 2 CD53 2.2U_0603_6.3V6K 1 2 CD74 1U_0402_6.3V6K 1 2 CD37 10U_0603_6.3V6M 1 2 RD28 0_0402_5% @ 1 2 CD49 1U_0402_6.3V6K 1 2 RD30 0_0402_5% 1 2 STD JDDRH1A ARGOS_D4AS0-26001-1P52 ME@ VSS_1 1 DQ5 3 VSS_3 5 DQ1 7 VSS_5 9 DQS0_C 11 DQS0_t 13 VSS_8 15 DQ7 17 VSS_10 19 DQ3 21 VSS_12 23 DQ13 25 VSS_14 27 DQ9 29 VSS_16 31 DM1_n/DBl1_n/NC 33 VSS_17 35 DQ15 37 VSS_19 39 DQ10 41 VSS_21 43 DQ21 45 VSS_23 47 DQ17 49 VSS_25 51 DQS2_c 53 DQS2_t 55 VSS_28 57 DQ23 59 VSS_30 61 DQ19 63 VSS_32 65 DQ29 67 VSS_34 69 DQ25 71 VSS_36 73 DM3_n/DBl3_n/NC 75 VSS_37 77 DQ30 79 VSS_39 81 VSS_2 2 DQ4 4 VSS_4 6 DQ0 8 VSS_6 10 DM0_n/DBI0_n/NC 12 VSS_7 14 DQ6 16 VSS_9 18 DQ2 20 VSS_11 22 DQ12 24 VSS_13 26 DQ8 28 VSS_15 30 DQS1_c 32 DQS1_t 34 VSS_18 36 DQ14 38 VSS_20 40 DQ11 42 VSS_22 44 DQ20 46 VSS_24 48 DQ16 50 VSS_26 52 DM2_n/DBl2_n/NC 54 VSS_27 56 DQ22 58 VSS_29 60 DQ18 62 VSS_31 64 DQ28 66 VSS_33 68 DQ24 70 VSS_35 72 DQS3_c 74 DQS3_t 76 VSS_38 78 DQ31 80 VSS_40 82 DQ26 83 VSS_41 85 CB5/NC 87 VSS_43 89 CB1/NC 91 VSS_45 93 DQS8_c 95 DQS8_t 97 VSS_48 99 CB2/NC 101 VSS_50 103 CB3/NC 105 VSS_52 107 CKE0 109 VDD_1 111 BG1 113 BG0 115 VDD_3 117 A12 119 A9 121 VDD_5 123 A8 125 A6 127 VDD_7 129 DQ27 84 VSS_42 86 CB4/NC 88 VSS_44 90 CB0/NC 92 VSS_46 94 DBI8_n/DBI_n/NC 96 VSS_47 98 CB6/NC 100 VSS_49 102 CB7/NC 104 VSS_51 106 RESET_n 108 CKE1 110 VDD_2 112 ACT_n 114 ALERT_n 116 VDD_4 118 A11 120 A7 122 VDD_6 124 A5 126 A4 128 VDD_8 130 CD44 1U_0402_6.3V6K 1 2 CD39 10U_0603_6.3V6M 1 2 RD14 24.9_0402_1% 1 2 RD12 2_0402_5% 1 2 CD43 1U_0402_6.3V6K 1 2 CD83 33P_0402_50V8J RF@ 1 2 CD41 10U_0603_6.3V6M 1 2 CD29 0.022U_0402_16V7-K 1 2 CD38 10U_0603_6.3V6M 1 2 CD63 10U_0402_6.3V6M 1 2 CD45 1U_0402_6.3V6K 1 2 RD21 0_0402_5% 1 2 CD70 0.1U_0402_10V7K @ 1 2 RD33 0_0402_5% @ 1 2 RD31 0_0402_5% @ 1 2 CD40 10U_0603_6.3V6M 1 2 CD84 33P_0402_50V8J RF@ 1 2 CD42 10U_0603_6.3V6M 1 2
  • 14. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A NGFF SSD HDD NGFF SSD NGFF SSD NGFF SSD HDD Cable Add Reserved HDD cable HLZ SDV 20160510 Change RH35 from 43 to 12.1 due to follow DG&CRB HLZ SDV 0601 Reserved Cap HLZ SDV 0616 Add RH781_@ for PCH PECI HLZ SIV 0811 Delete HDD Cable SATA signal HLZ SDV 20160510 EC_SCI# SSD_DET# PCIE_SATA_PRX_DTX_N9 PCIE_SATA_PRX_DTX_P9 PCIE_SATA_PTX_DRX_N9 PCIE_SATA_PTX_DRX_P9 PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12 PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12 PCH_THRMTRIP#_R CPU_PLTRST# PCH_PECI H_PM_SYNC_R H_PM_DOWN PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10 SATA_LED# H_PM_DOWN PCH_PECI CPU_PLTRST# EC_SCI# 20,49 SSD_DET# 45 PCIE_SATA_PRX_DTX_N9 45 PCIE_SATA_PRX_DTX_P9 45 PCIE_SATA_PTX_DRX_N9 45 PCIE_SATA_PTX_DRX_P9 45 PCIE_PTX_DRX_P11 45 PCIE_PTX_DRX_N11 45 PCIE_PRX_DTX_P11 45 PCIE_PRX_DTX_N11 45 PCIE_PTX_DRX_P12 45 PCIE_PTX_DRX_N12 45 PCIE_PRX_DTX_P12 45 PCIE_PRX_DTX_N12 45 H_THRMTRIP# 6,24 CPU_PLTRST# 6 H_PM_SYNC 6 H_PM_DOWN 6 EC_PECI 6,49 PCH_EDP_ENVDD 35 PCH_EDP_ENBKL 35 PCH_EDP_PWM 35 PCIE_PRX_DTX_N10 45 PCIE_PRX_DTX_P10 45 PCIE_PTX_DRX_N10 45 PCIE_PTX_DRX_P10 45 SATA_PRX_DTX_P2 46 SATA_PRX_DTX_N2 46 SATA_PTX_DRX_N2 46 SATA_PTX_DRX_P2 46 +3VS +3VS Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (1/9) PCIe/SATA/GPPFG Custom 14 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (1/9) PCIe/SATA/GPPFG Custom 14 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (1/9) PCIe/SATA/GPPFG Custom 14 75 Friday, November 25, 2016 2015/02/26 2016/02/26 RH34 620_0402_5% 1 2 CH7 .1U_0402_10V6-K @ 1 2 CLINK FAN PCIe/SATA HOST SPT-H_PCH 3 OF 12 UH1C SKYLAKE-H-PCH_FCBGA837 @ CL_CLK AV2 CL_DATA AV3 CL_RST# AW2 GPP_G8/FAN_PWM_0 R44 GPP_G9/FAN_PWM_1 R43 GPP_G10/FAN_PWM_2 U39 GPP_G11/FAN_PWM_3 N42 GPP_G0/FAN_TACH_0 U43 GPP_G1/FAN_TACH_1 U42 GPP_G2/FAN_TACH_2 U41 GPP_G3/FAN_TACH_3 M44 GPP_G4/FAN_TACH_4 U36 GPP_G5/FAN_TACH_5 P44 GPP_G6/FAN_TACH_6 T45 GPP_G7/FAN_TACH_7 T44 PCIE11_TXP B33 PCIE11_TXN C33 PCIE11_RXP K31 PCIE11_RXN L31 GPP_F10/SCLOCK AB33 GPP_F11/SLOAD AB35 GPP_F13/SDATAOUT0 AA44 GPP_F12/SDATAOUT1 AA45 PCIE14_TXN/SATA1B_TXN B38 PCIE14_TXP/SATA1B_TXP C38 PCIE14_RXN/SATA1B_RXN D39 PCIE14_RXP/SATA1B_RXP E37 PCIE13_TXN/SATA0B_TXN C36 PCIE13_TXP/SATA0B_TXP B36 PCIE13_RXN/SATA0B_RXN G35 PCIE13_RXP/SATA0B_RXP E35 PCIE12_TXP A35 PCIE12_TXN B35 PCIE12_RXP H33 PCIE12_RXN G33 PCIE20_TXP/SATA7_TXP J45 PCIE20_TXN/SATA7_TXN K44 PCIE20_RXP/SATA7_RXP N38 PCIE20_RXN/SATA7_RXN N39 PCIE19_TXP/SATA6_TXP H44 PCIE19_TXN/SATA6_TXN H43 PCIE19_RXP/SATA6_RXP L39 PCIE19_RXN/SATA6_RXN L37 PCIE9_RXN/SATA0A_RXN G31 PCIE9_RXP/SATA0A_RXP H31 PCIE9_TXN/SATA0A_TXN C31 PCIE9_TXP/SATA0A_TXP B31 PCIE10_RXN/SATA1A_RXN G29 PCIE10_RXP/SATA1A_RXP E29 PCIE10_TXN/SATA1A_TXN C32 PCIE10_TXP/SATA1A_TXP B32 PCIE15_RXN/SATA2_RXN F41 PCIE15_RXP/SATA2_RXP E41 PCIE15_TXN/SATA2_TXN B39 PCIE15_TXP/SATA2_TXP A39 PCIE16_RXN/SATA3_RXN D43 PCIE16_RXP/SATA3_RXP E42 PCIE16_TXN/SATA3_TXN A41 PCIE16_TXP/SATA3_TXP A40 PCIE17_RXN/SATA4_RXN H42 PCIE17_RXP/SATA4_RXP H40 PCIE17_TXN/SATA4_TXN E45 PCIE17_TXP/SATA4_TXP F45 PCIE18_RXN/SATA5_RXN K37 PCIE18_RXP/SATA5_RXP G37 PCIE18_TXN/SATA5_TXN G45 PCIE18_TXP/SATA5_TXP G44 GPP_E8/SATALED# AD44 GPP_E0/SATAXPCIE0/SATAGP0 AG36 GPP_E1/SATAXPCIE1/SATAGP1 AG35 GPP_E2/SATAXPCIE2/SATAGP2 AG39 GPP_F0/SATAXPCIE3/SATAGP3 AD35 GPP_F1/SATAXPCIE4/SATAGP4 AD31 GPP_F2/SATAXPCIE5/SATAGP5 AD38 GPP_F3/SATAXPCIE6/SATAGP6 AC43 GPP_F4/SATAXPCIE7/SATAGP7 AB44 GPP_F21/EDP_BKLTCTL W36 GPP_F20/EDP_BKLTEN W35 GPP_F19/EDP_VDDEN W42 THERMTRIP# AJ3 PECI AL3 PM_SYNC AJ4 PLTRST_PROC# AK2 PM_DOWN AH2 RH35 13_0402_5% 1 2 RH13 30_0402_1% 1 2 RH133 10K_0402_5% 1 2 RH15 10K_0402_5% 1 2 RH781 0_0402_5% @ 1 2 RH95 0_0402_5% 1 2 CH263 0.1U_0402_25V6 EMC_NS@ 1 2 CH6 .1U_0402_10V6-K @ 1 2 WWW.AliSaler.Com
  • 15. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A LEFT USB (3.0) LEFT USB (3.0) DDPB_CTRLDATA The signal has a weak internal pull-down. H Port B is detected. L Port B is not detected. * NGFF SSD HDMI DDPC_CTRLDATA The signal has a weak internal pull-down. H Port C is detected. L Port C is not detected. (Default) DDPD_CTRLDATA The signal has a weak internal pull-down. H Port D is detected. L Port D is not detected. (Default) * * 3D Camera Different to Y710 HLZ SDV 20160510 Add Port C/D strap HLZ SDV 20160510 Delete 3D camera HLZ SDV 20160510 Type C USB3.0 Add TypeC USB3 HLZ SDV 20160510 LPC_AD2 LPC_AD0 LPC_AD3 LPC_AD1 USB30_RX_N1 USB30_TX_N1 USB30_TX_P1 USB30_RX_P1 CLK_PCI_EC_R CLK_PCI_TPM_R CLK_PCI_EC PCH_SMI# KBRST# PCH_SMI# DDPB_CLK DDPB_DATA SERIRQ DEVSLP0_R DDPB_CLK DDPB_DATA PCH_EDP_HPD USB30_RX_N2 USB30_TX_N2 USB30_RX_P2 USB30_TX_P2 KBRST# LPC_FRAME# SERIRQ CLK_PCI_TPM DDPC_DATA DDPD_DATA DDPD_DATA DDPC_DATA TYPE-C_USB3_TX_N3 TYPE-C_USB3_TX_P3 TYPE-C_USB3_RX_N3 TYPE-C_USB3_RX_P3 DDPC_CLK DDPD_CLK LPC_AD3 49,50 LPC_AD2 49,50 LPC_AD1 49,50 LPC_AD0 49,50 USB30_TX_N1 47 USB30_RX_P1 47 USB30_RX_N1 47 USB30_TX_P1 47 CLK_PCI_EC 49 CLK_PCI_TPM 50 HDMI_HPD 36 DEVSLP0_R 45 DDPB_CLK 36 DDPB_DATA 36 PCH_EDP_HPD 35 USB30_RX_N2 47 USB30_RX_P2 47 USB30_TX_N2 47 USB30_TX_P2 47 KBRST# 49 SERIRQ 49,50 LPC_FRAME# 49,50 TYPE-C_DP_HPD 37 TYPE-C_USB3_RX_N3 38 TYPE-C_USB3_RX_P3 38 TYPE-C_USB3_TX_N3 38 TYPE-C_USB3_TX_P3 38 +3VS +3VS +3VS +3VS Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (2/9) USB3/GPPAEFGHI Custom 15 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (2/9) USB3/GPPAEFGHI Custom 15 75 Friday, November 25, 2016 2015/02/26 2016/02/26 Size Document Number Rev Date: Sheet o f Security Classification LC Future Center Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Issued Date Deciphered Date Title DY512 1.0 PCH (2/9) USB3/GPPAEFGHI Custom 15 75 Friday, November 25, 2016 2015/02/26 2016/02/26 USB SATA LPC/eSPI SPT-H_PCH 6 OF 12 UH1F SKYLAKE-H-PCH_FCBGA837 @ USB3_1_TXN C11 USB3_1_TXP B11 USB3_1_RXN B7 USB3_1_RXP A7 USB3_2_TXN/SSIC_1_TXN B12 USB3_2_TXP/SSIC_1_TXP A12 USB3_2_RXN/SSIC_1_RXN C8 USB3_2_RXP/SSIC_1_RXP B8 USB3_6_TXN B15 USB3_6_TXP C15 USB3_6_RXN K15 USB3_6_RXP K13 USB3_5_TXN B14 USB3_5_TXP C14 USB3_5_RXN G13 USB3_5_RXP H13 USB3_3_TXP/SSIC_2_TXP D13 USB3_3_TXN/SSIC_2_TXN C13 USB3_3_RXP/SSIC_2_RXP A9 USB3_3_RXN/SSIC_2_RXN B10 USB3_4_TXP B13 USB3_4_TXN A14 USB3_4_RXP G11 USB3_4_RXN E11 GPP_A1/LAD0/ESPI_IO0 AT22 GPP_A2/LAD1/ESPI_IO1 AV22 GPP_A3/LAD2/ESPI_IO2 AT19 GPP_A4/LAD3/ESPI_IO3 BD16 GPP_A5/LFRAME#/ESPI_CS0# BE16 GPP_A6/SERIRQ/ESPI_CS1# BA17 GPP_A7/PIRQA#/ESPI_ALERT0# AW17 GPP_A0/RCIN#/ESPI_ALERT1# AT17 GPP_A14/SUS_STAT#/ESPI_RESET# BC18 GPP_A9/CLKOUT_LPC0/ESPI_CLK BC17 GPP_A10/CLKOUT_LPC1 AV19 GPP_G19/SMI# M45 GPP_G18/NMI# N43 GPP_E6/DEVSLP2 AE45 GPP_E5/DEVSLP1 AG43 GPP_E4/DEVSLP0 AG42 GPP_F9/DEVSLP7 AB39 GPP_F8/DEVSLP6 AB36 GPP_F7/DEVSLP5 AB43 GPP_F6/DEVSLP4 AB42 GPP_F5/DEVSLP3 AB41 RH8 2.2K_0402_5% 1 2 RH104 10K_0402_5% 1 2 RH10 2.2K_0402_5% @ 1 2 RH84 22_0402_5% 1 2 RH32 2.2K_0402_5% 1 2 RH113 10K_0402_5% 1 2 CH265 10P_0402_50V8J EMC_NS@ 1 2 RH87 22_0402_5% TPM@ 1 2 TC110 PAD @ 1 RH33 2.2K_0402_5% 1 2 RH129 10K_0402_5% @ 1 2 CH266 10P_0402_50V8J EMC_NS@ 1 2 IT28 PAD @ 1 IT36 PAD @ 1 SPT-H_PCH 5 OF 12 UH1E SKYLAKE-H-PCH_FCBGA837 @ GPP_I0/DDPB_HPD0 AW4 GPP_I1/DDPC_HPD1 AY2 GPP_I2/DDPD_HPD2 AV4 GPP_I3/DDPE_HPD3 BA4 GPP_I4/EDP_HPD BD7 GPP_I7/DDPC_CTRLCLK BB3 GPP_I8/DDPC_CTRLDATA BD6 GPP_I5/DDPB_CTRLCLK BA5 GPP_I6/DDPB_CTRLDATA BC4 GPP_I9/DDPD_CTRLCLK BE5 GPP_I10/DDPD_CTRLDATA BE6 GPP_F14 Y44 GPP_F23 V44 GPP_F22 W39 GPP_G23 L43 GPP_G22 L44 GPP_G21 U35 GPP_G20 R35 GPP_H23 BD36