Esquemático para laptop HP.

1. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Compal Confidential
Version T0.1
AMD Richland APU / Bolton FCH M3
Pixar AMD M/B LA-9851P Schematics Document
Date : 2012-11-07
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
1 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
1 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
1 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.

2. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LPC BUS
Compal Confidential
USB20
USB Charger
3.3V 48MHz
HD Audio
FCH
Page 13~17
3.3V 24MHz
Model Name : VPU00 AMD
SATA3.0
page 22
port 0
CMOS
Camera
USB 2.0 Port 10
USB
page 27 page 20
uFCBGA-656
AMD Richland
AMD Richland APU
Trinity FP2
BGA 813- Ball
27mm x 31mm
Page 6~10
Bolton M3
Dual Channel BANK 0, 1, 2, 3
204pin DDRIII-SO-DIMM X2
1.5V DDRIII 1333/1600MHz
Memory BUS(DDR3)
Page 11,12
page 19
DP2
APU HDMI
(UMA / Muxless)
HDMI Conn.
DP0
DP1
UMI
MINI Card 1
(Wireless LAN with BT)
page 23
GPP3
GPP1
SATA HDD
P_GPP x 3
GEN1
Touch Pad Int.KBD
page 32
page 33
page 33
ENE
KBC9012
Port 5
USB 2.0 Port 8
page 28
HDA Codec
IDT 92HD91
page 38
LED
RTC CKT.
page 13
Fan Control
page 34
DC/DC
Interface CKT.
page 37
Power On/Off CKT.
page 34
Power Circuit
page 38~46
Sub board
Power/B
Daughter board
Gen3 6Gb/s
3.3MHz
FAN/LED
page 34
Sub Woofer
Amp
Sub Woofer
SPK
HP Amp
page 29
page 30
page 31
page 31
page 14
SYS BIOS (4M)
BIOS ROM
LVDS Conn.
2 CH
page 20
LVDS
Translator
RTD2136S
page 18
2 CH
USB 3.0 Port 0,1
page 26
USB30
M/B*2
USB 2.0 Port 10,11
Daughter board
HP3DC2
Page 36
Accelerometer
SMBus (FCH)
G-Sensor
X1
SATA repeater
reserve
eDPX2
GPP0
NIC
RTL8151GSH-CG
page 24
Transformer / RJ45
page 24
page 21
Port 6
WWAN
NGFF
page 24
SIM
SPI
page 22
page 31
Combo
jack
page 25
SD/ MMC slot
Card Reader
RTS5239-GR
Sub board
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
2 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
2 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
2 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.

3. WWW.AliSaler.Com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DP0
APU
DP0_TXP/N[0:1]
DP0_AUXP/N
C
ANX3112
LVDS_OUT
DP_IN
APU_TXOUT[0:2]+/-
APU_TXOUT_CLK+/-
APU_TZOUT[0:2]+/-
APU_TZOUT_CLK+/-
APU_LVDS_CLK/DATA
HDMI CONN
PCIE_GFX[0:15]
DP1
DISPLAY OUTPUT
CLOCK DISTRIBUTION
A_SODIMM
APU FP2 SOCKET
FCH
Hudson-M2/M3
Internal CLK GEN
100MHz
APU_DISP_CLKP/N
100MHz
APU_CLKP/N
GbE LAN
25MHz
GPP_CLK
WLAN
Mini PCI Socket
GPP1 GPP0
GPP2
WLAN
OPT PCI Socket
GPP3
USB30 SUS/B
GPP4
USB30 M/B
DP0_AUX
LVDS Transtator
B_SODIMM
1066~1866MHz
MEM_MA_CLK7_P/N
MEM_MB_CLK7_P/N
MEM_MB_CLK1_P/N
MEM_MA_CLK1_P/N
1066~1866MHz
AMD AMD
100MHz
32.768KHz 25MHz
LVDS CONN
DP2
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
3 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
3 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
3 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.

4. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
FCH
SM Bus 1 address
DDR DIMM1 1101 000X b
DDR DIMM2 1101 001X b
FCH
SM Bus 0 address
Device Address Device Address
HEX
90
94
HEX
Device Address HEX
EC SM Bus1 address EC SM Bus2 address
Smart Battery 0001 011X b 16H
Device IDSEL# REQ#/GNT# Interrupts
External PCI Devices
+CPU_CORE_NB ON OFF OFF
Voltage for On-die VGA of APU
+CPU_CORE
Voltage Rails
VIN
B+
S1 S3 S5
ON OFF
N/A N/A N/A
N/A
N/A
N/A
Power Plane Description
OFF
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
+VGA_CORE OFF
OFF
ON
0.95-1.2V switched power rail
+0.75VS ON
ON OFF
0.75V switched power rail for DDR terminator
+1.0VSG ON OFF OFF
1.0V switched power rail for VGA
STATE
LOW
LOW
LOW
SIGNAL
Full ON
S1(Power On Suspend)
LOW
LOW LOW
LOW
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF) LOW
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Vcc 3.3V +/- 5%
100K +/- 5%
Ra/Rc/Re
Board ID Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID V typ
AD_BID VAD_BID max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7 NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID / SKU ID Table for AD channel
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
+RTCVCC
+2.5VS
+5VS
+3VS
+5VALW
+3VALW
+VSB ON ON*
ON
ON
ON
ON
ON ON*
+3V_LAN ON ON ON
ON
OFF
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON*
OFF
ON
RTC power
2.5V for CPU_VDDA
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
3.3V power rail for LAN
+1.8VSG OFF
ON OFF
1.8V switched power rail
+1.5VS
+1.5V ON
OFF
OFF
ON OFF
ON
1.5V switched power rail
1.5V power rail for CPU VDDIO and DDR
+1.1VS
+1.2VS ON OFF OFF
ON OFF OFF
1.1V switched power rail for FCH
1.2V switched power rail for APU
+1.1ALW 1.1V switched power rail for FCH ON ON*
ON
Device Address HEX
ADI ADM1032 (GPU) 1001 101X b 9AH
BOM Option Table
x = 1 is read cmd, x= 0 is writee cmd.
SB-TSI (APU) 1001 100X b 98H
LVDS TR( RTD-2132S) 1010 100X b A8H
BOM
Structure Description
BOM Config
UMA
+VDDCI OFF
0.95-1.2V switched power rail ON OFF
VGA Internal Thermal 1000 001X b 82H
V
Audio Codec SSID
Platform Platform ID
Evora 1.0 UMA 0x18DE
G-Sensor
V
V
V
V
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
FCH
MINI3
V
HP Amp
EC_SMB_CK2
SOURCE
KB932
Charger
BATT
SODIMM
FCH_SCLK0
FCH_SDATA0 FCH
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
KB932
FCH_SCLK1
V
FCH_SDATA1
TP
SMBUS Control Table
USB 2.0 USB 1.1 Port
1 External
USB Port
Camera
USB2.0 (Right side)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
EHCI1
EHCI2
USB Port Table
USB 3.0 Port
1 External
USB Port
1
2
3
0 USB3.0 (Right side)
USB3.0 (Right side)
USB2.0 (Right side)
USB2.0 (left side)
BT
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
4 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
4 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
B
4 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.

5. WWW.AliSaler.Com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EC
ENE KB930
+1.5V
+0.75VS
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
+3.3VS 3mA
+3.3VALW 30mA
SATA
HDD*1
ODD*1
+5V 45mA
+3.3VS 25mA
+3.3VALW 201mA
+5V 3A
+3.3V
BATTERY
12.6V
PU21
CHARGER
BQ24725RGRR
AC ADAPTOR
19V 90W
LAN
BCM57785
RAM DDRIII SODIMMX2
VDD_MEM 4A
Audio Codec
ALC271X
RTC
Bettary
VTT_MEM 0.5A
Mini Card*2
BATT+
VIN
VDD CORE 60A
VDDNB 37A
VDDIO 3.2A
VDDR 8.5A
VDDA 750mA
AMD APU FS1R2
0.7~1.475V
+2.5VS
+1.5V
+1.2VS
FCH AMD Hudson M2/M3
VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA
VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA
VDDIO_33_GBE_S
VDDCR_11_GBE_S
VDDIO_GBE_S
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA
+1.1VALW
+1.1VS
+3VALW
+3VS
GND
VDDBT_RTC_G
RTC BAT
VGA ATI
Whistler/Seymour/Granville
PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
VDDCI 4.6A
DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VDDC 47A
A2VDD: 130 mA
VDDR3: 60 mA
+1.0VSG
+3VSG
0.85~1.1V
+1.5VSG
+1.8VSG
B+
+CPU_CORE
+CPU_CORE_NB
+5VALW
+3VALW
+USB_VCCA
U54
TPA2301DRG4
+CPU_CORE
+CPU_CORE_NB
0.9~1.0V
VDDR1: 3400 mA
VRAM 512/1GB/2GB
64M / 128Mx16 * 4 / 8
+1.5VSG 2.4 A
0.7~1.475V
+1.8VSG
+1.0VSG
PU27
ISL6277HRTZ-T
+1.5V
PU26
RT8207MZQW
PU17
RT8209MGQW
+1.2VS
+1.2VS
+1.5V
PU10
TPS51218DSCR
+VGA_CORE
+VGA_CORE
+VDDCI
+VDDCI
PU14
G9731G11U
PU7
SY8033BDBC +1.8VSG
PU15
APL5508
+2.5VS
+2.5VS
PU2
RT8205EGQW
+1.1VALW
PU5
RT8209MGQW
U41
AO4430L
+1.5VSG
+0.75VS
+0.75VS
U39
AO4430L +1.1VS
+1.1VS
+1.1VALW
U40
SI4800
+3VALW
+3VS
JUMP
+3VSG
+3VSG
+3.3 350mA
B+ 300mA
LCD panel
15.6"
+INVPWR_B+
+5V
Dual+1
2.5A
USB X3
Q63
SI2301
+1.5VS
+3VALW
+3VS
+5VS
+5VALW
+3VS
+5VS
U38
SI4800
FAN Control
APL5607
+5VS 500mA
+3VS
+0.75VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
5 47
Monday, October 21, 2013
2012/11/07 2012/11/07 Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
5 47
Monday, October 21, 2013
2012/11/07 2012/11/07 Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
5 47
Monday, October 21, 2013
2012/11/07 2012/11/07

6. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Card reader
WLAN
GPU
UMI
GPU
Card reader
WLAN
UMI
P_ZVSS W/S=8/12 mil, <3000mil
L
P_ZVDDP W/S=8/12 mil, <3000mil
L
Delete GPU
1202 Calvin
Delete GPU
1202 Calvin
GLAN GLAN
10/4 Eric chagne back on RC1 & RC2.
CPU THERMAL SENSOR
Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2
PCIE_FTX_DRX_P0
PCIE_FTX_DRX_N0
PCIE_FTX_DRX_P1
PCIE_FTX_DRX_N1
UMI_FTX_MRX_P0
UMI_FTX_MRX_N0
UMI_FTX_MRX_P1
UMI_FTX_MRX_N1
UMI_FTX_MRX_P2
UMI_FTX_MRX_N2
UMI_FTX_MRX_P3
UMI_FTX_MRX_N3
P_ZVDDP P_ZVSS
CPU_THERM#
EC_SMB_CK2
H_THERMDC
H_THERMDA EC_SMB_DA2
THERMAL_ALERT#
PCIE_FTX_DRX_P3
PCIE_FTX_DRX_N3
PCIE_DTX_C_FRX_P0
24
PCIE_DTX_C_FRX_N0
24
PCIE_DTX_C_FRX_P1
23
PCIE_DTX_C_FRX_N1
23
UMI_MTX_C_FRX_P0
13
UMI_MTX_C_FRX_N0
13
UMI_MTX_C_FRX_P1
13
UMI_MTX_C_FRX_N1
13
UMI_MTX_C_FRX_P2
13
UMI_MTX_C_FRX_N2
13
UMI_MTX_C_FRX_P3
13
UMI_MTX_C_FRX_N3
13
PCIE_FTX_C_DRX_P0 24
PCIE_FTX_C_DRX_N0 24
PCIE_FTX_C_DRX_P1 23
PCIE_FTX_C_DRX_N1 23
UMI_FTX_C_MRX_P0 13
UMI_FTX_C_MRX_N0 13
UMI_FTX_C_MRX_P1 13
UMI_FTX_C_MRX_N1 13
UMI_FTX_C_MRX_P2 13
UMI_FTX_C_MRX_N2 13
UMI_FTX_C_MRX_P3 13
UMI_FTX_C_MRX_N3 13
EC_SMB_DA2 18,30,32,8
EC_SMB_CK2 18,30,32,8
THERMAL_ALERT# 32
PCIE_DTX_C_FRX_P3
25
PCIE_DTX_C_FRX_N3
25
PCIE_FTX_C_DRX_P3 25
PCIE_FTX_C_DRX_N3 25
+1.2VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
6 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
6 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
6 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
CC2 .1U_0402_16V7K
1 2
CC7 .1U_0402_16V7K
1 2
CC12 .1U_0402_16V7K
1 2
CC14 .1U_0402_16V7K
1 2
GRAPHICS
GPP
UMI
UCPU1A
RICHLAND-A8-SERIES_BGA813
P_GFX_RXP[0]
AP1
P_GFX_RXN[0]
AP2
P_GFX_RXP[1]
AM1
P_GFX_RXN[1]
AM2
P_GFX_RXP[2]
AK3
P_GFX_RXN[2]
AK4
P_GFX_RXP[3]
AJ1
P_GFX_RXN[3]
AJ2
P_GFX_RXP[4]
AH4
P_GFX_RXN[4]
AH3
P_GFX_RXP[5]
AF2
P_GFX_RXN[5]
AF1
P_GFX_RXP[6]
AD1
P_GFX_RXN[6]
AD2
P_GFX_RXP[7]
AB3
P_GFX_RXN[7]
AB4
P_GFX_RXP[8]
AA1
P_GFX_RXN[8]
AA2
P_GFX_RXP[9]
Y4
P_GFX_RXN[9]
Y3
P_GFX_RXP[10]
V2
P_GFX_RXN[10]
V1
P_GFX_RXP[11]
T1
P_GFX_RXN[11]
T2
P_GFX_RXP[12]
P3
P_GFX_RXN[12]
P4
P_GFX_RXP[13]
N1
P_GFX_RXN[13]
N2
P_GFX_RXP[14]
M4
P_GFX_RXN[14]
M3
P_GFX_RXP[15]
K2
P_GFX_RXN[15]
K1
P_GFX_TXP[0]
AN1
P_GFX_TXN[0]
AN2
P_GFX_TXP[1]
AM4
P_GFX_TXN[1]
AM3
P_GFX_TXP[2]
AK2
P_GFX_TXN[2]
AK1
P_GFX_TXP[3]
AH1
P_GFX_TXN[3]
AH2
P_GFX_TXP[4]
AF3
P_GFX_TXN[4]
AF4
P_GFX_TXP[5]
AE1
P_GFX_TXN[5]
AE2
P_GFX_TXP[6]
AD4
P_GFX_TXN[6]
AD3
P_GFX_TXP[7]
AB2
P_GFX_TXN[7]
AB1
P_GFX_TXP[8]
Y1
P_GFX_TXN[8]
Y2
P_GFX_TXP[9]
V3
P_GFX_TXN[9]
V4
P_GFX_TXP[10]
U1
P_GFX_TXN[10]
U2
P_GFX_TXP[11]
T4
P_GFX_TXN[11]
T3
P_GFX_TXP[12]
P2
P_GFX_TXN[12]
P1
P_GFX_TXP[13]
M1
P_GFX_TXN[13]
M2
P_GFX_TXP[14]
K3
P_GFX_TXN[14]
K4
P_GFX_TXP[15]
J1
P_GFX_TXN[15]
J2
P_GPP_RXP[0]
AH5
P_GPP_RXN[0]
AH6
P_GPP_RXP[1]
AG5
P_GPP_RXN[1]
AG6
P_GPP_RXP[2]
AE6
P_GPP_RXN[2]
AE5
P_GPP_RXP[3]
AD6
P_GPP_RXN[3]
AD5
P_GPP_TXP[0]
AG7
P_GPP_TXN[0]
AG8
P_GPP_TXP[1]
AE7
P_GPP_TXN[1]
AE8
P_GPP_TXP[2]
AD7
P_GPP_TXN[2]
AD8
P_GPP_TXP[3]
AB6
P_GPP_TXN[3]
AB5
P_UMI_RXP[0]
AM10
P_UMI_RXN[0]
AN10
P_UMI_RXP[1]
AN8
P_UMI_RXN[1]
AM8
P_UMI_RXP[2]
AP8
P_UMI_RXN[2]
AR8
P_UMI_RXP[3]
AR7
P_UMI_RXN[3]
AP7
P_UMI_TXP[0]
AN6
P_UMI_TXN[0]
AM6
P_UMI_TXP[1]
AP6
P_UMI_TXN[1]
AR6
P_UMI_TXP[2]
AP4
P_UMI_TXN[2]
AR4
P_UMI_TXP[3]
AP3
P_UMI_TXN[3]
AR3
P_ZVDDP
AR11
P_ZVSS
AP11
CC9 .1U_0402_16V7K
1 2
RC2 196_0402_1%
1 2
CC8 .1U_0402_16V7K
1 2
CC4 .1U_0402_16V7K
1 2
RC1 196_0402_1%
1 2
CC13 .1U_0402_16V7K
1 2
CC174
2200P_0402_50V7K
1 2
CC6 .1U_0402_16V7K
1 2
CC11 .1U_0402_16V7K
1 2
CC173
0.1U_0402_16V4Z
1
2
RC106 33K_0402_5%
1 2
CC5 .1U_0402_16V7K
1 2
CC10 .1U_0402_16V7K
1 2
UC1
ADM1032ARMZ-2REEL_MSOP8
SA00003PU00
VDD
1
ALERT#
6
THERM#
4
GND
5
D+
2
D-
3
SCLK
8
SDATA
7
CC1 .1U_0402_16V7K
1 2
RC105 10K_0402_5%
1
2
CC3 .1U_0402_16V7K
1 2

7. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
0.75V reference voltage
+MEM_VREF 15mil
Close to JCPU1
L
M_ZVDDIO W/S=8/12 mil, <1000mil
L
10/4 Eric Del CC45.
EVENT# pull high
11/19 Eric change 4P2R to 8P4R.
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ3
DDRA_SDQ13
DDRA_SDQ40
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ61
DDRA_SDQ15
DDRA_SDQ34
DDRA_SDQ36
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ53
DDRA_SDQ47
DDRA_SDQ43
DDRA_SDQ39
DDRA_SDQ46
DDRA_SDQ33
DDRA_SDQ24
DDRA_SDQ54
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ8
DDRA_SDQ51
DDRA_SDQ9
DDRA_SDQ50
DDRA_SDQ12
DDRA_SDQ31
DDRA_SDQ7
DDRA_SDQ63
DDRA_SDQ62
DDRA_SDQ42
DDRA_SDQ26
DDRA_SDQ58
DDRA_SDQ25
DDRA_SDQ32
DDRA_SDQ1
DDRA_SDQ44
DDRA_SDQ48
DDRA_SDQ11
DDRA_SDQ55
DDRA_SDQ2
DDRA_SDQ38
DDRA_SDQ27
DDRA_SDQ41
DDRA_SDQ10
DDRA_SDQ14
DDRA_SDQ49
DDRA_SDQ30
DDRA_SDQ35
DDRA_SDQ37
DDRA_SDQ52
DDRA_SDQ45
DDRA_SDQ57
DDRA_SDQ56
DDRB_SDQ48
DDRB_SDQ39
DDRB_SDQ1
DDRB_SDQ42
DDRB_SDQ36
DDRB_SDQ2
DDRB_SDQ58
DDRB_SDQ33
DDRB_SDQ31
DDRB_SDQ21
DDRB_SDQ54
DDRB_SDQ62
DDRB_SDQ24
DDRB_SDQ15
DDRB_SDQ12
DDRB_SDQ49
DDRB_SDQ60
DDRB_SDQ43
DDRB_SDQ18
DDRB_SDQ34
DDRB_SDQ4
DDRB_SDQ61
DDRB_SDQ6
DDRB_SDQ25
DDRB_SDQ23
DDRB_SDQ57
DDRB_SDQ13
DDRB_SDQ0
DDRB_SDQ28
DDRB_SDQ16
DDRB_SDQ22
DDRB_SDQ19
DDRB_SDQ9
DDRB_SDQ50
DDRB_SDQ35
DDRB_SDQ46
DDRB_SDQ5
DDRB_SDQ37
DDRB_SDQ26
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ29
DDRB_SDQ14
DDRB_SDQ7
DDRB_SDQ51
DDRB_SDQ10
DDRB_SDQ59
DDRB_SDQ17
DDRB_SDQ44
DDRB_SDQ41
DDRB_SDQ38
DDRB_SDQ47
DDRB_SDQ32
DDRB_SDQ20
DDRB_SDQ52
DDRB_SDQ30
DDRB_SDQ63
DDRB_SDQ53
DDRB_SDQ40
DDRB_SDQ27
DDRB_SDQ45
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ11
DDRA_SDQ20
DDRA_SDQ22
DDRA_SDQ21
DDRA_SDQ23
DDRA_SDQ17
DDRA_SDQ16
DDRA_SDQ18
DDRB_SMA14
DDRB_SMA10
DDRB_SMA7
DDRB_SMA1
DDRB_SMA12
DDRB_SMA6
DDRB_SMA11
DDRB_SMA0
DDRB_SMA9
DDRB_SMA15
DDRB_SMA3
DDRB_SMA5
DDRB_SMA8
DDRB_SMA13
DDRB_SMA2
DDRB_SMA4
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDM6
DDRB_SDM4
DDRB_SDM2
DDRB_SDM0
DDRB_SDM5
DDRB_SDM3
DDRB_SDM1
DDRB_SDM7
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRA_SDQ19
DDRA_SDQS7#
DDRA_SDQS0
DDRA_SMA11
DDRA_SDQS3
DDRA_SDM7
DDRA_SBS1#
DDRA_SDQS6
DDRA_SDM2
DDRA_SMA0
DDRA_CLK1
DDRA_SMA6
DDRA_SDQS4#
DDRA_SMA10
DDRA_CLK0
DDRA_SDQS0#
DDRA_SBS0#
DDRA_SDQS3#
DDRA_SDM1
DDRA_SDQS6#
DDRA_SMA5
DDRA_SMA3
DDRA_CLK1#
DDRA_SDQS2
DDRA_SMA9
DDRA_SDQS5
DDRA_SMA15
DDRA_SMA13
DDRA_CLK0#
DDRA_SDQS1
DDRA_SDM0
DDRA_SDQS4
DDRA_SDM6
DDRA_SDM4
DDRA_SMA4
DDRA_SMA2
DDRA_SDQS7
DDRA_SMA8
DDRA_SDQS2#
DDRA_SMA14
DDRA_SMA12
DDRA_SDQS5#
DDRA_SBS2#
DDRA_SDQS1#
DDRA_SDM5
DDRA_SDM3
DDRA_SMA1
DDRA_SMA7
M_ZVDDIO
DDRA_CKE0
DDRA_ODT1
DDRA_CKE1
DDRA_ODT0
MEM_MA_RST#
MEM_MA_EVENT#
DDRA_SCAS#
DDRA_SRAS#
DDRA_SWE#
DDRA_SCS1#
DDRA_SCS0#
DDRB_CLK0#
DDRB_CLK0
DDRB_CLK1#
DDRB_CLK1
DDRB_ODT0
DDRB_ODT1
DDRB_CKE1
DDRB_CKE0
DDRB_SCS1#
DDRB_SCS0#
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
MEM_MB_RST#
MEM_MB_EVENT#
+MEM_VREF
MEM_MB_EVENT#
MEM_MA_EVENT#
DDRB_SDQ[63..0] 12
DDRA_SBS0#
11
DDRA_SBS1#
11
DDRA_SBS2#
11
DDRA_SDQS0
11
DDRA_SDQS0#
11
DDRA_SDQS1
11
DDRA_SDQS1#
11
DDRA_SDQS2
11
DDRA_SDQS2#
11
DDRA_SDQS3
11
DDRA_SDQS3#
11
DDRA_SDQS4
11
DDRA_SDQS4#
11
DDRA_SDQS5
11
DDRA_SDQS5#
11
DDRA_SDQS6
11
DDRA_SDQS6#
11
DDRA_SDQS7
11
DDRA_SDQS7#
11
DDRA_CLK0
11
DDRA_CLK0#
11
DDRA_CLK1
11
DDRA_CLK1#
11
DDRA_SMA[15..0]
11
DDRA_SDM[7..0]
11
DDRA_SDQ[63..0] 11
DDRB_SBS0#
12
DDRB_SBS1#
12
DDRB_SBS2#
12
DDRB_SMA[15..0]
12
DDRB_SDQS7
12
DDRB_SDQS7#
12
DDRB_SDQS6
12
DDRB_SDQS5
12
DDRB_SDQS4
12
DDRB_SDQS3
12
DDRB_SDQS2
12
DDRB_SDQS1
12
DDRB_SDQS0
12
DDRB_SDQS6#
12
DDRB_SDQS5#
12
DDRB_SDQS4#
12
DDRB_SDQS3#
12
DDRB_SDQS2#
12
DDRB_SDQS1#
12
DDRB_SDQS0#
12
DDRB_SDM[7..0]
12
DDRA_CKE0
11
DDRA_CKE1
11
DDRA_ODT0
11
DDRA_ODT1
11
MEM_MA_RST#
11
MEM_MA_EVENT#
11
DDRA_SRAS#
11
DDRA_SCAS#
11
DDRA_SWE#
11
DDRA_SCS1#
11
DDRA_SCS0#
11
DDRB_CLK0
12
DDRB_CLK0#
12
DDRB_CLK1
12
DDRB_CLK1#
12
DDRB_CKE0
12
DDRB_CKE1
12
DDRB_ODT0
12
DDRB_ODT1
12
DDRB_SCS0#
12
DDRB_SCS1#
12
DDRB_SRAS#
12
DDRB_SCAS#
12
DDRB_SWE#
12
MEM_MB_RST#
12
MEM_MB_EVENT#
12
+1.35V_VDDQ
+MEM_VREF
+1.35V_VDDQ
+1.35V_VDDQ
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
7 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
7 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
7 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
RC109 1K_0402_5%
1 2 CC15
.1U_0402_16V7K
1
2
UCPU1B
RICHLAND-A8-SERIES_BGA813
MA_ADD[0]
AA28
MA_ADD[1]
R29
MA_ADD[2]
T30
MA_ADD[3]
R28
MA_ADD[4]
R26
MA_ADD[5]
P26
MA_ADD[6]
P27
MA_ADD[7]
P30
MA_ADD[8]
P29
MA_ADD[9]
M28
MA_ADD[10]
AB26
MA_ADD[11]
M26
MA_ADD[12]
M29
MA_ADD[13]
AE27
MA_ADD[14]
L26
MA_ADD[15]
L27
MA_BANK[0]
AB27
MA_BANK[1]
AA29
MA_BANK[2]
M30
MA_DM[0]
D16
MA_DM[1]
D20
MA_DM[2]
E25
MA_DM[3]
F30
MA_DM[4]
AK29
MA_DM[5]
AL25
MA_DM[6]
AM20
MA_DM[7]
AM16
MA_DQS_H[0]
G17
MA_DQS_L[0]
H17
MA_DQS_H[1]
F22
MA_DQS_L[1]
G22
MA_DQS_H[2]
E26
MA_DQS_L[2]
F26
MA_DQS_H[3]
H30
MA_DQS_L[3]
G30
MA_DQS_H[4]
AL29
MA_DQS_L[4]
AL30
MA_DQS_H[5]
AH25
MA_DQS_L[5]
AJ25
MA_DQS_H[6]
AK20
MA_DQS_L[6]
AL20
MA_DQS_H[7]
AK15
MA_DQS_L[7]
AL15
MA_CLK_H[0]
W29
MA_CLK_L[0]
Y30
MA_CLK_H[1]
W26
MA_CLK_L[1]
W27
MA_CLK_H[2]
U29
MA_CLK_L[2]
V30
MA_CLK_H[3]
U26
MA_CLK_L[3]
U27
MA_CKE[0]
L29
MA_CKE[1]
K30
MA0_ODT[0]
AD30
MA0_ODT[1]
AG28
MA1_ODT[0]
AE26
MA1_ODT[1]
AG29
MA0_CS_L[0]
AD26
MA0_CS_L[1]
AE29
MA1_CS_L[0]
AB30
MA1_CS_L[1]
AF30
MA_RAS_L
AB29
MA_CAS_L
AD29
MA_WE_L
AD28
MA_RESET_L
J28
MA_EVENT_L
AA26
M_VREF
G32
M_ZVDDIO
AJ32
MA_DATA[0]
F15
MA_DATA[1]
E15
MA_DATA[2]
H19
MA_DATA[3]
F19
MA_DATA[4]
E14
MA_DATA[5]
H15
MA_DATA[6]
E17
MA_DATA[7]
D18
MA_DATA[8]
G20
MA_DATA[9]
E20
MA_DATA[10]
H23
MA_DATA[11]
G23
MA_DATA[12]
E19
MA_DATA[13]
H20
MA_DATA[14]
E22
MA_DATA[15]
D22
MA_DATA[16]
H25
MA_DATA[17]
F25
MA_DATA[18]
D28
MA_DATA[19]
D29
MA_DATA[20]
E23
MA_DATA[21]
D24
MA_DATA[22]
D26
MA_DATA[23]
D27
MA_DATA[24]
G28
MA_DATA[25]
G29
MA_DATA[26]
H27
MA_DATA[27]
J29
MA_DATA[28]
E28
MA_DATA[29]
F27
MA_DATA[30]
H29
MA_DATA[31]
H28
MA_DATA[32]
AH29
MA_DATA[33]
AJ30
MA_DATA[34]
AM28
MA_DATA[35]
AM27
MA_DATA[36]
AH27
MA_DATA[37]
AH28
MA_DATA[38]
AJ29
MA_DATA[39]
AK27
MA_DATA[40]
AK26
MA_DATA[41]
AJ26
MA_DATA[42]
AK23
MA_DATA[43]
AJ23
MA_DATA[44]
AM26
MA_DATA[45]
AL26
MA_DATA[46]
AM24
MA_DATA[47]
AL23
MA_DATA[48]
AK22
MA_DATA[49]
AH22
MA_DATA[50]
AK19
MA_DATA[51]
AH19
MA_DATA[52]
AM22
MA_DATA[53]
AL22
MA_DATA[54]
AJ20
MA_DATA[55]
AL19
MA_DATA[56]
AK17
MA_DATA[57]
AJ17
MA_DATA[58]
AK14
MA_DATA[59]
AH14
MA_DATA[60]
AM18
MA_DATA[61]
AL17
MA_DATA[62]
AH15
MA_DATA[63]
AL14
RC110 1K_0402_5%
1 2
RC113
1K_0402_1%
1
2
UCPU1C
RICHLAND-A8-SERIES_BGA813
MB_ADD[0]
Y33
MB_ADD[1]
R32
MB_ADD[2]
T31
MB_ADD[3]
P33
MB_ADD[4]
P32
MB_ADD[5]
P31
MB_ADD[6]
N32
MB_ADD[7]
M33
MB_ADD[8]
M32
MB_ADD[9]
L32
MB_ADD[10]
AB31
MB_ADD[11]
M31
MB_ADD[12]
K32
MB_ADD[13]
AF33
MB_ADD[14]
K33
MB_ADD[15]
J32
MB_BANK[0]
AB33
MB_BANK[1]
AA32
MB_BANK[2]
K31
MB_DM[0]
C18
MB_DM[1]
B23
MB_DM[2]
C28
MB_DM[3]
D31
MB_DM[4]
AM31
MB_DM[5]
AN30
MB_DM[6]
AR24
MB_DM[7]
AN18
MB_DQS_H[0]
B18
MB_DQS_L[0]
A18
MB_DQS_H[1]
B24
MB_DQS_L[1]
A24
MB_DQS_H[2]
B30
MB_DQS_L[2]
B29
MB_DQS_H[3]
D32
MB_DQS_L[3]
D33
MB_DQS_H[4]
AM32
MB_DQS_L[4]
AM33
MB_DQS_H[5]
AN28
MB_DQS_L[5]
AP29
MB_DQS_H[6]
AP23
MB_DQS_L[6]
AP24
MB_DQS_H[7]
AR18
MB_DQS_L[7]
AP18
MB_CLK_H[0]
W32
MB_CLK_L[0]
Y32
MB_CLK_H[1]
V33
MB_CLK_L[1]
V32
MB_CLK_H[2]
U32
MB_CLK_L[2]
V31
MB_CLK_H[3]
T33
MB_CLK_L[3]
T32
MB_CKE[0]
H32
MB_CKE[1]
H33
MB0_ODT[0]
AF31
MB0_ODT[1]
AH31
MB1_ODT[0]
AE32
MB1_ODT[1]
AH33
MB0_CS_L[0]
AD31
MB0_CS_L[1]
AF32
MB1_CS_L[0]
AC32
MB1_CS_L[1]
AG32
MB_RAS_L
AB32
MB_CAS_L
AD32
MB_WE_L
AD33
MB_RESET_L
H31
MB_EVENT_L
Y31
MB_DATA[0]
C16
MB_DATA[1]
B17
MB_DATA[2]
B20
MB_DATA[3]
C20
MB_DATA[4]
A16
MB_DATA[5]
B16
MB_DATA[6]
B19
MB_DATA[7]
A20
MB_DATA[8]
B22
MB_DATA[9]
C22
MB_DATA[10]
A26
MB_DATA[11]
B26
MB_DATA[12]
B21
MB_DATA[13]
A22
MB_DATA[14]
C24
MB_DATA[15]
B25
MB_DATA[16]
A28
MB_DATA[17]
B28
MB_DATA[18]
B31
MB_DATA[19]
A32
MB_DATA[20]
C26
MB_DATA[21]
B27
MB_DATA[22]
A30
MB_DATA[23]
C30
MB_DATA[24]
B33
MB_DATA[25]
C32
MB_DATA[26]
F33
MB_DATA[27]
F32
MB_DATA[28]
B32
MB_DATA[29]
C31
MB_DATA[30]
E32
MB_DATA[31]
F31
MB_DATA[32]
AK32
MB_DATA[33]
AL32
MB_DATA[34]
AP32
MB_DATA[35]
AN31
MB_DATA[36]
AK31
MB_DATA[37]
AK33
MB_DATA[38]
AN32
MB_DATA[39]
AP33
MB_DATA[40]
AP30
MB_DATA[41]
AR30
MB_DATA[42]
AP27
MB_DATA[43]
AN26
MB_DATA[44]
AR32
MB_DATA[45]
AP31
MB_DATA[46]
AR28
MB_DATA[47]
AP28
MB_DATA[48]
AP25
MB_DATA[49]
AN24
MB_DATA[50]
AR22
MB_DATA[51]
AP21
MB_DATA[52]
AP26
MB_DATA[53]
AR26
MB_DATA[54]
AN22
MB_DATA[55]
AP22
MB_DATA[56]
AR20
MB_DATA[57]
AP19
MB_DATA[58]
AP16
MB_DATA[59]
AR16
MB_DATA[60]
AN20
MB_DATA[61]
AP20
MB_DATA[62]
AP17
MB_DATA[63]
AN16
RC3 39.2_0402_1%
1 2
RC112
1K_0402_1%
1
2

8. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
100MHz
100MHz
NSS
To LVDS
Translator
THERMTRIP shutdown
temperature: 115 degree
Asserted as an input to
force processor into
HTC-active state
Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the FCH
to transition the system to S5 immediately
Allow_STOP leakage issue
Route as differential with APU_VDD_RUN_FB_L
CPU TSI interface level shift
BSH111, the Vgs is:
min = 0.4V
Max = 1.3V
HDT Debug conn
Close to Header
For ESD request close APU side
To HDMI
Internal PU when no use HDT
Vg = 1.607 V
When APU High -> MOS OFF (Vgs < 0.4V )
APU Low -> MOS ON (Vgs > 1.3V)
10/27 300 ohm??
Close to APU (JCPU1)
L
SB-TSI (S5 Domain)
SVI 2.0
(0 ohm
at Power Side)
To LVDS Translator
To HDMI
Place near APU
HDMI
LVDS/eDP
DP_AUX_ZVSS W/S=8/12 mil, <3000mil
L
10/27 add TP.
TEST35 change to PU for
HDMI can not output
20110126
Check
12/19 del CC141/CC142, RC10, RC11
TEST35 change to PU for
HDMI can not output
20110126
12/15 change to +1.5V
12/15 change to +1.5V
12/19 remove damping 0ohm.
12/19 RF request
2/29 remove RC42, add EC_THERM for power leakage issue
3/9 add QC5 for +5VS power leakage issue
4/17 change to 0ohm new symbol
4/17 change to 0ohm new symbol
10/18 Eric change Level shift solution with Pagani AMD.
10/3 Eric Add DP_ENVDD control pin.
10/4 Eric Del.
10/4 Eric Del.
12/27 Eric Del.
FHD eDP
TC13 near APU.
10/25 Eric aremovek H_PROCHOT# .
1/11 Eric mount RC25 for open drain needed.
APU_DISP_CLKP
APU_DISP_CLKN
APU_THERMTRIP#
APU_CLKP
APU_CLKN
DP0_TXN0
APU_SID
APU_SIC
ALERT_L
APU_PROCHOT#
APU_THERMTRIP#
APU_DBRDY
APU_DBREQ#
DP0_TXP0
APU_RST#
APU_PWRGD APU_PWRGD_APU
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_VDDNB_SEN
APU_SIC
APU_SID
APU_TCK
APU_TMS
APU_DBREQ#
APU_TRST#
EC_SMB_CK2
APU_SVT
APU_SVT
APU_SVC
APU_SVD
APU_SVC
APU_SVD
DP0_AUXN
DP0_AUXP
APU_HDMI_CLK
APU_HDMI_DATA
DP2_HPD
DP0_HPD
DP_INT_PWM
DP_AUX_ZVSS
APU_TEST24
APU_TEST20
APU_TEST19
APU_TEST18
M_TEST
TEST35
ALLOW_STOP
APU_PROCHOT#
APU_PWRGD
APU_DBRDY
APU_TEST18
APU_RST#
APU_DBREQ#
APU_TDO
APU_TCK
APU_TMS
APU_TDI
APU_TEST19
APU_SID
APU_RST#_APU
DP0_TXN1
DP0_TXP1
APU_RST#
APU_PWRGD
DP0_AUXN
DP0_AUXP
TEST25_L
TEST25_H
EC_SMB_DA2
DP_ENVDD
DP_ENBKL
DP0_TXN2
DP0_TXP2
DP0_TXN3
DP0_TXP3
APU_VDD_SEN
ALERT_L
ALLOW_STOP
ALLOW_STOP
APU_TEST20
APU_TEST19
APU_TEST18
APU_TEST24
APU_TRST#
APU_TDI
APU_SIC
APU_CLKP
13
APU_CLKN
13
APU_DISP_CLKP
13
APU_DISP_CLKN
13
DP0_TXN0_C
18
APU_VDD_RUN_FB_L
46
H_THERMTRIP# 15
MAINPWON 32,41
DP0_TXP0_C
18
APU_RST#
13
APU_PWRGD
13,46
APU_VDDNB_SEN
46
APU_VDD_SEN
46
EC_SMB_DA2 18,30,32,6
EC_SMB_CK2 18,30,32,6
APU_SVT
46
APU_HDMI_TXD2+
19
APU_HDMI_TXD2-
19
APU_HDMI_TXD1-
19
APU_HDMI_TXD1+
19
APU_HDMI_TXD0-
19
APU_HDMI_TXD0+
19
APU_HDMI_TXC-
19
APU_HDMI_TXC+
19
APU_SVC
46
APU_SVD
46
DP0_AUXP_C 18
DP0_AUXN_C 18
APU_HDMI_CLK 19
APU_HDMI_DATA 19
DP0_HPD 10
DP2_HPD 19
DP_INT_PWM 10
ALLOW_STOP 13
EC_THERM# 13,39,46
EC_THERM 32,39
DP0_TXN1_C
18
DP0_TXP1_C
18
DP_ENVDD 10
DP_ENBKL 10
DP0_TXN2_C
18
DP0_TXP2_C
18
DP0_TXN3_C
18
DP0_TXP3_C
18
+3VS
+1.35V_VDDQ
+1.35V_VDDQ
+3VS
+1.35V_VDDQ
+1.35V_VDDQ
+1.35V_VDDQ
+1.35V_VDDQ
+1.35V_VDDQ
+1.2VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
8 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
8 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
8 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
G
D
S
Q16
BSH111_SOT23-3
2
1
3
TC17
CC20 .1U_0402_16V7K
1 2
TC3
TC25
RC24 1K_0402_5%
1 2
RC18 39.2_0402_1%
1 2
TC11
TC2
RC21 300_0402_5%
1 2
TC10
TC18
TC26
RP3
1K_0804_8P4R_5%
1 8
2 7
3 6
4 5
TC5
CC21 .1U_0402_16V7K
1 2
TC13
RC11 300_0402_5%
1
2
TC6
RP4
1K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP5
1K_0804_8P4R_5%
1 8
2 7
3 6
4 5
TC19
RC107
1K_0402_5%
1
2
RC30
10K_0402_5%
1
2
RC20 0_0402_5%
@
1 2
RC7 150_0402_1%
1 2
RC17 39.2_0402_1%
@
1 2
TC20
RC22 300_0402_5%
@
1 2
TC4
RC29 0_0402_5%
@
1
2
CC23 .1U_0402_16V7K
@
1 2
G
D
S
Q12
BSH111_SOT23-3
2
1
3
RC6 1K_0402_5%
@
1
2
DISPLAY
PORT
0
DISPLAY
PORT
1
DISPLAY
PORT
2
CLK
SER.
CTRL
JTAG
SENSE
DISPLAY
PORT
MISC.
RSVD
TEST
UCPU1D
RICHLAND-A8-SERIES_BGA813
DP0_TXP[0]
H2
DP0_TXN[0]
H1
DP0_TXP[1]
H3
DP0_TXN[1]
H4
DP0_TXP[2]
F4
DP0_TXN[2]
F3
DP0_TXP[3]
F1
DP0_TXN[3]
F2
DP1_TXP[0]
E2
DP1_TXN[0]
E1
DP1_TXP[1]
D4
DP1_TXN[1]
D3
DP1_TXP[2]
D1
DP1_TXN[2]
D2
DP1_TXP[3]
C1
DP1_TXN[3]
C2
DP2_TXP[0]
B2
DP2_TXN[0]
A2
DP2_TXP[1]
B3
DP2_TXN[1]
A3
DP2_TXP[2]
B4
DP2_TXN[2]
A4
DP2_TXP[3]
B5
DP2_TXN[3]
A5
CLKIN_H
AL9
CLKIN_L
AK9
DISP_CLKIN_H
AL7
DISP_CLKIN_L
AK7
SVC
E5
SVD
E6
SVT
D6
SIC
AJ11
SID
AH11
RESET_L
AK11
PWROK
AH9
PROCHOT_L
AL12
THERMTRIP_L
AK5
ALERT_L
AR10
TDI
E11
TDO
G11
TCK
H12
TMS
F11
TRST_L
H11
DBRDY
E8
DBREQ_L
E7
VSS_SENSE
G6
VDDP_SENSE
H6
VDDNB_SENSE
H5
VDDIO_SENSE
G7
VDD_SENSE
G5
VDDR_SENSE
H7
DP0_AUXP
M5
DP0_AUXN
M6
DP1_AUXP
L5
DP1_AUXN
L6
DP2_AUXP
J5
DP2_AUXN
J6
DP3_AUXP
P5
DP3_AUXN
P6
DP4_AUXP
R5
DP4_AUXN
R6
DP5_AUXP
U5
DP5_AUXN
U6
DP0_HPD
M7
DP1_HPD
L7
DP2_HPD
J7
DP3_HPD
P7
DP4_HPD
R7
DP5_HPD
U7
DP_BLON
C6
DP_DIGON
D7
DP_VARY_BL
A6
DP_AUX_ZVSS
B6
TEST6
AL6
TEST9
Y23
TEST10
V23
TEST14
G9
TEST15
F9
TEST16
E9
TEST17
G8
TEST18
F12
TEST19
E12
TEST20
F14
TEST24
G12
TEST25_H
AJ8
TEST25_L
AH8
TEST28_H
G14
TEST28_L
H14
TEST30_H
V25
TEST30_L
Y25
TEST31
AH32
TEST32_H
R25
TEST32_L
T25
TEST35
AL5
DMAACTIVE_L
AP10
TEST4
T23
TEST5
R23
RSVD
L8
RSVD
P8
RSVD
AH12
RSVD
AJ12
RSVD
AK12
TC21
RC9 0_0603_5%
@
1 2
RC108
1K_0402_5%
1
2
CC19 .1U_0402_16V7K
1 2
TC12
CC24 .1U_0402_16V7K
@
1 2
RC19 0_0402_5%
@
1 2
RC28
30K_0402_1%
1 2
RC5 1.8K_0402_5%
1
2
RC15 1K_0402_5%
@
1 2
TC8
CC25 .1U_0402_16V7K
@
1 2
CC16 .1U_0402_16V7K
1 2
TC22
RC12 510_0402_1%
1 2
CC18 .1U_0402_16V7K
1 2
RC33 0_0402_5%
@
1 2
TC9
RC27
31.6K_0402_1%
1 2
E
B
C
QC4
MMBT3904_SOT23-3
2
3 1
TC23
TC1
RC16 1K_0402_5%
@
1 2
G
D
S
QC1
2N7002K_SOT23-3
2
1 3
RC13 510_0402_1%
1 2
RC25
10K_0402_5%
1 2
CC26 .1U_0402_16V7K
@
1 2
CC17 .1U_0402_16V7K
1 2
RC10 300_0402_5%
1
2
TC16
TC24
RC4 1.8K_0402_5%
1
2
CC22 0.1U_0402_16V4Z
1 2
RC14 1K_0402_5%
@
1 2
RC32 0_0402_5%
@
1
2
TC14
TC7

9. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Decoupling between CPU and DIMMs
across VDDIO and VSS split
3.2A
VDD
+CPU_CORE
VDDA
+2.5VS 0.75A
VDDNB
+CPU_CORE_NB
VDDIO
+1.5V
Consumption
60A
VDDP / VDDR
+1.2VS
Power Name
5A / 3.5A
37A
+APU_CORE Decoupling
330uF x 4 @ x1
22uF x 10
0.22uF x2
0.01uF x3
180pF x2 @ x1
+APU_CORE_NB Decoupling
330uF x2
22uF x2 @ x2
10uF x1
0.22uF x2
180pF x3
Group A
Group B
VDDA Decoupling
47uF x1
0.22uF x1
Comal
Pumori 2.0
P5WS5
330uF 220uF 47uF 22uF 10uF 4.7uF 0.22uF 0.01uF 3300pF 180pF
1nF
7 / 2
Pop / @
7 / 2
1
1
1
1
0
19/11 7 4 17 3
Decoupling Caps.
1 1 / 1 14/2
19/11 7 3
5 17 1 1 / 1 13/3
13 3 8 19 3 1 4 16
VDDR: 3500mA
VDDA: 750mA
VDDP: 5000mA +1.5VS
+CPU_CORE
+CPU_CORE_NB
+1.2VS
Power Sequence of APU
+1.5V
+2.5VS
On power team page
On power team page
Change 180p to 1000p by AMD
3/2 Reserve 4 pcs 180pF for EMI DDR noise issue
+1.5V / VDDIO Decoupling
220uF x1
22uF x4
4.7uF x4
0.22uF x6
180pF x1 @x1
VDDR Decoupling
Close JCPU1.AN14,AP14~15,AR14~15
10uF x2
0.22uF x2
180pF x2 @x2
0.01uFx2
4.7uFx2
220uF x1
VDDP Decoupling
Close JCPU1.AH3~7
22uF x4
0.22uF x2
180pF x2 @x2
Northbridge Power Pins
for Remote Decoupling
Change 180p to 1000p by AMD
12/22 for RF request
VDDP_CAP
VDDNB_CAP
VDDP_CAP
+APU_CORE
+APU_CORE_NB
+1.35V_VDDQ
+APU_CORE
+APU_CORE_NB
+1.35V_VDDQ
+1.35V_VDDQ
+1.2VS
+APU_VDDA
+1.2VS
+1.35V_VDDQ
+APU_VDDA
+1.35V_VDDQ
+1.2VS
+1.2VS
+2.5VS
+APU_CORE_NB
+1.2VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
9 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
9 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
9 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
CC152
0.22U_0402_10V4Z
@
1
2
CC120
180P_0402_50V8J
@EMI@
1
2
C122
15P_0402_50V8J
@
1
2
CC98
4.7U_0603_6.3V6K
1
2
CC99
4.7U_0603_6.3V6K
@
1
2
CC135
22U_0603_6.3V6M
@
1
2
TC15
CC106
0.22U_0402_10V4Z
1
2
CC155
1000P_0402_50V7K
@
1
2
CC102
0.22U_0402_10V4Z
1
2
CC157
.01U_0402_16V7K
@
1
2
CC100
4.7U_0603_6.3V6K
1
2
CC144
0.22U_0402_10V4Z
@
1
2
CC130
1000P_0402_50V7K
@
1
2
CC108
180P_0402_50V8J
@EMI@
1
2
C123
15P_0402_50V8J
@
1
2
CC136
180P_0402_50V8J
@EMI@
1
2
CC94
22U_0805_6.3V6M
@
1
2
CC105
0.22U_0402_10V4Z
@
1
2
CC168
180P_0402_50V8J
@EMI@
1
2
CC126
22U_0805_6.3V6M
1
2
CC101
4.7U_0603_6.3V6K
@
1
2
CC110
0.22U_0402_10V4Z
1
2
CC114
10U_0603_6.3V6M
1
2
CC118
0.22U_0402_10V4Z
@
1
2
CC119
1000P_0402_50V7K
@
1
2
CC150
0.22U_0402_10V4Z
@
1
2
CC112
180P_0402_50V8J
@EMI@
1
2
CC169
180P_0402_50V8J
@EMI@
1
2
LC1
FBMA-L11-201209-221LMA30T_0805
1
2
CC146
4.7U_0603_6.3V6K
@
1
2
CC137
47U_0805_4V6
1
2
CC148
4.7U_0603_6.3V6K
1
2
CC149
0.22U_0402_10V4Z
1
2
CC113
180P_0402_50V8J
@EMI@
1
2
CC159
1000P_0402_50V7K
@
1
2
CC166
180P_0402_50V8J
@EMI@
1
2
CC117
0.22U_0402_10V4Z
1
2
CC158
4.7U_0603_6.3V6K
@
1
2
CC104
0.22U_0402_10V4Z
1
2
CC127
22U_0805_6.3V6M
@
1
2
CC151
0.22U_0402_10V4Z
1
2
CC170
180P_0402_50V8J
@EMI@
1
2
CC138
0.22U_0402_10V4Z
@
1
2
CC134
22U_0603_6.3V6M
1
2
+
CC133
220U_D2_2VY_R15M
1
2
CC124
22U_0805_6.3V6M
1
2
CC116
4.7U_0603_6.3V6K
1
2
CC171
180P_0402_50V8J
@EMI@
1
2
CC107
0.22U_0402_10V4Z
@
1
2
CC122
22U_0805_6.3V6M
@
1
2
CC109
180P_0402_50V8J
@EMI@
1
2
CC125
10U_0603_6.3V6M
@
1
2
CC97
22U_0805_6.3V6M
1
2
CC131
180P_0402_50V8J
@EMI@
1
2
CC139
3300P_0402_50V7-K
@
1
2
UCPU1F
RICHLAND-A8-SERIES_BGA813
VSS
A17
VSS
A19
VSS
A21
VSS
A23
VSS
A25
VSS
A27
VSS
A29
VSS
A31
VSS
B1
VSS
C3
VSS
C4
VSS
C33
VSS
D5
VSS
D9
VSS
D11
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D25
VSS
D30
VSS
E4
VSS
E27
VSS
E29
VSS
E30
VSS
E33
VSS
F5
VSS
F6
VSS
F7
VSS
F8
VSS
F17
VSS
F20
VSS
F23
VSS
F28
VSS
F29
VSS
G1
VSS
G2
VSS
G4
VSS
G15
VSS
G19
VSS
G25
VSS
G26
VSS
G27
VSS
G33
VSS
H8
VSS
H9
VSS
H22
VSS
H26
VSS
J4
VSS
J8
VSS
J9
VSS
J11
VSS
J23
VSS
J25
VSS
J26
VSS
J27
VSS
J30
VSS
K9
VSS
K11
VSS
K12
VSS
K14
VSS
K15
VSS
K17
VSS
K19
VSS
K20
VSS
K22
VSS
L1
VSS
L2
VSS
L4
VSS
M8
VSS
M23
VSS
M25
VSS
N4
VSS
N11
VSS
N12
VSS
N14
VSS
N15
VSS
N17
VSS
N19
VSS
N20
VSS
N22
VSS
R1
VSS
R2
VSS
R4
VSS
T9
VSS
T11
VSS
T12
VSS
T14
VSS
T15
VSS
T17
VSS
T19
VSS
T20
VSS
T22
VSS
U4
VSS
W1
VSS
W2
VSS
W4
VSS
W5
VSS
W6
VSS
W7
VSS
Y9
VSS
Y11
VSS
Y12
VSS
Y14
VSS
Y15
VSS
Y17
VSS
Y19
VSS
Y20
VSS
Y22
VSS
AA4
VSS
AA5
VSS
AB7
VSS
AB8
VSS
AC1
VSS
AC2
VSS
AC4
VSS
AC9
VSS
AC11
VSS
AC12
VSS
AC14
VSS
AC15
VSS
AC17
VSS
AC19
VSS
AC20
VSS
AC22
VSS
AC23
VSS
AC25
VSS
AE4
VSS
AF9
VSS
AF11
VSS
AF12
VSS
AF14
VSS
AF15
VSS
AF17
VSS
AF19
VSS
AF20
VSS
AF22
VSS
AF23
VSS
AF25
VSS
AG1
VSS
AG2
VSS
AG4
VSS
AG9
VSS
AG11
VSS
AG26
VSS
AH7
VSS
AH17
VSS
AH20
VSS
AH23
VSS
AH26
VSS
AH30
VSS
AJ4
VSS
AJ5
VSS
AJ6
VSS
AJ7
VSS
AJ9
VSS
AJ14
VSS
AJ15
VSS
AJ19
VSS
AJ22
VSS
AJ27
VSS
AJ28
VSS
AJ33
VSS
AK6
VSS
AK8
VSS
AK25
VSS
AK28
VSS
AK30
VSS
AL1
VSS
AL2
VSS
AL4
VSS
AL8
VSS
AL11
VSS
AL27
VSS
AL28
VSS
AL33
VSS
AM5
VSS
AM7
VSS
AM9
VSS
AM11
VSS
AM15
VSS
AM17
VSS
AM19
VSS
AM21
VSS
AM23
VSS
AM25
VSS
AM29
VSS
AM30
VSS
AN3
VSS
AN4
VSS
AN33
VSS
AP5
VSS
AP9
VSS
AR2
VSS
AR5
VSS
AR9
VSS
AR17
VSS
AR19
VSS
AR21
VSS
AR23
VSS
AR25
VSS
AR27
VSS
AR29
VSS
AR31
CC167
180P_0402_50V8J
@EMI@
1
2
CC143
0.22U_0402_10V4Z
1
2
CC153
180P_0402_50V8J
@EMI@
1
2
CC129
0.22U_0402_10V4Z
@
1
2
CC123
10U_0603_6.3V6M
1
2
CC156
.01U_0402_16V7K
1
2
UCPU1E
RICHLAND-A8-SERIES_BGA813
VDD
J12
VDD
J14
VDD
J15
VDD
J17
VDD
J19
VDD
J20
VDD
J22
VDD
M11
VDD
M12
VDD
M14
VDD
M15
VDD
M17
VDD
M19
VDD
M20
VDD
M22
VDD
R8
VDD
R9
VDD
R11
VDD
R12
VDD
R14
VDD
R15
VDD
R17
VDD
R19
VDD
R20
VDD
R22
VDD
U8
VDD
V9
VDD
V11
VDD
V12
VDD
V14
VDD
V15
VDD
V17
VDD
V19
VDD
V20
VDD
V22
VDD
W8
VDD
AA8
VDD
AA9
VDD
AA11
VDD
AA12
VDD
AA14
VDD
AA15
VDD
AA17
VDD
AA19
VDD
AA20
VDD
AA22
VDD
AD9
VDD
AD11
VDD
AD12
VDD
AD14
VDD
AD15
VDD
AD17
VDD
AD19
VDD
AD20
VDD
AD22
VDD
AG12
VDD
AG14
VDD
AG15
VDD
AG17
VDD
AG19
VDD
AG20
VDD
AG22
VDDNB
A7
VDDNB
A8
VDDNB
A9
VDDNB
A10
VDDNB
A11
VDDNB
A12
VDDNB
A13
VDDNB
A14
VDDNB
A15
VDDNB
B7
VDDNB
B8
VDDNB
B9
VDDNB
B10
VDDNB
B11
VDDNB
B12
VDDNB
B13
VDDNB
B14
VDDNB
B15
VDDNB
C8
VDDNB
C10
VDDNB
C12
VDDNB
C14
VDDNB
D8
VDDNB
D10
VDDNB
D12
VDDNB_CAP
M9
VDDNB_CAP
N9
VDDIO
J33
VDDIO
K23
VDDIO
K25
VDDIO
L28
VDDIO
L30
VDDIO
L33
VDDIO
M27
VDDIO
N23
VDDIO
N25
VDDIO
N30
VDDIO
N33
VDDIO
P28
VDDIO
R27
VDDIO
R30
VDDIO
R33
VDDIO
U28
VDDIO
U30
VDDIO
U33
VDDIO
W28
VDDIO
W30
VDDIO
W33
VDDIO
AA23
VDDIO
AA25
VDDIO
AA27
VDDIO
AA30
VDDIO
AA33
VDDIO
AB28
VDDIO
AC30
VDDIO
AC33
VDDIO
AD23
VDDIO
AD25
VDDIO
AD27
VDDIO
AE28
VDDIO
AE30
VDDIO
AE33
VDDIO
AG23
VDDIO
AG25
VDDIO
AG27
VDDIO
AG30
VDDIO
AG33
VDDP
AM12
VDDP
AN12
VDDP
AP12
VDDP
AP13
VDDP
AR12
VDDP
AR13
VDDP_CAP
AA6
VDDP_CAP
AA7
VDDR
AN14
VDDR
AP14
VDDR
AP15
VDDR
AR14
VDDR
AR15
VDDA
AM13
VDDA
AM14
VDDNB
D14
CC161
22U_0603_6.3V6M
1
2
CC172
180P_0402_50V8J
@EMI@
1
2
CC140
1000P_0402_50V7K
1
2
C121
15P_0402_50V8J
@
1
2
CC145
4.7U_0603_6.3V6K
1
2
CC132
180P_0402_50V8J
@EMI@
1
2
CC147
4.7U_0603_6.3V6K
@
1
2
CC128
0.22U_0402_10V4Z
1
2
CC96
22U_0805_6.3V6M
@
1
2
CC121
180P_0402_50V8J
@EMI@
1
2
C120
15P_0402_50V8J
@
1
2
+
CC93
330U_D2_2V_Y
1
2
CC154
180P_0402_50V8J
@EMI@
1
2
CC115
10U_0603_6.3V6M
@
1
2
CC103
0.22U_0402_10V4Z
@
1
2
CC160
22U_0603_6.3V6M
@
1
2
CC111
0.22U_0402_10V4Z
@
1
2
CC95
22U_0805_6.3V6M
1
2

10. WWW.AliSaler.Com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Translator and eDP HPD
HPD
From Translator or Conn.
eDP Panel ENVDD
Panel PWM
Del reserved NMOS
Del reserved NMOS
12/06 Del FCH_CRT_HPD
4/17 change to 0ohm new symbol
Panel ENVDD
10/3 Eric Add DP_ENVDD control pin.
Panel ENBKL
11/13 Eric Add Panel EBBKL circuit.
Verify eDP on DB phase.
EDP_HPD DP0_HPD
DP_ENBKL ENBKL
DP_INT_PWM
8
APU_INVT_PWM 18
DP0_HPD 8
EDP_HPD
18
DP_ENVDD
8
APU_ENVDD 20
ENBKL 32
APU_PCIE_RST# 13,23,31
DP_ENBKL
8
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
10 47
Monday, October 21, 2013
2012/11/07 2012/11/07 Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
10 47
Monday, October 21, 2013
2012/11/07 2012/11/07 Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
10 47
Monday, October 21, 2013
2012/11/07 2012/11/07
RC35
0_0402_5%
@
1 2
G
D
S
Q1
2N7002K_SOT23-3
APUEDP@
2
1
3
E
B
C
Q153
MMBT3904_SOT23-3
2
3
1
E
B
C
Q3A1
MMBT3904_SOT23-3
2
3
1
E
B
C
Q2
MMBT3904_SOT23-3
APUEDP@
2
3
1
RC36
4.7K_0402_5%
1
2
R580
4.7K_0402_5%
1
2
R2
4.7K_0402_5%
APUEDP@
1
2
G
D
S
Q152
2N7002K_SOT23-3
2
1
3
R1
100K_0402_5%
APUEDP@
1
2
R584 0_0402_5%
@
1 2
D5 RB751V-40_SOD323-2
@
2 1
R583
100K_0402_5%
1
2
RC39
4.7K_0402_5%
1
2
R582 2.2K_0402_5%
1 2
Q3B
2N7002KDW_SOT363-6
3
5
4
R581
100K_0402_5%
1
2
RC37
47K_0402_5%
1
2
RC38
2.2K_0402_5%
1 2
R3 2.2K_0402_5%
APUEDP@
1 2
C74
100P_0402_50V8J
@ESD@
1
2
R4
100K_0402_5%
APUEDP@
1
2

11. WWW.AliSaler.Com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA
DDR3 SO-DIMM A
Layout Note:
Place near JDIMM1
Layout Note:
Place near JDIMM1.203 & JDIMM1.204
DDR3 SO-DIMM A
LA-8661P
All VREF traces should
have 20 mil trace width
<Address: 00>
DIMM_A REV H:4mm
+VREF_DQ 15mil
L
SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue
3/2 Reserve 4 pcs 180pF for EMI DDR noise issue
+VREF_CB 15mil
DDRA_SDQ26
DDRA_SDQS6
DDRA_SDQ2
DDRA_SDQ25
DDRA_SDQ35
DDRA_SMA12
DDRA_SDQS4
DDRA_SDQ42
DDRA_SDQ27
DDRA_CKE0
DDRA_SDQ59
DDRA_SMA3
DDRA_SCS1#
DDRA_SWE#
DDRA_SDQ57
DDRA_SDQ0
DDRA_SDM0
DDRA_SDQ51
DDRA_SDQ19
DDRA_SDQS2
DDRA_SDQ33
DDRA_SDQ58
DDRA_SDM5
DDRA_SMA8
DDRA_SDQ10
DDRA_SMA10
DDRA_SDQ3
DDRA_SDQS6#
DDRA_SDQ1
DDRA_SDQ40
DDRA_SMA9
DDRA_SDQ16
DDRA_SDQS4#
DDRA_SDM3
DDRA_SDQ49
DDRA_SBS2#
DDRA_SDQ9
DDRA_SDM7
DDRA_SMA1
DDRA_SBS0#
DDRA_SCAS#
DDRA_SMA5
DDRA_SDQS1#
+V_DDR_REFA
DDRA_SDQ24
DDRA_SDQ56
DDRA_SDQ18
DDRA_SDQ43
DDRA_SDQ34
DDRA_SDQ48
DDRA_SDQS2#
DDRA_SDQ11
DDRA_CLK0
DDRA_CLK0#
DDRA_SDQ32
DDRA_SMA13
DDRA_SDQ50
DDRA_SDQ8
DDRA_SDQS1
DDRA_SDQ41
DDRA_SDQ17
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
MEM_MA_EVENT#
DDRA_SDQ36
DDRA_SDQ63
DDRA_SDQ5
DDRA_SDQ22
DDRA_SDQ14
DDRA_SDQS0#
DDRA_SDM6
DDRA_CKE1
DDRA_SMA15
DDRA_SDQ31
DDRA_SDQ12
DDRA_SDQ6
DDRA_SDQ39
DDRA_SBS1#
DDRA_SMA7
DDRA_SDQS0
DDRA_SMA0
DDRA_SDM2
DDRA_SDQS7
DDRA_SDM1
DDRA_SDQ46
DDRA_SDQ28
DDRA_SDQS5#
DDRA_SDM4
DDRA_SDQ4
DDRA_SDQ30
DDRA_SDQ44
DDRA_SRAS#
DDRA_SDQS3
DDRA_SCS0#
DDRA_SMA6
MEM_MA_RST#
DDRA_SDQS7#
DDRA_SDQ29
DDRA_SDQ52
DDRA_SDQS5
DDRA_SDQ54
DDRA_SDQ45
DDRA_SDQ7
DDRA_SDQ13
DDRA_SDQ20
DDRA_SDQ60
DDRA_ODT0
DDRA_SDQ37
DDRA_SMA14
DDRA_SDQ55
DDRA_SMA4
DDRA_SDQ21
DDRA_SDQ62
DDRA_SDQ15
DDRA_SDQ23
DDRA_SDQ53
DDRA_SDQ47
DDRA_ODT1
DDRA_CLK1
DDRA_CLK1#
DDRA_SDQ38
DDRA_SDQS3#
DDRA_SMA11
DDRA_SDQ61
DDRA_SMA2
DDRA_CKE0
7
DDRA_SCS1#
7
DDRA_SWE#
7
DDRA_SBS2#
7
DDRA_SBS0#
7
DDRA_SCAS#
7
DDRA_CLK0
7
DDRA_CLK0#
7
DDRA_SDQS1#
7
DDRA_SDQS1
7
DDRA_SDQS2#
7
DDRA_SDQS2
7
DDRA_SDQS4#
7
DDRA_SDQS4
7
DDRA_SDQS6#
7
DDRA_SDQS6
7
DDRA_SDQ[0..63]
7
DDRA_SDM[0..7]
7
DDRA_SMA[0..15]
7
DDRA_SBS1# 7
DDRA_SRAS# 7
DDRA_SCS0# 7
MEM_MA_RST# 7
DDRA_ODT0 7
DDRA_ODT1 7
DDRA_CLK1# 7
DDRA_CLK1 7
DDRA_CKE1 7
FCH_SDATA0 12,15
FCH_SCLK0 12,15
DDRA_SDQS3 7
DDRA_SDQS0 7
DDRA_SDQS3# 7
DDRA_SDQS0# 7
DDRA_SDQS5 7
DDRA_SDQS5# 7
DDRA_SDQS7 7
DDRA_SDQS7# 7
MEM_MA_EVENT# 7
+1.35V_VDDQ
+0.675VS
+3VS
+V_DDR_REFA +1.35V_VDDQ
+0.675VS
+1.35V_VDDQ
+VREF_CA
+1.35V_VDDQ +1.35V_VDDQ
+1.35V_VDDQ
+V_DDR_REFA
+1.35V_VDDQ
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
A
SCHEMATIC, MB A9851
C
11 47
Monday, October 21, 2013
2012/11/07 2012/11/07
4019NK
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
A
SCHEMATIC, MB A9851
C
11 47
Monday, October 21, 2013
2012/11/07 2012/11/07
4019NK
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
A
SCHEMATIC, MB A9851
C
11 47
Monday, October 21, 2013
2012/11/07 2012/11/07
4019NK
CD25
0.1U_0402_16V7K
@
1
2
CD59
180P_0402_50V8J
@
1
2
CD3
1U_0402_6.3V6K
@
1
2
CD26
0.1U_0402_16V7K
@
1
2
CD17
10U_0603_6.3V6M
@
1
2
CD13
10U_0603_6.3V6M
@
1
2
CD27
0.1U_0402_16V7K
@
1
2
JDIMM1
LCN_DAN06-K4406-0102
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
RD5 10K_0402_5%
1 2
CD19
0.1U_0402_16V7K
1
2
CD28
0.1U_0402_16V7K
@
1
2
RD10
1K_0402_1%
1
2
CD18
0.1U_0402_16V7K
1
2
CD24
0.1U_0402_16V7K
@
1
2
CD5
1U_0402_6.3V6K
@
1
2 CD2
1000P_0603_50V7K
1
2
RD12
1K_0402_1%
1
2
CD1
0.1U_0402_16V7K
1
2
RD11
1K_0402_1%
1
2
CD7
10U_0603_6.3V6M
@
1
2
CD57
180P_0402_50V8J
@
1
2
RD13
1K_0402_1%
1
2
CD21
0.1U_0402_16V7K
1
2
CD10
0.1U_0402_16V7K
1
2
CD6
1U_0402_6.3V6K
1
2
RD6
0_0402_5%
@
1
2
CD12
10U_0603_6.3V6M
1
2
+ CD22
47U 6.3V M B1 ESR70M
@
1
2
CD4
1U_0402_6.3V6K
1
2
CD9
10U_0603_6.3V6M
1
2
CD14
10U_0603_6.3V6M
1
2
CD20
0.1U_0402_16V7K
1
2
CD8
10U_0603_6.3V6M
1
2
CD23
2.2U_0603_6.3V6K
1
2
CD58
180P_0402_50V8J
@
1
2
CD16
10U_0603_6.3V6M
1
2
CD11
1000P_0603_50V7K
1
2
CD15
10U_0603_6.3V6M
@
1
2
CD60
180P_0402_50V8J
@
1
2

12. WWW.AliSaler.Com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA
DDR3 SO-DIMM B
Layout Note:
Place near JDIMM1
Layout Note:
Place near JDIMM1.203 & JDIMM1.204
DDR3 SO-DIMM B
Standard
All VREF traces should
have 20 mil trace width
10/05 change to PH.
15mil
<Address: 01>
+VREF_DQ 15mil
L
DIMM_B REV H:8mm
+VREF_CB 15mil
L
01/15 update DDR address 10 to 01
for common design
10/03 change to +V_DDR_REFB
3/2 Reserve 4 pcs 180pF for EMI DDR noise issue
SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue
+V_DDR_REFB
MEM_MB_EVENT#
DDRB_SDQ40
DDRB_SDQ38
DDRB_SDQ52
DDRB_SDQS6
DDRB_SDQ26
DDRB_SDQ63
DDRB_SDQ36
DDRB_SDQ35
DDRB_SDQ25
DDRB_SDQ22
DDRB_SDQ5
DDRB_SDQ2
DDRB_SDQS0#
DDRB_SDQ14
DDRB_SMA12
DDRB_CKE1
DDRB_SDQ42
DDRB_SDM6
DDRB_SDQS4
DDRB_SMA15
DDRB_SDQ27
DDRB_SDQ12
DDRB_CKE0
DDRB_SDQ31
DDRB_SMA3
DDRB_SDQ59
DDRB_SBS1#
DDRB_SDQ39
DDRB_SCS1#
DDRB_SDQ6
DDRB_SDQS0
DDRB_SMA7
DDRB_SWE#
DDRB_SMA0
DDRB_SDM2
DDRB_SDQ0
DDRB_SDQ46
DDRB_SDQ57
DDRB_SDM1
DDRB_SDQS7
DDRB_SDM0
DDRB_SDQ28
DDRB_SDM4
DDRB_SDQ19
DDRB_SDQ51
DDRB_SDQS5#
DDRB_SDQS2
DDRB_SDQ30
DDRB_SDQ4
DDRB_SDQ33
DDRB_SRAS#
DDRB_SDQ44
DDRB_SDQS3
DDRB_SDM5
DDRB_SDQ58
DDRB_SMA8
DDRB_SCS0#
DDRB_SMA10
DDRB_SMA6
DDRB_SDQ10
DDRB_SDQS6#
DDRB_SDQS7#
MEM_MB_RST#
DDRB_SDQ3
DDRB_SDQ16
DDRB_SMA9
DDRB_SDQ1
DDRB_SDQS4#
DDRB_SDQ29
DDRB_SDQ49
DDRB_SDQ54
DDRB_SDQS5
DDRB_SDM3
DDRB_SDQ9
DDRB_SDQ45
DDRB_SBS2#
DDRB_SDQ20
DDRB_SDQ13
DDRB_SDQ7
DDRB_SMA1
DDRB_SDM7
DDRB_SBS0#
DDRB_SDQ60
DDRB_SDQ37
DDRB_ODT0
DDRB_SCAS#
DDRB_SDQ55
DDRB_SMA14
DDRB_SDQS1#
DDRB_SMA5
DDRB_SDQ21
DDRB_SMA4
DDRB_SDQ62
DDRB_SDQ15
DDRB_SDQ24
DDRB_SDQ47
DDRB_SDQ53
DDRB_SDQ23
DDRB_SDQ56
DDRB_SDQ43
DDRB_SDQ18
DDRB_ODT1
DDRB_CLK1#
DDRB_CLK1
DDRB_SDQ34
DDRB_SDQS2#
DDRB_SDQ48
DDRB_CLK0#
DDRB_CLK0
DDRB_SDQ11
DDRB_SDQ50
DDRB_SMA11
DDRB_SMA13
DDRB_SDQS3#
DDRB_SDQ32
DDRB_SMA2
DDRB_SDQ61
DDRB_SDQS1
DDRB_SDQ8
DDRB_SDQ17
DDRB_SDQ41
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
DDRB_SCS1#
7
DDRB_CKE0
7
DDRB_SCS0# 7
DDRB_SRAS# 7
DDRB_SWE#
7
DDRB_SBS1# 7
DDRB_SCAS#
7
DDRB_SBS0#
7
DDRB_SBS2#
7
MEM_MB_RST# 7
DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_ODT1 7
DDRB_ODT0 7
DDRB_CKE1 7
DDRB_CLK0#
7
DDRB_CLK0
7
DDRB_SDQS2
7
DDRB_SDQS2#
7
DDRB_SDQS4
7
DDRB_SDQS4#
7
DDRB_SDQS6
7
DDRB_SDQS6#
7
DDRB_SDQS0# 7
DDRB_SDQS0 7
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_SDQS5 7
DDRB_SDQS5# 7
DDRB_SDQS7 7
DDRB_SDQS7# 7
FCH_SDATA0 11,15
FCH_SCLK0 11,15
DDRB_SDQS1#
7
DDRB_SDQS1
7
MEM_MB_EVENT# 7
DDRB_SDQ[0..63]
7
DDRB_SDM[0..7]
7
DDRB_SMA[0..15]
7
+1.35V_VDDQ
+0.675VS
+V_DDR_REFB
+VREF_CB
+3VS
+0.675VS
+1.35V_VDDQ
+1.35V_VDDQ
+3VS
+1.35V_VDDQ
+1.35V_VDDQ
+V_DDR_REFB
+1.35V_VDDQ
+1.35V_VDDQ
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
A
SCHEMATIC, MB A9851
12 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
A
SCHEMATIC, MB A9851
12 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
A
SCHEMATIC, MB A9851
12 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
CD29
1000P_0603_50V7K
1
2
CD31
2.2U_0603_6.3V6K
1
2
RD9
0_0402_5%
@
1
2
RD15
1K_0402_1%
1
2
RD17
1K_0402_1%
1
2
CD47
0.1U_0402_16V7K
1
2
CD54
1U_0402_6.3V6K
@
1
2
RD16
1K_0402_1%
1
2
CD48
1U_0402_6.3V6K
1
2
CD50
0.1U_0402_16V7K
1
2
CD61
180P_0402_50V8J
@
1
2
CD45
10U_0603_6.3V6M
1
2
CD43
0.1U_0402_16V7K
1
2
CD63
180P_0402_50V8J
@
1
2
CD42
10U_0603_6.3V6M
1
2
CD52
10U_0603_6.3V6M
1
2
CD62
180P_0402_50V8J
@
1
2
CD35
0.1U_0402_16V7K
@
1
2
CD30
1000P_0603_50V7K
1
2
CD44
0.1U_0402_16V7K
1
2
CD64
180P_0402_50V8J
@
1
2
CD32
0.1U_0402_16V7K
@
1
2
+ CD36
47U 6.3V M B1 ESR70M
@
1
2
CD46
10U_0603_6.3V6M
@
1
2
CD51
1U_0402_6.3V6K
1
2
CD49
10U_0603_6.3V6M
1
2
CD33
0.1U_0402_16V7K
@
1
2
RD7 10K_0402_5%
1 2
CD53
10U_0603_6.3V6M
@
1
2
CD56
10U_0603_6.3V6M
@
1
2
CD34
0.1U_0402_16V7K
@
1
2
CD41
1U_0402_6.3V6K
@
1
2
CD37
10U_0603_6.3V6M
1
2
CD39
0.1U_0402_16V7K
1
2
CD55
0.1U_0402_16V7K
1
2
RD14
1K_0402_1%
1
2
CD40
10U_0603_6.3V6M
@
1
2
CD38
0.1U_0402_16V7K
@ 1
2
JDIMM2
LCN_DAN06-K4406-0102
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206

13. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
For "EXT" CLK mode, input to PCIE,
Close to BOLTON-M2
PCI Host Bus Reset (To EC)
VGA
APU
APU DISP
Wireless LAN
W>=15mils
01/15 change R860 to Jump for Clear CMOS
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.
NSS
SS
SS
Ethernet LAN DMA_ACTIVE# : IN/OD, 0.8V threshold
APU_PG/APU_RST#/LDT_STP# : OD pin
LDT_STP : No use, NC
PROCHOT# : IN, 0.8V threshold
for ESD Close FCH Side
VGA_PWRGD_R Change to GPIO51
C1205,C1206
Change for G3
RTC timing issue
<improve amplitude>
Del GPP PCI-E
Del MIN2,Card reader, USB 3.0 IC
ABO connect to USB3.0 PHY.
Del USB3.0_CLKREQ# PH.
Del USB3.0_CLKREQ#
20mils
Update to +3VLP
25M_X1 and 25M_X1_R=50ohm, 4mil
25M_X2=50ohm, 4mil
L
32K_X1=50ohm, 4mil,<1500mil
32K_X2=50ohm, 4mil,<1500mil
L
RTC_CLK_R=50ohm, 4mil
RTC_CLK=50ohm, 4mil
L
PCIE_CALRP R=50ohm, 4mil,<1000mil
PCIE_CALRN R=50ohm, 4mil,<1000mi
L
D23 close to U25 (FCH)
L
W>=15mils
W>=15mils
Delete GPU
1202 Calvin
Delete GPU
1202 Calvin
11/08 Reserved BIOS setting
PX4
FCH_GPIO31
FCH_GPIO30
Board ID
0 0
1
0
1 0
1 1
Reserve
UMA
DIS
Board ID
20mil
For EMI Requirement Close to U25
02/02 change +3VALW to +3VS for power rail leakage
card Reader
10/4 Eric Del.
For PCIE device reset on FS1
(GFX,GLAN,WLAN,LVDS Travis)
10/4 Eric Del.
10/22 Eric modify 32.768 footprint.
12/25 Eric Del TP_INT#
12/27 Eric Del J1 jumper.
ALLOW_STOP
UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3
PCIE_CALRP
PCIE_CALRN
CLK_CALRN
UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
APU_DISP_CLKP
UMI_FTX_C_MRX_P1
APU_DISP_CLKN
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
APU_CLKP
UMI_FTX_C_MRX_N2
APU_CLKN
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3
25M_X2
APU_PCIE_RST#_C
LPC_CLK1
RTCVCC_R
32K_X1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SERIRQ
LPC_FRAME#
25M_X1
EC_THERM_R#
32K_X2
RTC_CLK_R
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
APU_RST#
CRCLK_REQ#
APU_PWRGD
FCH_GPIO30
FCH_GPIO31
FCH_GPIO30
PM_CLKRUN#
LPC_CLK0_EC
LPC_CLK0_EC_R
CLK_PCIE_CR
CLK_PCIE_CR#
FCH_GPIO31
32K_X1
32K_X2
APU_PCIE_RST#_C
ALLOW_STOP 8
EC_THERM# 39,46,8
PLT_RST#
25,32,36
UMI_FTX_C_MRX_P0
6
UMI_FTX_C_MRX_N0
6
UMI_FTX_C_MRX_P1
6
UMI_FTX_C_MRX_N1
6
UMI_FTX_C_MRX_P2
6
UMI_FTX_C_MRX_N2
6
UMI_FTX_C_MRX_P3
6
UMI_FTX_C_MRX_N3
6
UMI_MTX_C_FRX_P0
6
UMI_MTX_C_FRX_N0
6
UMI_MTX_C_FRX_P1
6
UMI_MTX_C_FRX_N1
6
UMI_MTX_C_FRX_P2
6
UMI_MTX_C_FRX_N2
6
UMI_MTX_C_FRX_P3
6
UMI_MTX_C_FRX_N3
6
LPC_CLK1 16
RTC_CLK 16,32
LPC_AD0 23,32,36
LPC_AD1 23,32,36
LPC_AD2 23,32,36
LPC_AD3 23,32,36
SERIRQ 32,36
LPC_FRAME# 23,32,36
PCI_AD27 16
PCI_AD26 16
PCI_AD25 16
PCI_AD24 16
PCI_AD23 16
APU_CLKP
8
APU_CLKN
8
APU_DISP_CLKP
8
APU_DISP_CLKN
8
LPC_CLK0_EC 16,32
CLK_PCIE_LAN
24
CLK_PCIE_LAN#
24
CLK_PCIE_MINI1
23
CLK_PCIE_MINI1#
23
APU_RST# 8
APU_PWRGD 46,8
GPIO0 32
ACCEL_INT# 36
PM_CLKRUN# 32
HDDHALT_LED# 25
CLK_PCIE_CR
25
CLK_PCIE_CR#
25
APU_PCIE_RST# 10,23,31
PCI_CLK4 16
PCI_CLK3 16
PCI_CLK1 15,16
+1.1VS_CKVDD
+PCIE_VDDR_FCH
+RTCVCC
+3VLP
+RTCBATT
+RTCBATT
+3VS
+3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
13 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
13 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
13 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
RH6 2K_0402_1%
1 2
C75
100P_0402_50V8J
ESD@
1
2
RF15
680P_0402_50V7K
@RF@
1
2
CH12
0.1U_0402_16V4Z
1
2
RH7
100K_0402_5%
@
1
2
JRTC1
ACES_50271-0020N-001
@
1
1
2
2
GND
3
GND
4
RH126
2.2K_0402_5%
Touch@
1
2
X1
25MHZ_10PF_X1E000311000900
IN
1
GND
2
OUT
3
GND
4
RH17 510_0402_5%
1 2
RH11 33_0402_5%
RF@
1 2
HUDSON-2
PCI
CLKS
PCI
EXPRESS
INTERFACES
PCI
INTERFACE
CLOCK
GENERATOR
LPC
APU
S5
PLUS
UH1A
BOLTON-M2_FCBGA656
PCIE_RST#
AE2
A_RST#
AD5
UMI_TX0P
AE30
UMI_TX0N
AE32
UMI_TX1P
AD33
UMI_TX1N
AD31
UMI_TX2P
AD28
UMI_TX2N
AD29
UMI_TX3P
AC30
UMI_TX3N
AC32
UMI_RX0P
AB33
UMI_RX0N
AB31
UMI_RX1P
AB28
UMI_RX1N
AB29
UMI_RX2P
Y33
UMI_RX2N
Y31
UMI_RX3P
Y28
UMI_RX3N
Y29
PCIE_CALRP
AF29
PCIE_CALRN
AF31
GPP_TX0P
V33
GPP_TX0N
V31
GPP_TX1P
W30
GPP_TX1N
W32
GPP_TX2P
AB26
GPP_TX2N
AB27
GPP_TX3P
AA24
GPP_TX3N
AA23
GPP_RX0P
AA27
GPP_RX0N
AA26
GPP_RX1P
W27
GPP_RX1N
V27
GPP_RX2P
V26
GPP_RX2N
W26
GPP_RX3P
W24
GPP_RX3N
W23
CLK_CALRN
F27
PCIE_RCLKP
G30
PCIE_RCLKN
G28
DISP_CLKP
R26
DISP_CLKN
T26
DISP2_CLKP
H33
DISP2_CLKN
H31
APU_CLKP
T24
APU_CLKN
T23
SLT_GFX_CLKP
J30
SLT_GFX_CLKN
K29
GPP_CLK0P
H27
GPP_CLK0N
H28
GPP_CLK1P
J27
GPP_CLK1N
K26
GPP_CLK2P
F33
GPP_CLK2N
F31
GPP_CLK3P
E33
GPP_CLK3N
E31
GPP_CLK4P
M23
GPP_CLK4N
M24
GPP_CLK5P
M27
GPP_CLK5N
M26
GPP_CLK6P
N25
GPP_CLK6N
N26
GPP_CLK7P
R23
GPP_CLK7N
R24
GPP_CLK8P
N27
GPP_CLK8N
R27
14M_25M_48M_OSC
J26
25M_X1
C31
25M_X2
C33
PCICLK0
AF3
PCICLK1/GPO36
AF1
PCICLK2/GPO37
AF5
PCICLK3/GPO38
AG2
PCICLK4/14M_OSC/GPO39
AF6
PCIRST#
AB5
AD0/GPIO0
AJ3
AD1/GPIO1
AL5
AD2/GPIO2
AG4
AD3/GPIO3
AL6
AD4/GPIO4
AH3
AD5/GPIO5
AJ5
AD6/GPIO6
AL1
AD7/GPIO7
AN5
AD8/GPIO8
AN6
AD9/GPIO9
AJ1
AD10/GPIO10
AL8
AD11/GPIO11
AL3
AD12/GPIO12
AM7
AD13/GPIO13
AJ6
AD14/GPIO14
AK7
AD15/GPIO15
AN8
AD16/GPIO16
AG9
AD17/GPIO17
AM11
AD18/GPIO18
AJ10
AD19/GPIO19
AL12
AD20/GPIO20
AK11
AD21/GPIO21
AN12
AD22/GPIO22
AG12
AD23/GPIO23
AE12
AD24/GPIO24
AC12
AD25/GPIO25
AE13
AD26/GPIO26
AF13
AD27/GPIO27
AH13
AD28/GPIO28
AH14
AD29/GPIO29
AD15
AD30/GPIO30
AC15
AD31/GPIO31
AE16
CBE0#
AN3
CBE1#
AJ8
CBE2#
AN10
CBE3#
AD12
FRAME#
AG10
DEVSEL#
AK9
IRDY#
AL10
TRDY#
AF10
PAR
AE10
STOP#
AH1
PERR#
AM9
SERR#
AH8
REQ0#
AG15
REQ1#/GPIO40
AG13
REQ2#/CLK_REQ8#/GPIO41
AF15
REQ3#/CLK_REQ5#/GPIO42
AM17
GNT0#
AD16
GNT1#/GPO44
AD13
GNT2#/SD_LED/GPO45
AD21
GNT3#/CLK_REQ7#/GPIO46
AK17
CLKRUN#
AD19
LOCK#
AH9
INTE#/GPIO32
AF18
INTF#/GPIO33
AE18
INTG#/GPIO34
AC16
INTH#/GPIO35
AD18
LPCCLK0
B25
LPCCLK1
D25
LAD0
D27
LAD1
C28
LAD2
A26
LAD3
A29
LFRAME#
A31
LDRQ0#
B27
LDRQ1#/CLK_REQ6#/GPIO49
AE27
SERIRQ/GPIO48
AE19
DMA_ACTIVE#
G25
PROCHOT#
E28
APU_PG
E26
LDT_STP#
G26
APU_RST#
F26
S5_CORE_EN
H7
RTCCLK
F1
INTRUDER_ALERT#
F3
VDDBT_RTC_G
E6
32K_X1
G2
32K_X2
G4
RH12 0_0402_5%
@
1 2
RH5 590_0402_1%
1 2
BAV70W_SOT323-3
D1
2
3
1
RH127
2.2K_0402_5%
@
1
2
CH16
22P_0402_50V8J
1
2
CH7 .1U_0402_16V7K
1 2
CH3 .1U_0402_16V7K
1 2
RH2 33_0402_5%
@
1 2
RF10
33_0402_5%
RF@
1
2
CH4 .1U_0402_16V7K
1 2
CH2 .1U_0402_16V7K
1 2
RF14
680P_0402_50V7K
@RF@
1
2
TH2
CH13
1U_0402_6.3V6K
1
2
RH10 8.2K_0402_5%
1 2
CH101
0.1U_0402_16V4Z
ESD@
1
2
UH2
NC7SZ08P5X_NL_SC70-5
@
B
2
A
1 Y
4
P
5
G
3
CH11 10P_0402_50V8J
1
2
RF16
680P_0402_50V7K
@RF@
1
2
RH16
1M_0402_5%
R5
0_0402_5%
@ 1
2
RH1 33_0402_5%
1 2
RH9 2K_0402_1%
1 2
RH8
100K_0402_5%
@
1
2
RH3
8.2K_0402_5%
@
1
2
CH8 .1U_0402_16V7K
1 2
RH13 22_0402_5%
1 2
TH3
RH4 0_0402_5%
@
1 2
RF11
33_0402_5%
RF@ 1
2
CH18 150P_0402_50V8J
1 2
RH130 20M_0402_5%
1 2
TH1
RH14
1K_0402_5%
1
2
CH5 .1U_0402_16V7K
1 2
CH1 .1U_0402_16V7K
1 2
CH9 15P_0402_50V8J
RF@
1 2
CH15
22P_0402_50V8J
1
2
RF12
33_0402_5%
RF@
1
2
CH10 10P_0402_50V8J
1
2
CH14
0.1U_0402_16V4Z
1
2
CH6 .1U_0402_16V7K
1 2
YC1
32.768KHZ Q13FC1350000500
1 2

14. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
FCH Schematics Check List V1.20
GBE_COL / GBE_CRS / GBE_MDIO
GBE_RXERR / Left unconnected.
FCH SCL V1.20 19-35
GBE_PHY_INTR
Pulled-up to +3.3V_S5 with a 10-KΩ 5% resistor.
FCH SCL v1.20 #19-85
Removed RGMII/MII support and updated termination
requirements for GBE_COL, GBE_CRS, GBE_RXERR
and GBE_MDIO when RGMII/MII interface is not used.
FCH DGv1.20 / SCL v1.20
Enabled integrated pull-down/up and left unconnected.
Confirm BT_ON# or BT_ON
Del W_DISABLE#_2
SATA_CALRP=35ohm,<1000mil
SATA_CALRN=35ohm,<1000mi
L
HDD1
Check?
10/03 Eric del mSATA by customer
12/19 remove RH29, RH31 for HW request
4MB SPI ROM
& Non-share ROM.
Check CS# PU R 1kor10k and pop/nopop
SCL v1.20 : If an SPI ROM is shared between
the FCH and the Embedded Controller
a 10-K pull-up resistor to +3.3V_S5 is installed.
Add for EMI 201011291330
10/4 Eric Del.
10/9 Eric change RH20 form 0 to 33(EMI).
10/17 Eric add GPIO of 56,58,54.
10/17 Eric modify BT_ON to pull low.
M5
FCH_SPI_MISO
GBE_PHY_INTR
FCH_SPI_MOSI
SATA_CALRP
SATA_CALRN
BT_ON
SATA_LED#
FCH_SPI_CS1#
FCH_SPI_WP#
WL_OFF#
SATA_STX_DRX_P0
SATA_STX_DRX_N0
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0 FCH_SPI_CLK_ROM
FCH_SPI_MOSI
FCH_SPI_HOLD#
FCH_SPI_CS1#
FCH_SPI_MISO
FCH_SPI_WP#
LAN_PWR_EN
TOUCH_PAD_PWREN#
FCH_SPI_CS1#
FCH_SPI_MISO
FCH_SPI_MOSI
FCH_SPI_CLK
FCH_SPI_HOLD#
FCH_SPI_CS1#
FCH_SPI_WP#
GBE_PHY_INTR
L2
K5
K6
K6
K5
N2
N2
N4
N4
M5
M3
M6
M6
BT_ON
LANCB_DET#_PCH
LAN_PWR_EN
TOUCH_PAD_PWREN#
L2
K3
K3
M3
FCH_SPI_CLK
FCH_SPI_CLK_R
FCH_SPI_CLK_ROM
SATA_LED#
25
BT_ON
23
WL_OFF#
23
SATA_STX_DRX_P0
22
SATA_STX_DRX_N0
22
SATA_DTX_SRX_P0
22
SATA_DTX_SRX_N0
22
LAN_PWR_EN
31
LANCB_DET#_PCH
31
TOUCH_PAD_PWREN#
33
FCH_SPI_CS1# 32
FCH_SPI_MISO 32
FCH_SPI_CLK 32
FCH_SPI_MOSI 32
+AVDD_SATA
+3VS
+3VALW
+3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
14 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
14 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
14 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
RP16
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RH21
1K_0402_1% 1
2
UH3
MX25L3206EM2I-12G_SO8
SA00003K810
CS#
1
SO/SIO1
2
WP#
3
GND
4
VCC
8
HOLD#
7
SCLK
6
SI/SIO0
5
RP12
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RH22
931_0402_1% 1
2
RP13
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RF17
680P_0402_50V7K
@RF@
1
2
RH20 33_0402_5%
EMI@
1 2
RH25 10K_0402_5%
@
1 2
RP15
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP14
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RH23 715_0402_1%
1 2
CF15 39P_0402_50V8J
@RF@
1 2
CH17
0.1U_0402_16V4Z
1
2
HUDSON-2
SERIAL
ATA
SD
CARD
GBE
LAN
SPI
ROM
VGA
DAC
VGA
MAINLINK
HW MONITOR
UH1B
BOLTON-M2_FCBGA656
SATA_TX0P
AK19
SATA_TX0N
AM19
SATA_RX0N
AL20
SATA_RX0P
AN20
SATA_TX1P
AN22
SATA_TX1N
AL22
SATA_RX1N
AH20
SATA_RX1P
AJ20
SATA_TX2P
AJ22
SATA_TX2N
AH22
SATA_RX2N
AM23
SATA_RX2P
AK23
SATA_TX3P
AH24
SATA_TX3N
AJ24
SATA_RX3N
AN24
SATA_RX3P
AL24
SATA_TX4P
AL26
SATA_TX4N
AN26
SATA_RX4N
AJ26
SATA_RX4P
AH26
SATA_TX5P
AN29
SATA_TX5N
AL28
SATA_RX5N
AK27
SATA_RX5P
AM27
NC6
AL29
NC7
AN31
NC8
AL31
NC9
AL33
NC10
AH33
NC11
AH31
NC12
AJ33
NC13
AJ31
SATA_X2
AG21
SATA_X1
AF21
SATA_CALRP
AF28
SATA_CALRN
AF27
FANOUT0/GPIO52
AH16
FANOUT1/GPIO53
AM15
FANOUT2/GPIO54
AJ16
FANIN0/GPIO56
AK15
FANIN1/GPIO57
AN16
FANIN2/GPIO58
AL16
TEMPIN0/GPIO171
K6
TEMPIN1/GPIO172
K5
TEMPIN2/GPIO173
K3
TEMPIN3/TALERT#/GPIO174
M6 NC1
AG16
NC2
AH10
NC3
A28
NC4
G27
NC5
L4
VIN0/GPIO175
N2
VIN1/GPIO176
M3
VIN2/SDATI_1/GPIO177
L2
VIN3/SDATO_1/GPIO178
N4
VIN4/SLOAD_1/GPIO179
P1
VIN5/SCLK_1/GPIO180
P3
VIN6/GBE_STAT3/GPIO181
M1
VIN7/GBE_LED3/GPIO182
M5
SD_CLK/SCLK_2/GPIO73
AL14
SD_CMD/SLOAD_2/GPIO74
AN14
SD_CD/GPIO75
AJ12
SD_WP/GPIO76
AH12
SD_DATA0/SDATI_2/GPIO77
AK13
SD_DATA1/SDATO_2/GPIO78
AM13
SD_DATA2/GPIO79
AH15
SD_DATA3/GPIO80
AJ14
GBE_COL
AC4
GBE_CRS
AD3
GBE_MDCK
AD9
GBE_MDIO
W10
GBE_RXCLK
AB8
GBE_RXD3
AH7
GBE_RXD2
AF7
GBE_RXD1
AE7
GBE_RXD0
AD7
GBE_RXCTL/RXDV
AG8
GBE_RXERR
AD1
GBE_TXCLK
AB7
GBE_TXD3
AF9
GBE_TXD2
AG6
GBE_TXD1
AE8
GBE_TXD0
AD8
GBE_TXCTL/TXEN
AB9
GBE_PHY_PD
AC2
GBE_PHY_RST#
AA7
GBE_PHY_INTR
W9
SPI_DI/GPIO164
V6
SPI_DO/GPIO163
V5
SPI_CLK/GPIO162
V3
SPI_CS1#/GPIO165
T6
ROM_RST#/SPI_WP#/GPIO161
V1
VGA_RED
L30
VGA_GREEN
L32
VGA_BLUE
M29
VGA_DAC_RSET
K31
VGA_HSYNC/GPO68
M28
VGA_VSYNC/GPO69
N30
VGA_DDC_SDA/GPO70
M33
VGA_DDC_SCL/GPO71
N32
ML_VGA_HPD/GPIO229
C29
ML_VGA_L0P
T31
ML_VGA_L0N
T33
ML_VGA_L1P
T29
ML_VGA_L1N
T28
ML_VGA_L2P
R32
ML_VGA_L2N
R30
ML_VGA_L3P
P29
ML_VGA_L3N
P28
AUXCAL
U28
AUX_VGA_CH_P
V28
AUX_VGA_CH_N
V29
SATA_ACT#/GPIO67
AD22
RH24 10K_0402_5%
@
1 2
RH58 33_0402_5%
1 2

15. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Mini1-WLAN
Touch
OHCI CTL
DEV 20, Fn 5
EHCI CTL
DEV 22, Fn 2
EHCI CTL
DEV 19, Fn 2
EHCI CTL
DEV 18, Fn 2
<Disable CTL>
SM bus 0-->S0 PWR domain
SM bus 1-->S5 PWR domain
THERMTRIP:
Need level shift from +3VALW to +1.5V
Note: Ensure FCH internal pull-up resistor
to +3.3V S5 is disabled to prevent leakage
when APU is powered down.
<Disable CTL of M2>
<Support Wakeup>
xHCI CTL
DEV 16, Fn 1
Hudson-M2 Hudson-M3
xHCI CTL
DEV 16, Fn 0
Hudson-M2/M3
Hudson-M2/M3
Hudson-M2/M3
For PCIE device reset on FS1
(GFX,GLAN,WLAN,LVDS Travis)
For FCH internal debug use
xHCI CTL
DEV 16, Fn 0
xHCI CTL
DEV 16, Fn 1
Hudson-M3
33ohm termination
resistor at CODEC side
Change GPIO fellow Pumori
FCH GEVENT (S5 domain)
with isolation circuit to avoid leakage
FCH_PCIE_RST# IS FOR PCIE
DEVICES ON Hudson-M2/M3
Del MINI2_CLKREQ#
Del USB port 7
Del USB port 9
Confirm CR det or not.
PC_BEEP use.
Del SIMB output
Del MINI2_CLKREQ# PH.
USB 2.0 port(Left-2)
USBSS_CALRP=35ohm,<1000mil
USBSS_CALRN=35ohm,<1000mi
L
Del FCH_GPIO187 R57 R55
Del FCH_GPIO187
Check with BIOS
Del ODD_DA#
USB 3.0 port(Left-1)
USB 3.0 port(Left-2)
USB 2.0 port(Left-1)/ Charger
12/06 Del VGA_PWRGD
12/20 Del DDR3L_EN
Camera
10/4 Eric Del.
10/5 Eric modify for EMI requirement RH65 close to PCH
02/22 Add SUS_STAT#
10/18 Eric Add SATA_ODD/PCH_AUDIO control pin.
USB 2.0 / To IO Board. 10/29 change from 2 to 1.
11/20 Eric add test point from TH8 ~ TH26.
01/30 Eric del WWAM for USB 6.
WD_PWRGD
USB_RCOMP
USBSS_CALRP
USBSS_CALRN
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
H_THERMTRIP#
SLP_S3#
SLP_S5#
FCH_PWRGD
PBTN_OUT#
EC_SMI#
EC_SCI#
EC_GA20
EC_KBRST#
EC_RSMRST#
USB_OC0#
HDA_BITCLK
HDA_SDIN0
HDA_SDIN1
HDA_SDOUT
USB20_N5
USB20_P5
USB20_P8
USB20_N8
EC_PWM2
TEST0
TEST1
TEST2
FCH_SPKR
FCH_PCIE_WAKE#
H19
G19
CARD_DET_FCH
EC_LID_OUT#
SYS_RESET#
HDA_BITCLK
HDA_SDIN0
HDA_SDIN1
EC_RSMRST#
MINI1_CLKREQ#
LAN_CLKREQ#
EC_LID_OUT#
TEST0
TEST1
TEST2
LAN_CLKREQ#
USB_OC1#
MINI1_CLKREQ#
G22
G21
SYS_RESET#
HDA_SDIN2
HDA_SDIN3
HDA_SDIN2
HDA_SDIN3
SMIB
CARD_DET_FCH
SMIB
USB3_RX0_P
USB3_RX0_N
USB3_TX0_P
USB3_TX0_N
USB3_RX1_P
USB3_RX1_N
USB3_TX1_P
USB3_TX1_N
USB20_P10
USB20_N10
USB20_P11
USB20_N11
HDA_SDOUT
FCH_PCIE_WAKE#
H_THERMTRIP#
WD_PWRGD
LAN_CLKREQ#
USB_OC0#
USB20_N4
USB20_P4
HDA_BITCLK
CR_CLKREQ#
CR_CLKREQ#
SATA_ODD_PRSNT_R_N
SATA_ODD_PRSNT_R_N
FCH_SDATA1
FCH_SCLK1
USB20_P0
USB20_N0
WWAN_OFF#
WWAN_OFF#
HDA_RST#
HDA_RST#
HDA_SYNC
HDA_SYNC
USB_OC1#
H19
G19
G21
G22
FCH_SCLK0
FCH_SDATA0
SUS_STAT#
H_THERMTRIP#
EC_GA20
32
EC_RSMRST#
32
H_THERMTRIP#
8
SLP_S3#
32
SLP_S5#
32
FCH_PWRGD
32
PBTN_OUT#
32
FCH_SCLK0
11,12
FCH_SDATA0
11,12
EC_SMI#
32
EC_SCI#
32
USB_OC0#
26
USB20_N5 20
USB20_P5 20
USB20_P8 23
USB20_N8 23
EC_PWM2 16
EC_KBRST#
32
FCH_SPKR
28
FCH_PCIE_WAKE#
23,24
EC_LID_OUT#
32
LAN_CLKREQ#
24
USB_OC1#
27,31
MINI1_CLKREQ#
23
HDA_SDIN0
28
FCH_SCLK1
18,33
FCH_SDATA1
18,33
USB3_TX0_N 26
USB3_TX0_P 26
USB3_RX0_N 26
USB3_RX0_P 26
USB3_TX1_N 26
USB3_TX1_P 26
USB3_RX1_N 26
USB3_RX1_P 26
USB20_P10 27
USB20_N10 27
USB20_P11 26
USB20_N11 26
USB20_N4 20
USB20_P4 20
HDA_BITCLK_AUDIO
28
CR_CLKREQ#
25
USB20_P0 24
USB20_N0 24
HDA_SYNC_AUDIO
28
HDA_RST_AUDIO#
28
HDA_SDOUT_AUDIO
28
PCI_CLK1
13,16
SUS_STAT#
36
+FCH_VDD_11_SSUSB_S
+3VS
+3VALW
+3VALW
+3VALW
+3VS
+3VALW
+3VS
+3VS +3VALW
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
C
15 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
C
15 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
C
15 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
TH10
TH17
TH22
RP17
33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RH57 10K_0402_5%
1 2
TH11
TH23
RP21
2.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RH28
33_0402_5%
EMI@
1 2
RH66 10K_0402_5%
@
1 2
RF9
15P_0402_50V8J
RF@
1
2
TH24
RH129 2.2K_0402_5%
1 2
TH4
TH25
RH30 10K_0402_5%
@
1 2
RH37 10K_0402_5%
@
1 2
TH6
RP20
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RH39 10K_0402_5%
@
1 2
RH36 2.2K_0402_5%
@
1 2
TH12
RH33 2.2K_0402_5%
@
1 2
TH13
RH26 11.8K_0402_1%
1 2
RH128 2.2K_0402_5%
1 2
TH5
RH34 2.2K_0402_5%
@
1 2
RH29 100K_0402_5%
@
1 2
RH31 10K_0402_5%
@
1 2
RH55 1K_0402_1%
1 2
TH7
TH26
RH56 1K_0402_1%
1 2
TH27
RH27
10K_0402_5%
@
1
2
TH18
RH40 10K_0402_5%
@
1 2
TH19
TH9
RH38 10K_0402_5%
@
1 2
RH35 8.2K_0402_5%
@
1 2
RP18
100K_0804_8P4R_5%
1 8
2 7
3 6
4 5 TH8
TH14
C72
100P_0402_50V8J
ESD@
1
2
TH20
RP19
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
TH15
RH32 2.2K_0402_5%
@
1 2
TH21
RH41 10K_0402_5%
@
1 2
USB
OC
GPIO
ACPI
/
WAKE
UP
EVENTS
HD
AUDIO
USB
MISC
USB
1.1
USB
2.0
USB
3.0
EMBEDDED CTRL
HUDSON-2
UH1D
BOLTON-M2_FCBGA656
SCL2/GPIO193
H19
SDA2/GPIO194
G19
SCL3_LV/GPIO195
G22
SDA3_LV/GPIO196
G21
EC_PWM0/EC_TIMER0/GPIO197
E22
EC_PWM1/EC_TIMER1/GPIO198
H22
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
J22
EC_PWM3/EC_TIMER3/GPIO200
H21
KSI_0/GPIO201
K21
KSI_1/GPIO202
K22
KSI_2/GPIO203
F22
KSI_3/GPIO204
F24
KSI_4/GPIO205
E24
KSI_5/GPIO206
B23
KSI_6/GPIO207
C24
KSI_7/GPIO208
F18
PS2_DAT/SDA4/GPIO187
K19
PS2_CLK/CEC/SCL4/GPIO188
J19
SPI_CS2#/GBE_STAT2/GPIO166
J21
PS2KB_DAT/GPIO189
D21
PS2KB_CLK/GPIO190
C20
PS2M_DAT/GPIO191
D23
PS2M_CLK/GPIO192
C22
KSO_0/GPIO209
F21
KSO_1/GPIO210
E20
KSO_2/GPIO211
F20
KSO_3/GPIO212
A22
KSO_4/GPIO213
E18
KSO_5/GPIO214
A20
KSO_6/GPIO215
J18
KSO_7/GPIO216
H18
KSO_8/GPIO217
G18
KSO_9/GPIO218
B21
KSO_10/GPIO219
K18
KSO_11/GPIO220
D19
KSO_12/GPIO221
A18
KSO_13/GPIO222
C18
KSO_14/GPIO223
B19
KSO_15/GPIO224
B17
KSO_16/GPIO225
A24
KSO_17/GPIO226
D17
AZ_BITCLK
AB3
AZ_SDOUT
AB1
AZ_SDIN0/GPIO167
AA2
AZ_SDIN1/GPIO168
Y5
AZ_SDIN2/GPIO169
Y3
AZ_SDIN3/GPIO170
Y1
AZ_SYNC
AD6
AZ_RST#
AE4
BLINK/USB_OC7#/GEVENT18#
M7
USB_OC6#/IR_TX1/GEVENT6#
R8
USB_OC5#/IR_TX0/GEVENT17#
T1
USB_OC4#/IR_RX0/GEVENT16#
P6
USB_OC3#/AC_PRES/TDO/GEVENT15#
F5
USB_OC2#/TCK/GEVENT14#
P5
USB_OC1#/TDI/GEVENT13#
J7
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
T8
CLK_REQ4#/SATA_IS0#/GPIO64
AG24
CLK_REQ3#/SATA_IS1#/GPIO63
AE24
SMARTVOLT1/SATA_IS2#/GPIO50
AE26
CLK_REQ0#/SATA_IS3#/GPIO60
AF22
SATA_IS4#/FANOUT3/GPIO55
AH17
SATA_IS5#/FANIN3/GPIO59
AG18
SPKR/GPIO66
AF24
SCL0/GPIO43
AD26
SDA0/GPIO47
AD25
SCL1/GPIO227
T7
SDA1/GPIO228
R7
CLK_REQ2#/FANIN4/GPIO62
AG25
CLK_REQ1#/FANOUT4/GPIO61
AG22
IR_LED#/LLB#/GPIO184
J2
SMARTVOLT2/SHUTDOWN#/GPIO51
AG26
DDR3_RST#/GEVENT7#/VGA_PD
V8
GBE_LED0/GPIO183
W8
SPI_HOLD#/GBE_LED1/GEVENT9#
Y6
GBE_LED2/GEVENT10#
V10
GBE_STAT0/GEVENT11#
AA8
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
AF25
RSMRST#
U2
TEST0
T9
TEST1/TMS
T10
TEST2
V9
GA20IN/GEVENT0#
AE22
KBRST#/GEVENT1#
AG19
LPC_PME#/GEVENT3#
R9
LPC_SMI#/GEVENT23#
C26
LPC_PD#/GEVENT5#
T5
SYS_RESET#/GEVENT19#
U4
WAKE#/GEVENT8#
K1
IR_RX1/GEVENT20#
V7
THRMTRIP#/SMBALERT#/GEVENT2#
R10
WD_PWRGD
AF19
PCIE_RST2#/PCI_PME#/GEVENT4#
AB6
RI#/GEVENT22#
R2
SPI_CS3#/GBE_STAT1/GEVENT21#
W7
SLP_S3#
T3
SLP_S5#
W2
PWR_BTN#
J4
PWR_GOOD
N7
USBCLK/14M_25M_48M_OSC
G8
USB_RCOMP
B9
USB_FSD1P/GPIO186
H1
USB_FSD1N
H3
USB_FSD0P/GPIO185
H6
USB_FSD0N
H5
USB_HSD13P
H10
USB_HSD13N
G10
USB_HSD12P
K10
USB_HSD12N
J12
USB_HSD11P
G12
USB_HSD11N
F12
USB_HSD10P
K12
USB_HSD10N
K13
USB_HSD9P
B11
USB_HSD9N
D11
USB_HSD8P
E10
USB_HSD8N
F10
USB_HSD7P
C10
USB_HSD7N
A10
USB_HSD6P
H9
USB_HSD6N
G9
USB_HSD5P
A8
USB_HSD5N
C8
USB_HSD4P
F8
USB_HSD4N
E8
USB_HSD3P
C6
USB_HSD3N
A6
USB_HSD2P
C5
USB_HSD2N
A5
USB_HSD1P
C1
USB_HSD1N
C3
USB_HSD0P
E1
USB_HSD0N
E3
USBSS_CALRP
C16
USBSS_CALRN
A16
USB_SS_TX3P
A14
USB_SS_TX3N
C14
USB_SS_RX3P
C12
USB_SS_RX3N
A12
USB_SS_TX2P
D15
USB_SS_TX2N
B15
USB_SS_RX2P
E14
USB_SS_RX2N
F14
USB_SS_TX1P
F15
USB_SS_TX1N
G15
USB_SS_RX1P
H13
USB_SS_RX1N
G13
USB_SS_TX0P
J16
USB_SS_TX0N
H16
USB_SS_RX0P
J15
USB_SS_RX0N
K15
TH16

16. WWW.AliSaler.Com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CLKGEN
ENABLED
S5 PLUS
MODE
ENABLED
DEFAULT
CLKGEN
DISABLE
PULL
LOW
PULL
HIGH
DEFAULT
RTC_CLK
LPC_CLK1
LPC ROM
SPI ROM
EC_PWM2
EC
ENABLED
EC
DISABLED
DEFAULT
PCI_CLK1
ALLOW
PCIE GEN2
PCI_CLK3
NON_FUSION
CLOCK MODE
DEFAULT
IGNORE
DEBUG
STRAP
USE
DEBUG
STRAPS
PCI_CLK4 LPC_CLK0
DEFAULT
FORCE
PCIE GEN1
FUSION
CLOCK
MODE
DEFAULT
S5 PLUS
MODE
DISABLED
STRAP PINS
PCI_AD25 PCI_AD24
USE EEPROM
PCIE STRAPS
USE DEFAULT
PCIE STRAPS
DEFAULT
DEFAULT
USE FC
PLL
DISABLE
ILA
AUTORUN
USE PCI
PLL
DEFAULT
BYPASS
FC PLL
PULL
HIGH
DEFAULT
BYPASS
PCI PLL
PCI_AD27 PCI_AD26
PULL
LOW
DEFAULT
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PCI_AD23
DEBUG STRAPS
ENABLE
ILA
AUTORUN
DISABLE PCI
MEM BOOT
ENABLE PCI
MEM BOOT
Remove VGA_PD
Remove VGA_PD
Change to SPI
DEFAULT
LPC_CLK1
RTC_CLK
PCI_CLK1
13,15
PCI_CLK3
13
PCI_CLK4
13
LPC_CLK0_EC
13,32
LPC_CLK1
13
EC_PWM2
15
RTC_CLK
13,32
PCI_AD27
13
PCI_AD26
13
PCI_AD25
13
PCI_AD24
13
PCI_AD23
13
+3VALW
+3VALW
+3VALW
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
16 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
16 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019NK A
SCHEMATIC, MB A9851
Custom
16 47
Monday, October 21, 2013
2012/11/07 2012/11/07
Compal Electronics, Inc.
RH51
2.2K_0402_5%
@
1
2
RH50
2.2K_0402_5%
@
1
2
RH46
10K_0402_5%
@
1
2
RH44
10K_0402_5%
@
1
2
RH42
10K_0402_5%
@
1
2
RP23
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RH45
10K_0402_5%
@
1
2
RP24
10K_0804_8P4R_5%
1
8
2
7
3
6
4
5
RH43
10K_0402_5%
@
1
2
RH48
2.2K_0402_5%
1
2
RH52
2.2K_0402_5%
@
1
2
RH47
10K_0402_5%
@
1
2
RH49
2.2K_0402_5%
@
1
2
RH54
2.2K_0402_5%
@
1
2
RH53
2.2K_0402_5%
@
1
2