FPGA to ASIC, ASIC to ASIC,<br />DSP to ASIC<br />CONVERSIONs<br />
Reduce Production Cost <br />Reduce your FPGA chip cost by more than 50% from your product, with no effort from your side" <br />KaiSemi provides you a Guaranteed ASIC drop-in replacement with No NREpayment, as Fast as 6-14 weeks.<br />KaiSemi is the only vendor who owns in-house semi-automated tools converting FPGA-to-ASIC directly from netlist, any size of FPGA.<br />KaiSemi will convert your FPGA, covering the whole ASIC workflow from customer decision until 2nd source product shipping, seamless to customer work.<br /> relies on a strong firm financial footing of Kai-Tek Group and a massive proven conversion experience.<br />
About KaiSemi<br /><ul><li>KaiSemi is a fabless semiconductor vendor specialized in product conversions of:</li></ul>FPGA-to-ASIC <br />ASIC-to-ASIC<br />DSP-to-ASIC<br />MultiChip-to-ASIC<br />www.kaisemi.com<br /><ul><li>KaiSemi is a part of the Kai-Tek Group of companies, a well established representative, distributor and a R&D service provider in the semiconductor market with a strong financial backing. </li></ul>www.kai-tek.com<br /><ul><li>The Kai-Tek Group is a member of the ATeG “Advanced Technology Group”, a provider of very strong technical offerings to its customers, worldwide, from design-in to production service.</li></ul>www.ateg-ww.com<br />
Specialists of Cost-reduction chips<br /><ul><li>Cost-reduction by FPGA-to-ASIC replacement.
Significant lower radiated EMI.</li></li></ul><li>KaiSemi exclusive Workflow<br />Traditional flow<br />KaiSemi flow<br />FPGARTL<br />FPGA Netlist<br />RTL fit to ASIC<br /><ul><li>KaiSemi is focused on converting, FPGA or ASIC, directly from the FPGA’s Post-P&R-Compiled Netlist.
Kai-Semi has an exclusive set of tools and processes to convert directly from FPGA netlist to ASIC final chip.
Converting from FPGA netlist stage allows us to give quality guarantee with no functional risk and very fast cycle time.</li></ul>Functional Simulation<br />Full ASIC Synthesis<br />KaiSemi in-house tools<br />Timing + Functional Simulation<br />DFT insertions<br />ASIC Netlist<br />Layout P&R<br />Timing + Functional Simulation<br />FAB hand-off<br />
KaiSemi business model<br />Functionality Guaranteed “No good, no pay”.<br />Zero NRE Payment“Minimum Risk”.<br />Fastest cycle-time “as fast as 6-14 weeks”.<br />Minimum customer intervention “Fire and forget”.<br />Any size FPGA“Minimum complexity limitation”.<br />1<br />2<br />5<br />Customer<br />3<br />4<br />
KaiSemi exclusive benefits<br />Functionality Guaranteed (No Good No Pay!), because:<br />No RTL touch ! Functional source code is untouched. <br />Using ONLY the Netlist outcome of the proven working FPGA. <br />Proven in-house semi-automated developed conversion tool with experience limits human errors<br />No NRE Payment (No Risk), because: <br />Our business model is targeted to ease on the customer. Based on minimum quantity ordering.<br />Fastest cycle-time, because: <br />Shortening ASIC flow cycle by using automated process and by starting, higher, from netlist stage<br />Limiting the need for customers cycles of RTL flow, synthesis, verifications and back-annotations.<br />Having well established coherent work flow with FABs.<br />Minimum customer intervention (Fire & Forget), because:<br /> Customer is required to provide 2 main receivables: <br />The FPGA netlist <br />A verification test vectors. <br />From that point on we proceed in posted mode, performing the whole ASIC process until providing a final working chip. <br />Any size FPGA, because:<br />KaiSemi conversion tool deals with any size and any type of FPGA with No limit on netlist size.<br />
KaiSemi Team<br /><ul><li>The KaiSemi team is built from experts, having 12 to 19 years of experience in the relevant activity of FPGAs & ASIC conversions including the full flow required for ASIC productization.
The team members have an experience of over 500 successful FPGAs & ASIC conversions. </li></li></ul><li>KaiSemi Additional Expertise<br />Delivering a fully compatible pin-to-pin packaged device based on the existing FPGA. <br />Capability to fit compatible IPs, PLLs & I/Os of FPGAs to ASICs.<br />Capability to provide various types of special cells like PLLs, DLLs, ADPLLs, Multipliers, Power-On-Reset and broad range of IPs.<br />KaiSemi has a well established infrastructure with FABs and Processes in a wide range of technology processes (0.5u, 0.35u, 0.18u, 0.13u, 0.09u). FAB-Process is carefully defined based on the required frequency and other design constraints, targeting to lower the cost.<br />Supporting Commercial, Industrial and Military grades.<br />Supporting Mixed signal and custom Analog cells solutions.<br />Providing Custom low power design for specific modules.<br />Supporting High performance libraries and clocking, convering both high speed and low power requirements.<br />
ASIC to ASIC<br />KaiSemi provides EOL (End Of Life) replacements for ASICs taking care of the entire production process, without customer involvement.<br />We guarantee a fully compatible drop-in replacement for use as a reliablereplacement part second source.<br />We do not charge NRE, we only get paid for the working parts, so no risk is involved for the customer.<br />KaiSemi has also the capability to provide ASIC to ASIC conversion for improving performance and/or using improved replaceable ASIC libraries and IPs.<br />
Multi Chip Merge<br />Kaisemi provides advanced multi chip solutions, that convert several FPGA's into one ASIC, thus reducing the total system cost and power consumption immensely.<br />We could also package your EOL (End Of Life) ASIC or converted FPGA along with its external memories etc. thus enabling further cost reduction and a reduced PCB footprint.<br />We have the ability to assemble Multiple dies in a single package.<br />In addition, we have the ability to convert Multiple FPGAs into a single die.<br />
DSP to ASIC<br />Performance comparing example:<br />JPEG Encoder Case Study<br />Link:<br />www.gmvhdl.com/fpga_for_dsp.html<br />KaiSemi offers a migration flow from DSP designs to a dedicated ASIC.<br />This allows our customers to boost DSP performance up to x100 from the existing top of the line expensive DSP chips.<br />KaiSemi offers a development environment flow and service to import DSP designs into ASIC while using evaluation verification on an FPGA.<br />DSP design houses can now boost performance per cost in their applications, by moving from a traditional DSP chip to a dedicated ASIC, using KaiSemi's offering, with minimum development effort on their side.<br />* Estimated performance based ASIC frequency speedup<br />Performance per Cost comparing <br />www.latticesemi.com/lit/docs/generalinfo/ecp_whitepaper.pdf<br />Link:<br />* Estimated performance/cost based ASIC area parallelism<br />