Digital electronics about gate level minimization

1. Gate-Level Minimization
Md. Zubair Alam Emon
https://youtu.be/Z3Ha0jicl3k

2. Karnaugh Map
• The simplified expressions produced by the map are
always in one of the two standard form: SOP or POS
• Only one bit changes in value from one adjacent
column to the next.
• Any two adjacent squares in the map differ by only
one variable.
• There are cases where two squares in the map are
considered to be adjacent even though they do not
touch each other.
• Number of small squares = 2n ;where n is the number
of variables in a function.

3. 2- Variable Map
• 22 = 4 small squares
• Say, F(x,y)=x’y+xy’+xy
y
x
F(x,y)=x+y

4. Example
• Simplify the Boolean expression using Karnaugh Map (K-Map).
F(x,y)=x’y’+xy+x’y
Ans: F(x,y)=x’+y

5. 3- Variable Map
• 23 = 8 small squares
• Say, F(x,y,z)=xy’z + xyz
F(x,y)=z
1 1

6. Example
• Simplify the Boolean expression
F(x,y,z)=∑(0,2,4,5,6)
x yz 00 01 11 10
0
1
Ans: xy’+z’
1 1
1 1 1
z’
xy’

7. 4-Variable K-Map
• Simplify the Boolean expression
F (w, x, y, z) =∑ (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
Ans:F=y’+w’z’+xz’
https://youtu.be/Y0mUJ1LLzbY

8. Example
• Simplify the Boolean expression
F = A’B’C’ + B’CD’ +
A’BCD’ + AB’C’
Ans:F=B’D’ +
B’C’ + A’CD’

9. K-Map
• 2-variable map
• 3-variable map
F (x,y,z) = Σ(2,3,4,5)
F (x,y,z) = Σ(3,4,6,7)
F (x,y,z) = Σ(0,2,4,5,6)
F = A’C +A’B + AB’C + BC
F (x,y,z) = Σ(1,2,3,5,7)
• 4-variable map
F (w,x,y,z) = Σ(0,1,2,4,5,6,8,9,12,13,14)
F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’

10. Prime Implicants
• Prime implicant is a product term obtained by combining the
maximum possible number of adjacent squares in the map.
• If a minterm in a square is covered by only one prime implicant, that
prime implicant is said to be essential.
• Example:
• F(A,B,C,D) = Σ(0,2,3,5,7,8,9,10,11,13,15)

11. F(A,B,C,D) = Σ(0,2,3,5,7,8,9,10,11,13,15)

12. K-Map
• 5-variable map
F(A,B,C,D,E) = Σ(0,2,4,6,9,13,21,23,25,29,31)

13. POS Simplification
• F(A,B,C,D) = Σ(0,1,2,5,8,9,10)
F’(A,B,C,D) = Σ(3,4,6,7,11,12,13,14,15)
F’(A,B,C,D) = Σ(3,4,6,7,11,12,13,14,15)
• F(x,y,z) = Σ(1,3,4,6)
= π(0,2,5,7)
• The 1’s of the function represent the minterms, and
the 0’s represent the maxterms.

14. Example
F’ = AB + CD + BD’ So, F=(A’ + B’) (C’ + D’) (B’ + D)

15. Combinational Ckt Problems
1. Construct a logic ckt such that, one can control a light using 2
switches (sw1, sw2.). If any of the two switch is ON then the light
will be ON.
2. Construct a logic ckt such that, one can control a light using 2
switches (sw1, sw2.) located at two different rooms. Make sure that
one can turn ON/OFF the light from any room.

16. Don’t Care Condition
• Don’t care condition exists where the function is not specified for
certain combinations of the variables
• Example
F(w,x,y,z) = Σ(1,3,7,11,15)
and d(w,x,y,z) = Σ(0,2,5)
• Could be written as
F(w,x,y,z) = Σ m(1,3,7,11,15) + d(0,2,5)

17. Example

18. NAND Implementation
• Create inverter / AND / OR gate using NAND gates.
• NAND Implementation for SOP
F = AB + CD
F = xy’ + x’y + z
F = A(CD + B) + BC’
F = (AB’ + A’B)(C + D’)
• AND-OR-INVERT
F = (AB + CD + E)’
+ Z’

19. F=AB+CD with NAND

20. NOR Implementation
• Create inverter / AND / OR gate using NOR gates.
• NOR Implementation for POS
F = (A + B)(C + D)E
F = (AB’ + A’B)(C + D’)
• OR-AND-INVERT
F = [(A + B)(C + D)E]’

21. F=(A+B)(C+D)E with NOR

22. Exclusive-OR Function
• Exclusive-OR (XOR) is denoted by e.g.
It is equal to 1 if either x or y is 1 but not both.
• Particularly useful in arithmetic operations and error detection and
correction circuits.
• An n-variable XOR function is an odd function whose binary numerical
values have an odd number of 1’s.
• Complement of an odd function is an even function (i.e. has even
number of 1’s) e.g. XNOR

'
' xy
y
x
y
x 



23. Parity
• Circuit that generates the parity bit in the transmitter is called a parity
generator.
• Circuit that checks the parity in the receiver is called a parity checker.
• XOR functions are very useful in systems requiring error-detection
and correction codes.

24. Parity Generation / Checking
3-bit message Parity Bit
x y z P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
4 bit received Parity check
x y z P C
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Even parity generator truth table
z
y
x
P 

 Even
parity
checker
truth
table
P
z
y
x
C 




25. Parity Generator/Checker
• Parity generator can be implemented with the parity
checker circuit by grounding the input P
• Odd parity function can be implemented just by
changing the final XOR with an XNOR gate.
x
y
z
P
C
P
x
y
z
3-bit even parity generator
4-bit even parity checker

26. HDL
• HDL describes the hardware of digital systems.
• It describes hardware structures and behavior.
• It represents logic diagrams, Boolean functions and
other more complex digital circuits.
• To simulate a digital system, the design is first
described in HDL and then verified by simulating the
design and checking it with a test bench.
• Logic synthesis is the process of deriving a netlist from
the model of a digital system written in HDL.
• There are two standard HDLs:
• VHDL and Verilog HDL.

27. Module Representation
• Verilog uses about 100 keywords predefined, lowercase, identifiers
that defines the language constructs. e.g.
• module, endmodule, input, output, wire, and, or, not etc.
• Comments start with two slashes (//)
• Blank spaces are ignored
• Names are case sensitive
• Each statement is terminated with a ;
• Output is always listed first, followed by inputs

28. Verilog Example
●
g1
g2
g3
A
B
C
x
y
e
// description of simple circuit
module smpl_circuit( x, y, A, B, C );
input A, B, C;
output x, y;
wire e;
and g1( e, A, B );
not g2( y, C );
or g3( x, e, y );
endmodule

29. Gate Delays
• Simulator defaults to certain time unit, usually 1 ns but could be
changed with
`timescale 1ns / 100ps
• Delay is specified in terms of time units and the symbol #
and #(10) gate1(e, A, B)

30. Test Bench Example
●
g1
g2
g3
A
B
C
x
y
e
// description of simple circuit
module smpl_circuit( x, y, A, B, C );
input A, B, C;
output x, y;
wire e;
and #(30) g1( e, A, B );
not #(20) g2( y, C );
or #(10) g3( x, e, y );
endmodule
// description of test bench
module smpl_ckt_tb;
reg A, B, C;
wire x, y;
smpl_circuit inst1(x,y,A,B,C);
initial
begin
A=1’b0; B=1’b0; C=1’b0;
#100 A=1’b1; B=1’b1; C=1’b1;
#100 $finish;
end
endmodule
An HDL description that provides the stimulus to a design is called a test bench

31. Test Bench Output
y
x

32. Filename must have the
“.v” extension

33. Output
• See that the simulation ends at 80ns.

34. Boolean Expression in Verilog
●
g1
g2
g3
A
B
C
x
y
e
// Circuit with Boolean expression
module smpl_circuit( x, y, A, B, C );
input A, B, C;
output x, y;
assign y = ~C;
assign x = (A & B) | (~C);
endmodule
Write a Verilog for the following Boolean expression :
E = A + BC + B’D
F = B’C + BC’D’
// Circuit with Boolean expression
module Circuit_Boolean (E, F, A, B, C, D);
output E, F;
input A, B, C, D;
assign E = A | (B & C) | ((~B) & D);
assign F = ((~B) & C) | (B & (~C) & (~D));
endmodule

35. User Defined Primitives (UDP)
// User defined primitive (UDP)
primitive crctp (x, A, B, C);
output x;
input A, B, C;
// truth table for x(A,B,C) = Σ(0,2,4,6,7)
table
// A B C : x
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
// Instantiate primitive
module test_crctp;
reg x, y, z;
wire w;
crctp (w, x, y, z);
endprimitive
The system recognizes the variables
by the order that they are listed in the
input declaration.
User-defined primitive can be employed
in construction of other digital circuits
just as the system primitives are used.

36. Example
// Verilog model: Circuit instantiation of Circuit_UDP_02467
module Circuit_with_UDP_02467 (e, f, a, b, c, d);
output e, f;
input a, b, c, d
UDP_02467 (e, a, b, c);
and (f, e, d); // Option gate instance name omitted
endmodule

37. UDP (cont.)
• Declared with keyword primitive followed by a name and port list.
• Only one output – must be listed first in the port list and declared with output
keyword.
• Any number of inputs allowed – order in the input must be same as the values in
the table that follows.
• Truth table is enclosed within table and endtable.
• Values of inputs end with a colon (:) Output is the last entry in a row followed by
a semicolon (;)
• UDP ends with the keyword endprimitive.
• and, or, not etc. gates are referred to as system primitive

38. HW
• 3.1(c), 3.3(b), 3.5(a), 3.6(a), 3.7(d), 3.8(c), 3.9(b), 3.12(b), 3.13(a,c),
3.14, 3.15(b), 3.16(a), 3.17, 3.18, 3.19(a), 3.23, 3.24, 3.30, 3.31(a,e),
3.32(b,f), 3.33~3.36, 3.37