1. GYAN GANGA INSTITUTE OF TECHNOLOGY AND MANAGEMENT,
BHOPAL -462021
An IS0 9001-2008 Certified Institution
(Approved by AICTE & Affiliated to RGPV)
Village-Khajuri Khurd, P.O. Anand Nagar, Raisen Road,
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
20 Questions
Subject: CMOS CKTS Subject Code: EC-802
1. Draw the analog design octagon and explain how the trade of between various
parameters is obtained?
2. Discuss the single stage common source (CS) amplifier and also derive the equation
for its voltage gain.
3. Draw the circuit diagram and small signal equivalent circuit of a source degenerated
common source (CS) amplifier. Obtain the equation for transconductance (G) for
this circuit. Give the significance of this equation.
4. Numerical on the voltage gain for the given circuit.
5. Explain how the Gilbert cell can be used in differential amplifier .Also draw neat
circuit diagram of Gilbert cell.
6. Numerical on circuit uses a resistor rather than a current source to define a tail
current of 1mA.
I) what is the required input CM for which Rss sustains 0.5 V?
II) Calculate RD for a differential gain of 5.
III) What happens at the output if the CM level is 50 mV higher than the value
calculated in (I).
7. Discuss how the feedback circuits in amplifier help in:
i) Gain desensitization ii) Impedance modification
8. Draw a basic switched-capacitor amplifier and explain its operation. How is it
different from conventional amplifier?
9. Explain why a single common source (CS) stage does not oscillate if it is placed in
unity gain loop.

2. 10. Draw a differential implementation of ring oscillator. Explain how it works. Also
calculate the maximum voltage swing of each stage.
11. Draw the basic block diagram of Phase Lock Loop (PLL) and explain its operation
with neat waveforms.
12. Explain how a master slave D flip flop can be used as phase frequency detector. What
are its limitations?
13. Draw and explain the architecture of 4X6 MOS NAND ROM with suitable example
and compare it with MOS NOR ROM with respect to:
i) Layout area ii) Voltage swing iii) propagation delay
14. Discuss the operation of one transistor dynamic cell. Explain the read, write and
refresh operations with the help of path diagram and associated waveforms.
15 Discuss the architecture of a 3-input, 2-output PLA. Implement the following function
through the above PLA devices:
F0= x0.x1 +x2 F1 = x0x1x2+ x2 +x0x1
16 Discuss in detail Content Addressable Memory (CAM) and its applications.
17 Draw the transistor level circuit diagram of a positive edge triggered D flip flop with
synchronous set and reset control signals and explain its operation.
18 A parity generator is to be implemented for data path subsystem. Draw its
conventional implementation using XOR gate. Also explain its CMOS dynamic version.
19. List various types of adders used in data path subsystems. Explain with block
diagram carry select adder. How does it increase the speed of operation?
20. List various binary multiplication algorithms. Discuss Wallace- tree multiplication
algorithm with appropriate example.