This lecture discusses different types of basic flip-flops including SR, D, JK, and T flip-flops. It begins by distinguishing between latches and flip-flops, with latches using level-sensitive control and flip-flops using edge-triggered clock signals. The lecture then covers the operation of SR, D, and JK flip-flops using NAND gates, including their truth tables. It also introduces the T flip-flop as a variation of the JK flip-flop with its single input T causing the output to toggle states. The concept of a "race around condition" is explained for the JK flip-flop where feedback from the output to the input can cause the output

1. Lecture-2
SWITCHING THEORY AND LOGIC
DESIGN
UNIT-iv
V. KUMARA SWAMY,
BE(ECE), MTECH(DSCE), [Ph.D], MIEEE
ASSOC.PROF & ASSOC.HoD
Dept of ECE
Basic flip-flops

2. Contents Covered in the last class
Classification of sequential circuits (Synchronous,
Asynchronous Pulse mode, and Level mode with
examples).
Latches
• S’R’ Latch.
• SR Latch with Clock Signal.
• Gated D-Latch.

3. Contents to be Covered Today
Basic flip-flops.
• SR Flip-Flop
• D- Flip-Flop
• JK-Flip-Flop
• T-Flip-Flop

4. Latches A latch is a memory element whose
excitation signals control the state of the device. A
latch has two stages set and reset. Set stage sets the
output to 1. Reset stage set the output to 0.
Flip-flops A flip-flop is a memory device that has
clock signals control the state of the device.

5. Q
Q’
INPUTS
NORMAL OUTPUT
INVERTED OUTPUT
The basic 1-bit digital memory circuit is known as a flip-flop. It
can have two states either the 1 state or the 0 state.
It is also known as a bistable multivibrator. Flip-flops can be
obtained by using NAND or NOR gates.

6. n+1 n+1
Qn Qn
Qn Qn
0 1
0
1
1
0
0
1
1
0
1
0

7. n+1 n+1
Qn Qn
Qn Qn
0 1
1
0
0
1
1
0
0
1
0
1
1 0

8. n+1 n+1
Qn Qn
Qn Qn
0 1
1
0
Prohibited
1
1
1
1
0 1
1
1
0
0

9. 1
1
1
1
1
1
1
1

10. Truth Table
D-Flip Flop using NAND Gates
Truth
Table:
1
0
0
1
1
0
1
1
0
1

11. Truth Table
D-Flip Flop using NAND Gates
Truth
Table:
0
1
1
0
0
1
0
1
1
1

12. • Make S and R complements of each other
–Eliminates 1s catching problem
–Value of D just propagated to output of the flip-
flop with PD.
–D FF is most commonly used in registers, and
memory devices.

13. JK Flip Flop using NAND gates
0 1
1
0
1
1
0
1
0
0
1
0
1
1
1
0
1

14. Clk J K Qn+1
Qn+1X X Qn Qn
0
0
Qn Qn
0
0
1
0
1 0
0
1
0
1
1
1
1
1
0
0
1
0
1

15. 1 1
1
1
0
0
0
1
1
0
1
1
1
1
Qn Qn

16. With a slight modification of a J-K flip-flop, we can construct a new
flip flop called the T-FLIPFLOP . If the two inputs J and K of a J-K
flip-flop are tied together it is referred to as a T-flip-flop. Hence a
T flip-flop has only one input T and two outputs Q and Q’. The
name T flip-flop actually indicates the fact that the flip-flop has the
ability to TOGGLE. It has actually only two states TOGGLE
STATE and MEMORY STATE.

17. T FLIP FLOP
TRUTH TABLE

18. What is meant by race around condition?
•In JK Flip-Flop the output is feedback to the input,
therefore change in the output results change in the input.
•Due to this in the positive half of the clock pulse if J and
K are both high then output toggles continuously as
shown at points a,b,c,d and e in the below figure.
•This condition is known as “Race Around Condition”, it
must be avoided