vlsi pdf imprtant

1. UNIT V
MEMORY AND SUBSYSTEM DESIGN:
Latches and Registers
Clocking strategies (Single Phase)
Memory cells (SRAM & DRAM)
Adders, Shifter, Multipliers and ALUs
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11. Clock Strategy
One of the most important decisions made at the start
of a design is the selection of a clocking strategy.
It effects:
How many transistors are used per storage element.
How many clock signals need to be routed throughout
the chip.
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12. System Timing
Two possible strategies to implement clocked systems:
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13. Latches are a more economical implementation strategy but
are transparent on half of the clock cycle, and cannot be used
in feedback systems.
Also, the following constraint must be met for latches:
T d < T c /2 - T q - T s
where T d is the worst case propagation delay, T c is the
clock cycle time, T q is the Clock-to-Q time of latch A and
T sis the setup time for latch B.
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14. Clock Race Conditions
Occurs when the data input to the register does not obey
the setup and hold-time constraints.
Delays in the clock line to Reg B (hold-time violation).
New data stored instead of previous data:
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15. Single Phase Global Clock Generation
Transistors in the inverter and pass gate should be similar in size.
Keep them small and use buffers to drive the load.
Note: The routing load MUST also be balanced on each of the clk
lines
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