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REALIZATION OF FLIP-FLOPS USING
NAND GATES
Flip-Flop is popularly known as the basic digital memory circuit. It has
two states as logic 1(High) and logic 0(low) states.
A flip flop is a sequential circuit which consists of a single binary state
of information or data.
The digital circuit is a flip flop which has two outputs and are of
opposite states. It is also known as a Bistable Multivibrator.
JK Flip Flop :
The JK flip flop diagram below represents the basic structure
which consists of Clock (CLK), Clear (CLR), and Preset (PR).
Operations in JK Flip-Flop –
Case-1:
PR = CLR = 0
This condition is in its invalid state.
Case-2:
PR = 0 and CLR = 1
The PR is activated which means the output in the Q is set to 1. Therefore, the flip flop is in the set
state.
Case-3:
PR = 1 and CLR = 0
The CLR is activated which means the output in the Q’ is set to 1. Therefore, the flip flop is in the reset
state.
Case-4:
PR = CLR = 1
In this condition, the flip flop works in its normal way whereas the PR and CLR gets deactivated.
JK Flip-Flop with the representation of Preset and
Clear –
Race Around Condition in JK
Flip-Flop –
When the J and K both are set
to 1, the input remains high
for a longer duration of time,
then the output keeps on
toggling. Toggle means
switching in the output
instantly i.e. Q = 0, Q’ = 1 will
immediately change to Q = 1
and Q’ = 0 and this
continuation keeps on
changing. This change in
output leads to Race Around
Condition.
jBCBPIa.pptx
jBCBPIa.pptx
jBCBPIa.pptx
jBCBPIa.pptx
jBCBPIa.pptx
jBCBPIa.pptx

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jBCBPIa.pptx

  • 1. REALIZATION OF FLIP-FLOPS USING NAND GATES
  • 2.
  • 3.
  • 4. Flip-Flop is popularly known as the basic digital memory circuit. It has two states as logic 1(High) and logic 0(low) states. A flip flop is a sequential circuit which consists of a single binary state of information or data. The digital circuit is a flip flop which has two outputs and are of opposite states. It is also known as a Bistable Multivibrator.
  • 5.
  • 6.
  • 7.
  • 8.
  • 9.
  • 10.
  • 11.
  • 12.
  • 13. JK Flip Flop : The JK flip flop diagram below represents the basic structure which consists of Clock (CLK), Clear (CLR), and Preset (PR).
  • 14. Operations in JK Flip-Flop – Case-1: PR = CLR = 0 This condition is in its invalid state. Case-2: PR = 0 and CLR = 1 The PR is activated which means the output in the Q is set to 1. Therefore, the flip flop is in the set state. Case-3: PR = 1 and CLR = 0 The CLR is activated which means the output in the Q’ is set to 1. Therefore, the flip flop is in the reset state. Case-4: PR = CLR = 1 In this condition, the flip flop works in its normal way whereas the PR and CLR gets deactivated.
  • 15. JK Flip-Flop with the representation of Preset and Clear – Race Around Condition in JK Flip-Flop – When the J and K both are set to 1, the input remains high for a longer duration of time, then the output keeps on toggling. Toggle means switching in the output instantly i.e. Q = 0, Q’ = 1 will immediately change to Q = 1 and Q’ = 0 and this continuation keeps on changing. This change in output leads to Race Around Condition.