1. Kalyani Anil Gonde
2825 Ellendale Pl, Apt C
Los Angeles, CA 90007 (323)403-9869
https://www.linkedin.com/in/kalyanigonde____________________________________________________________gonde@usc.edu_______
Objective:
Seeking Full-time job opportunities in the field of ASIC Design/ VLSI/ Physical Design starting from December 2016
Education:
Jan ’15 – Dec ‘16 Masters of Electrical Engineering (MSEE) at University of Southern California (USC), LA, CA
July ‘10 – June ‘14 Bachelor of Technology (B.Tech, Electronics and Telecommunication) at
Shri Guru Gobind Singhji Institute of Engineering and Technology, (SGGSIE&T), Nanded, India
Relevant Coursework:
Digital System Design (EE560) Computer Systems Organization (EE-457) MOS VLSI Circuit Design (EE-477)
VLSI System Design (EE-577A&B) Diagnosis and Design of Reliable Digital
Computers (EE-658)
Integrated Memory Devices and Technology (EE-
599)
Technical skills:
Programming Languages: Verilog, Perl,
VHDL, TCL, MATLAB, C++
Packages/Tools: Cadence Tools(Virtuoso,Spectre), Xilinx ISE Design Suite, HSpice, ModelSim,
NCSim Cadence Conformal, Primetime, Cadence SoC Encounter, Synopsys Design Compiler
Academic Projects:
Feb ‘16 – May ‘16 Chip Multi Processor: Designed and implemented a 4 core processor (5 stage pipeline variable width processor) which sends
64-bit data packet through bi directional Ring Router to communicate the data where every processor acts as a sender and
receiver. Synthesized the RTL design to gate level netlist using Synopsys DC. Static Timing Analysis was performed using
PrimeTime. Performed Logic Equivalence Checking using Cadence Conformal, APR and CTS using Cadence SOC Encounter.
Language: Verilog CAD Tools: Cadence Encounter, Cadence Conformal, Synopsys Design Compiler, NCSim
Feb’16 – April ‘16 32-bit Floating-Point Multiplier (IEEE-754 Number Representation): Models a single precision floating-point multiplier.
Design treats the exponent and fraction parts of inputs/output as separate bit-fields that are operated on with binary arithmetic.
Synthesized the RTL design to gate level netlist using Synopsys DC.
Language: Verilog CAD Tools: Synopsys Design Compiler, NCSim
June’15 – Aug ‘15 Tomasulo Algorithm based CPU: Developed RTL coding in VHDL for a 32-bit Out‐of‐Order Processor with speculative
execution and branch prediction. Synthesized on Artix-7 FPGA and tested using different instruction streams and test benches.
Language: VHDL
June’15 – Aug ‘15 FIFO Design and CDC: Designed an interface between Producer and Consumer using FIFO, which delinks two components.
This system can be used to connect two different components in a system running at different clock frequencies.
Language: VHDL
June’15 – Aug ‘15 Fully Associative Cache using Content Addressable Memory (Divider with Cache):
Designed fully associative cache using CAM with BRAM and Least Recently Used (LRU) replacement policy.
Implemented LRU stack, Tag RAM and Data RAM
Language: Verilog
June’15 – Aug ‘15 AXI Protocol: Designed Multiprocessor system with 4 cores and 4 cache blocks interconnected using AXI protocol and uses
4x2 mesh to transfer data packets. Data packetizing, AXI Master, AXI Slave, Write transaction, read transaction were used in
this project.
Language: Verilog
Aug ‘15 – Dec ‘15 Implementation of a 1-Bit cell: Implemented a one-bit cell in Hspice using PTM 22nm CMOS Technology. Developed Perl
script to linearly sweep the width of the transistor, capacitance and print the results of corresponding values of Iavg, Pavg
generated to a text file.Coded in Matlab to plot 3D graphs of the results from the text file earlier generated.
Language: Perl, MATLAB CAD Tools: HSPICE
Aug ‘15 – Dec ‘15 Full Custom layout of a General Purpose 32-bit Pipelined System: Designing of 5 stage pipelined system in TSMC 180nm
technology to perform simple arithmetic operations, memory burst read and write operation (SRAM). To design the Perl code
for providing the control signals depending upon the instruction executed.
Language: Perl CAD Tools: Cadence Virtuoso
Aug ‘15 – Dec ‘15 Full Custom layout for SRAM: Designing of 1024 (1KB) bit SRAM in 180nm technology and check for multiple write and
read functionality. Design of decoder circuit sense amplifier and SRAM 1-bit cell, check for proper sizing to get desired output.
Feb ‘15 – May ‘15 Full Custom layout for 4-bit Up-Down timer: Designing of 4 bit UP/DOWN timer circuit in TSMC 180nm technology.
Design the schematic and perform LVS match and test it rigorously for possible cases.
CAD Tools: Cadence Virtuoso
Work Experience:
Aug ’16 – Present Mentor for EE352 (Computer Organization and Architecture)
July ‘14 – Dec ‘14 Lecturer at Shri Guru Gobind Singhji Institute of Engineering and Technology (SGGSIE&T), Nanded, India
May ‘13 – July ‘13 Internship at Indian Institute of Technology, Bombay, India