This document outlines a project that aims to improve the performance of the Advanced Encryption Standard (AES) algorithm by implementing it using multicore processors and OpenMP parallel programming. It discusses limitations of existing single-core AES implementations including long execution times for large data files. The proposed methodology is to assign blocks of an input file to different processor cores for parallel encryption/decryption. Hardware requirements of a multicore processor, RAM, and software including JDK and Eclipse are listed. A literature review covers past work on parallelizing AES using strategies like divide-and-conquer and extending block sizes. The expected result is reduced execution time for AES when implemented in a multicore versus single-core system.

1. ANALYZING THE EFFECTIVENESS OF THE
ADVANCED ENCRYPTION STANDARD
ALGORITHM ON MULTICORE PROCESSOR
Presented By
Chethan B M 4BB13CS011
Nikhil Jain C S 4BB13CS021
Sharath M S 4BB13CS029
Under the guidance of
Mrs. Kavitha C.R.
Associate Professor & HOD
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
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2. CONTENTS
• Aim
• Scope
• Objectives
• Problem definition
• Literature survey
• Existing system
• Drawbacks of Existing systems
• Advantages of proposed system
• Methodology
• Hardware and software requirements
• References
• Result expected
• Gantt chart
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3. AIM
To implement and improve the performance
of Advanced Encryption Standard algorithm by
using multicore systems and OpenMP API
extracting as much parallelism as possible from the
algorithm in parallel implementation approach.
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4. SCOPE
• The requirement of information security on a network has
become highly challenging.
• Cryptography is a method to provide information
confidentiality, authenticity and integrity.
• The cryptography overcomes several challenges such as
execution time, memory requirement, and computation power.
However, one cannot get desired outcomes by using sequential
computation.
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5. OBJECTIVES
• To facilitate encryption and decryption of large data.
• To reduce execution time by using multicore system.
• To compare the execution time of single core and
multicore systems.
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6. PROBLEM DEFINITION
• Secure transmission of information from one
place to another.
• The sensitive information must be unreadable to
all others except the receiver.
• Performance limitations of AES algorithm such
as memory requirement and execution time.
• Secure way of transfering the sensitive
information.
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7. LITERATURE SURVEY
PERFORMANCE IMPROVEMENT OF ADVANCED
ENCRYPTION ALGORITHM USING PARALLEL
COMPUTATION
Author: M. Nagendra, M. Chandra Sekhar.
Year: 2014
In this paper, mainly divide-and-conquer strategy is used
in parallel computation to solve the algorithms in parallel by
partitioning and allocating, number of given subtask to available
processing units.
Disadvantages:
Divide and conquer strategy works slow for large data
files and recursion is slow. Sometimes once the problem is
broken down into some sub problems, the same sub problem can
occur many times.
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8. AN IMPLEMENTATION OF AESALGORITHM ON
MULTICORE PROCESSORS FOR HIGH
THROUGHPUT
Author: Supachai Thongsuk, Prabhas.
Year: 2014
AES algorithm is a block encryption algorithm established by
the U.S. National Institute of Standards and Technology (NIST) in
2001. It has been adopted by many data security systems and now
used worldwide. Most of AES implementations are for single-core
processors. To achieve high performance for large data, this work
proposed an AES algorithm for multi-core processors. Using
parallelism inherent in large data, all cores are working concurrently
to speed up the task.
Disadvantages:
In this paper, Open MP (Open multiprocessing) is not used.
Open MP is one of the application programming interface which is
supported by multicore architectures to provide multithreaded shared
memory parallelism. So by using multicore architectures we can
parallelize the execution of AES algorithm among different cores to
reduce the execution time of the algorithm.
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9. DESIGN OFAN EFFICIENT ARCHITECTURE FOR
ADVANCED ENCRYPTION STANDARD ALGORITHM
USING SYSTOLIC STRUCTURES
Author: Suresh Sharma, T S B Sudarshan.
Year: 2005
This Paper presents a systolic architecture for Advanced Encryption
standard (AES). Use of systolic architecture has improved the hardware complexity
and the rate of encryption/decryption. Similarities of encryption and decryption are
used to provide a high performance using an efficient architecture. The encryption
or decryption rate increases due to the use of pipelined systolic architecture.
Disadvantages:
Here only one core is used irrespective of the size of the file which has to
be encrypted or decrypted. This method will work slowly if the data file is big in
size. It may work well for data files which are small but it is sure that it takes much
longer time to encrypt and decrypt the data for bigger files
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10. DESIGN AND IMPLEMENTATION A DIFFERENT
ARCHITECTURES OF MIXCOLUMN IN FPGA
Author: Sliman Arrag, Abdellatif Hamdoun, Abderrahim Tragha and
Salah eddine Khamlich
Year: 2014
This paper details Implementation of the Encryption algorithm AES under
VHDL language In FPGA by using different architecture of mixcolumn. We then
review this research investigates the AES algorithm in FPGA and the Very High
Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus
II software is used for simulation and optimization of the synthesizable VHDL
code.
Disadvantages:
VHDL is complicated and confusing language. Hardware that is
synthesized is not always obvious. Constructs that have similar syntax have very
different semantics. It is not suitable for verifying the basic objects like gates.
Mixcolumn is a modular multiplication which is a complex one.
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11. REORDERING ALGORITHMS FOR INCREASING
LOCALITY ON MULTICORE PROCESSORS
Author: Juan C. Pichel, David E. Singh and Jes´us Carretero.
Year: 2014
In this paper a technique for increasing locality of sparse
matrix codes on multicore platforms is presented. The technique
consists on reorganizing the data guided by a locality model which
introduces the concept of windows of locality. The evaluation of the
reordering technique has been performed on two different leading
multicore platforms: Intel Core2Duo and Intel Xeon.
Disadvantages:
The proposed data reordering technique has been tested on
two different leading multicore processors: Intel Core2Duo and Intel
Xeon only. All the codes were written in C, which makes more
complex.
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12. AREA OPTIMIZED ADVANCED ENCRYPTION STANDARD
Author: Sandip R. Aher, G. U. Kharat.
Year: 2014
This paper shows various approaches for efficient FPGA implementations
of the Advanced Encryption Standard algorithm. For different applications of the
AES algorithm may require different speed/area tradeoffs, they propose a vital
study of the possible implementation schemes, but also the discussion of design
methodology and algorithmic optimization in order to improve previous reported
results. They propose system to evaluate hardware efficiency at different steps of
the design process. They also use an optimal pipeline that takes the place and route
constraints into account.
Disadvantages:
Algorithm will be implemented using single core systems and thus it
works slower for large files.
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13. 13
PARALLEL EXECUTION OF AES-CTR ALGORITHM USING
EXTENDED BLOCK SIZE
Author: Nhat-Phuong Tran, Myungho Lee, Sigwon Hong.
Year: 2011
In this paper, they propose a new approach to parallelize AES-CTR algorithm
by extending the size of the block which is encrypted at one time across the unit block
boundaries. The proposed approach leads to significant performance improvements
using a general-purpose multi-core processor and a Graphic Processing Unit (GPU)
which become popular those days.
Disadvantages:
In this paper, GPU is used which consumes more power, so this could effect
battery life and also cost of GPU is high

14. Existing System
• The implementation of encrypting the data that
is converting the plain text in to cipher text and
decrypting the data is by using the single core
system.
• The concept of double encryption and double
decryption is used.
• Since twice encryption and decryption takes
much time.
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15. Drawbacks of Existing systems
• In the existing system only one core is used
irrespective of the size of the file which has to be
encrypted or decrypted.
• Using only one core will work slowly if the data
file is big in size. It may work well for data files
which are small but it is sure that it takes much
longer time to encrypt and decrypt the data for
bigger files.
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16. ADVANTAGES OF PROPOSED
SYSTEM
• The concept of parallel programming by using a multi-
core processor is proposed .
• Proposed system shows how to efficiently and
effectively implement the Advanced Encryption
Algorithm by using multicore systems and OpenMP
API.
• The AES algorithm is implemented using multi core
systems and thus it works faster even for large files.
• The time taken to encrypt/decrypt the large data is
reduced.
• The comparision of execution time of single core
system and multicore system is shown. 16

17. METHODOLOGY
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• The input is a text file consisting of n-blocks of data.
• The first n/2 blocks can be assigned to one core for
encryption/decryption, while another n/2 blocks can be assigned to
another core for performing encryption/decryption.
• The encryption/decryption on multiple blocks of data is done
simultaneously by using the concept of simultaneous multithreading,
some of the blocks by one core and some of the blocks by another core.
This process will continue until the end of the file.

18. 18

19. HARDWAREAND SOFTWARE
REQUIREMENTS
•1.4 GHz processor
•2 GB RAM
•40 GB hard disk
•JDK 1.8
•Eclipse
•Apache tomcat 9
•MySQL 19

20. 20
REFERENCES
JOURNALS
[1] M. Nagendra and M. Chandra Sekhar ., “Performance
Improvement of Advanced Encryption Algorithm using Parallel
Computation”, International Journal of Software Engineering and Its
Applications.
[2] Supachai Thongsuk1, Prabhas Chongstitvatana., “An
implementation of AES algorithm on multicore processors for high
throughput”, Department of Computer Engineering Faculty of
Engineering, Chulalongkorn University Bangkok, Thailand.
[3] Nhat-Phuong Tran, Myungho Lee, Sigwon Hong., “Parallel
Execution of AES-CTR Algorithm Using Extended Block Size”, Dept
of Computer Science and Engineering, Myong Ji University.
cont…

21. 21
cont…
[4] Suresh Sharma, T S B Sudarshan., “Design of an Efficient
Architecture for Advanced Encryption Standard Algorithm Using Systolic
Structures”, International Conference of High Performance Computing.
[5] Sliman Arrag1, Abdellatif Hamdoun 2, Abderrahim Tragha 3 and
Salah eddine Khamlich., “Design and Implementation A different
Architectures of mixcolumn in FPGA”, Department of Electronics and
treatment of information UNIVERSITE HASSAN II MOHAMMEDIA,
Casablanca, Morocco.
[6] Juan C. Pichel, David E. Singh and Jes´us Carretero., “Reordering
Algorithms for Increasing Locality on Multicore Processors”, Computer
Science Dpt. Universidad Carlos III de Madrid, Spain.

22. Result Expected
•To obtain an improved execution
time for AES algorithm in multicore
system over single core system
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23. 23
THANK YOU

24. QUERIES???
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