1. Mohammed Salman Mandoor Khan
500 El Camino Real, SCU: 3137, Santa Clara, 95053 CA E-mail: salmanmandoor@gmail.com
Phone: +1 408 921 5987 LinkedIn: http://www.linkedin.com/in/salman4
Objective: Seeking a full-time position / internship in the field of Digital Design and Verification
Education:
Santa Clara University Santa Clara, CA
Master of Science in Electrical Engineering; GPA: 3.22 Expected June 2015
Key Courses: Fund. of Semiconductors, VLSI Design-1, Logic Analysis & Synthesis, Logic Design using Verilog
HDL, VLSI Design-2, Semi-Custom Design with Programmable Devices, System on Chip (SoC) Formal Verification,
Design for Testability, Modern Timing Analysis, VLSI Physical Design, High Level Synthesis, Computer Architecture
Osmania University Hyderabad, India
Bachelor of Engineering in Electronics and Communication Engineering; GPA: 3.36 2013
Skills:
 Tools Used: Xilinx ISE, Mentor Graphics IC Studio, Synopsys VCS, Vivado Tool Chain, Synopsys Formality,
Design Compiler, Lattice Diamond
 Languages: Matlab, Verilog, VHDL, System Verilog, Assembly Language, Python, C & C++
 Environment: Microsoft Windows, Macintosh, Linux
Projects:
Design and Implementation of 32-Bit ALU with Data Memory & Register File SCU, 2014
 Designed an ALU, a register file, and a data memory using verilog
 Used Xilinx Vivado tool chain to implement design through place-and-route to determine the fastest speed
of operation by tightening & timing constrains and used Lattice Diamond for compilation and synthesis
Design of Hamming code Encoder & Decoder with random error injection in Verilog SCU, 2014
 Designed a chip that encodes and decodes a data stream using Hamming Code
 Injected random errors into the data stream and used decoder to fix single-bit errors
System on Chip Formal Verification SCU, 2014
 Collaborated with team to design and formally verify IO Controller & 4-Bit Adder with Zero Detection
 Designed and synthesized the chips using Verilog and verified it’s functionality
Physical Design of Priority Encoder SCU, 2014
 Designed a 4-bit priority encoder in Verilog and synthesized the netlist using Leonardo Spectrum
 Used IC Studio/ IC Station for place & route, floor planning and global routing
Design of a Single Cycle Control and Data path of a 32-Bit MIPS Processor SCU, 2014
 Implemented and simulated different components of the data path and developed the RTL code
 Used Verilog to design and Synopsis VCS for simulation & verification
Schematic and Layout Design of 4-Bit Manchester CarryChain Full Adder SCU, 2013
 Used Mentor Graphics - IC Studio to design the schematic and layout of a 4 – Bit Manchester Carry Chain
Full Adder and performed transient analysis, LVS & DRC checks
Face Recognition System with GSM Alerts Hyderabad, India
 Collaborated with team to develop a Face Recognition System using MATLAB 2012
Experience:
Bharat Sanchar Nigam Limited (Telecom Trainee) Hyderabad, India
 Completed one month regional telecom training on telecom technologies July 2012
 Developed understanding of broadband and OFC installation with GSM and CDMA BTS
Premier Solar Systems Limited (Summer Intern) Hyderabad, India
 Demonstrated understanding of solar panelling, tilt angle and spacing June 2011 – July 2011
 Worked in a team to design a parking garage with solar panels for the roof