1. Luke Grantham
Phone: 619-339-3958 Email: Lukeographer@gmail.com
LinkedIn: https://www.linkedin.com/in/lukegrantham
Driven student-professional seeking a career in hardware engineering applications.
EDUCATION:
University of Southern California: Master of Science in Electrical Engineering Expected: December 2021
Cumulative GPA: 4.0 (PART TIME STUDENT)
Relevant Coursework: System Verification, Design and Diagnosis of Reliable Digital Systems, Computer Systems Organization, MOS
VLSI Design.
San Diego State University: Bachelor of Science in Computer Engineering Conferred: May 2019
Cumulative GPA: 3.61, Dean’s List (2015-19) Cum Laude.
Relevant Coursework: Microprocessors, Digital Circuits, Modeling and Simulation, Multimedia Communication Systems, Digital
Signal Processing, Computer Networks, Circuit Analysis, Data Structures and OOP, Computer Vision, and Signals and Systems.
SKILLS AND TRAINING:
Languages: C, C++, Verilog, SystemVerilog, Python, VBScript, MATLAB, MIPS/ARM/x86 Assembly, Bash, VHDL.
Technologies: PCIe Gen4, NVMe 1.4, UVM, FPGA, High-speed analog analysis, SoC/ASIC Architecture, Git, UART, SATA,
I2C, AXI, Ethernet.
Tools: Xilinx Vivado, QuestaSim, Teledyne LeCroy Protocol Analysis Suite, Xgig Analysis Suite, LTSpice, Quartus II, Oscilloscopes,
Cadence Virtuoso, SolidWorks 2018, Microsoft Office Suite.
Non-Technical: Team-oriented goals, strong interpersonal skills, excellent communicator, fast learner, excels under pressure, open
minded, effective problem-solver, team player, and golf.
RELEVANT INDUSTRY EXPERIENCE:
ASIC Validation Engineer – ASIC Design Engineering, Western Digital Corporation May 2019 – Present
o Successfully accelerated tape-out of two SoCs thorough validation of pre-silicon designs from implementation on FPGA
(or similar) platforms to post-silicon ASICs for client and enterprise SSD/HDD data storage products.
o Actively expanded automated and manual validation procedures of PCIe and NVMe hardware/firmware across multiple
host platforms using integrated Synopsys and Broadcom IP blocks.
o Coordinated debugging of in-house developed blocks integrated with vendor IP to ensure robust functionality and
specification compliance.
o Collaborated closely with vendor and in-house ASIC design and firmware engineers in debugging SoCs to ensure host
interface QoS.
Automation and Controls Engineer (Part Time), AIM Aerospace May 2018 – December 2018
o Programmed, installed, and tested Inductive Automation SCADA control systems, collaborative Universal Robots,
PLCs, IOT integration, and SQL database administration.
o Accomplished real-time updating and debugging of systems to drive the completion of production deadlines.
Project Engineer, Grantham Engineering Inc. Jun. 2017 – July 2019
o Experienced in design, drafting and analysis of structures consisting of lifting devices, canopies, docs, tanks, and others.
o Utilized CAD design in SolidWorks, RISA 3D, RISA Foundation, and RISA Connection to determine appropriate design
specifications.
PROJECTS:
Intelligent Verification: Functional Verification of Complex Systems using Deep Learning
o Designed, constructed, and verified a Deep Learning Neural Network framework in conjunction with UVM model to
generate, filter, and apply test vectors to achieve maximal coverage while minimizing redundancies.
o Successfully implemented the framework on pipelined 32-bit MIPS processor with full forwarding and hazard detection.
32-bit MIPS Processor Design & Verification (Verilog, SystemVerilog, UVM)
o Designed 5-stage pipelined MIPS processor in RTL coding in Verilog and verified functionality in QuestaSim.
o Verified FIFO design using UVM methodology through assertions and covergroups to ensure functional coverage
