PROFESSIONAL SUMMARY: To be associated with a semiconductor industry that provides me boundless growth opportunities and exposure to cutting-edge technologies and learning possibilities. AREAS OF INTREST: • Verilog,System Verilog • Digital Circuit Design • Verification(uvm)

1. Sajeeth Raj S
598, North Kollaimedu, Email:008sajeeth@gmail.com
Kilarasampattu, Vellore, Mobile: +91 9080541238
Tamil Nadu, India-632312
LinkedIn ID: https://www.linkedin.com/in/sajeeth-raj-78361b160
Career Objective
I am fresh engineering graduate looking for a full-time position. An enthusiastic self-starter with strong
leadership and communications skills. Proven academic and curricular achievements , and possess the
right technical and soft skills required to propel the organization achieving its goals and objectives.
Education Details
Class/
Course
(stream)
Name of the institution Board of Study/
University
Year of
Passing
Aggregate
B.E(ECE)
Arunai Engineering
College, Tiruvannamalai.
Anna University,Chennai.
2018 67.1%
HSC
NKM Higher Secondary
School,
Vellore.
State Board 2014 62.2%
SSLC
Don Bosco High
School,Vellore. State Board 2012 70.6%
Professional Qualification
Advanced VLSI Design and Verification course
Maven Silicon VLSI Design and Training Center, Bangalore
Dec 2018 - Till Date.
Technical Skills
HDL : Verilog
HVL : System Verilog
Verification Methodology : Coverage Driven Verification, Assertion Based Verification
TB Methodology : UVM
EDA Tools : Riviera Pro – Aldec
ISE – Xilinx
Domain : ASIC/FPGA front-end Design and Verification
Knowledge : RTL Coding, FSM based design, Simulation,
Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis, SVA

2. VLSI Projects
[1] SPI Controller Core - Verification
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Riviera Pro - Aldec
Description: The SPI IP core provides serial communication capabilities with external device of variable
length of transfer word. This core can be configured to connect with 32 slaves.
Responsibilities:
➢ Architected the class based verification environment in UVM
➢ Defined Verification Plan
➢ Verified the RTL module using System Verilog
➢ Generated functional and code coverage for the RTL verification sign-off
[2]Router 1x3 – RTL design and Verification
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tools: ISE – Xilinx and Riviera Pro – Aldec
Description: The router accepts data packets on a single 8-bit port and routes them to one of the three
output channels, channel0, channel1 and channel2.
Responsibilities:
➢ Architected the block level structure for the design
➢ Implemented RTL using Verilog HDL.
➢ Architected the class based verification environment using System Verilog
➢ Verified the RTL model using System Verilog.
➢ Generated functional and code coverage for the RTL verification sign-off
➢ Synthesized the design.
Curriculum Project
[1]An IoT Based Fire Alarm Authentication System Using RASPBERRY PI3 From
BSNL , ,Chennai ,Tamilnadu
Description: Raspberry Pi-3 has been used to control which are integrated with a couple of sensors and
camera. We have provided a confirmation of the fire suspecting system to avoid any false alarm and
surveillance.
Platform: Raspberry Pi-3,Smoke sensor, Flame sensor, web camera.

3. Activities
➢ Short film 2nd
place in Arunai Engineering College for Aecofest 2018 , Thiruvannaamalai
➢ Participated in National Level symposium in S.K.P Engineering College, Thiruvannaamalai
➢ Participated in National Level symposium in GTEC Engineering College, Vellore
➢ Social Service for Voluntary Blood donation in TamilNadu Govt Medical College & Hospital,
Thiruvannaamalai
Personal Details
NAME : Sajeeth Raj.S
FATHER NAME : Mr.C.Srinivasan
DATE OF BIRTH : 21-11-1996
NATIONALITY : INDIAN
AGE : 22
GENDER : Male
MARITAL STATUS : Single
LANGUAGES KNOWN : Tamil, English
Behavioral Skills
➢ I am a very people friendly person.
➢ I am ambitions.
Declaration
I do hereby declare that all the information given above is true to the best of my knowledge and belief.
Signature
Sajeeth Raj.S