The line control unit LCU has several important functions. LCU at primary station serves as an interface between the host computer and the circuit it serves. The LCU directs the flow of input and output data between the different data communications links and their respective applications program. The LCU performs parallel-to-serial and serial-to-parallel conversion of data and transfers to modem serially. LCU also performs error detection and correction apart from inserting and deleting data link control characters.
2. Parallel data transfer
âSignaling elements sent down the line all 8 bits at a
time.
âOne clock loads 8 bits.
â8 times faster than serial transmission.
âData available to PC in desired form.
âBest suitable for internal BUS.
âRequires much larger cabling infrastructure.(One wire per
bit)
âCan not be used for longer distances as delay in each
wire may be different.
3. Serial data transfer
âSignaling elements sent down the line one at a time.
âOne clock loads one symbol.
âEach signaling element may be
â Less than a bit â Manchester code
â One bit long -- NRZ-L, FSK, etc..
â More than a bit â QPSK.
âRequires much lesser cabling.
âCan be used for longer distances.
âSlower than parallel transmission.
âSynchronization is a critical issue.
4. Serial data transfer
âReceiver should recognize beginning and end of bit
stream and each bit duration.
âIf Transmitter and Receiver are not synchronized, bits
sampled would be erroneous.
âError may not occur immediately but will occur later
due to cumulative effect.
5. Serial data transfer-- Example
âTr rate is 10,000 bits/ s.
âBit time T = 0.1ms
âBits sampled at mid-bit time = 0.05ms away from both ends.
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!
!
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âReceiver clock faster or slower by 1%.
âEach pulse will be sampled at a cumulative of 0.001ms.
âAfter how many bits, it would be samples at the edge of the bit?
â50 bits.
â51st bit sampled will be the adjacent bit â error.
âLarger the CLK difference, earlier the error.
0.1ms
0.05ms
6. Asynchronous Transmission
âData sent one character at a time.
âData can be 5 to 8 bits in length.
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!
!
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âReceiver resynchronizes with each character.
âLarger difference in CLK of TR and REC can also be
accommodated as only 8 bits max transmitted together. How
much ?
âReceiver alerted with a start bit.
7. Asynchronous Transmission
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!
!
!
!
!
!
âIdle â1â is negative voltage and â0â is positive voltage.
âReceiver is activated with one bit start bit i.e. positive pulse.
âFollowed by 5 to 8 data bits and one bit parity.
âFrame ends with 1 to 2 stop bits â idle 1âs.
âNew character will have a new start bit.
START
BIT
One
character
P STOP
BITs
0
1
8. Asynchronous Transmission
âADVANTAGES:
âSimple and cheap.
âResynchronizes at every start bit.
âVery good for low speed transmission.
âExample: PC connected to real time terminal where operator feeds
manually.
âDISADVANTAGES:
â2 to 3 bits overhead per character(25%).
âAdditional gap between words.
9. Synchronous Transmission
âBlocks of characters or bits transmitted without start or stop bits.
âREC synchronizes with either separate clocking line or clocking info
embedded in data.
âPre-amble and post-amble bits sent at beginning and end
respectively for synchronization.
âTYPES:
â Character oriented transmission
â Bit oriented transmission
10. Character Oriented Synchronous Transmission
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!
!
!
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âData and control information both in character form.
âIndividual bits have no meaning, except in character form.
âSYNC are predetermined unique bit pattern in character form for
synchronization of Rec.
âPost amble can be avoided by stating length of data.
âOverheads are very less as large chunk of data can be sent with
one set of headers.
Other control
information
S
Y
N
S
Y
N
S
Y
N
S
Y
N
DATAPreamble
Post amble
Address
11. Bit Oriented Synchronous Transmission
!
!
!
!
!
âData and control information both in bit form.
âEvery bit has a definition.
âOverheads are very less as large chunk of data can be sent with
one set of headers.
Control Field
Fâ¨
Lâ¨
Aâ¨
G
â¨âŚFâ¨
Lâ¨
Aâ¨
G
DATA8 bit flag
8 bit flag
Address CRC
12. Line Control Unit LCU
âPC is Data Terminal Equipment DTE.
âDTE feeds Data Communication Equipment DCE. (MODEM).
âDTE gives parallel data, which needs to be carried to DCE as serial
data.
âLCU converts parallel data to serial data.
âTYPES:
â UART Universal Asynchronous Receiver/Transmitter.
â USRT Universal Synchronous Receiver/Transmitter.
13. UART Universal Asynchronous Receiver/Transmitter
âUsed to transmit asynchronous data format without clocking
information.
âFUNCTIONS:
âPerforms parallel to serial and serial to parallel conversion at
Transmitter and Receiver respectively.
âPerform error detection by inserting and checking parity bits at
Transmitter and Receiver respectively.
âInserts and detects start and stop bits at Transmitter and Receiver
respectively.
âUses a control word to accommodate options for parity, data and
stop bits.
âControl word must be programmed into UART control register prior
to transmission.
14. UART Control Word
âSTART Bit: Always a single bit â0â, +ve voltage. No other option.
âNumber of Parity Bit NPB:
â NPB â1â = No parity bit used.(RPE disable)
â NPB â0â = One Parity bits used
â EVEN or ODD Parity POE:
â POE â1â = Even Parity
â POE â0â = ODD Parity
â Number of STOP Bits NSB
â NSB â1â = 2 stop bits
â NSB â0â = 1 stop bits
15. UART Control Word
âNumber of DATA Bit NDB1, NDB2:
!
!
!
!
!
!
!
âIf NDB2-NDB1 is 11 and NSB is 1 then:
â NSB = 1.5
NDB2 NDB1 Bits/word
0
0
1
1
0
1
0
1
5
6
7
8
16. UART Transmitter
Transmit Buffer Register
TD7 TD8TD5 TD6TD7 TD4 TD9 TD0
TDS
Control Register
NPB NSB NDB1 NDB2
CS
Parity
Generator
Data bits, Parity bits, Stop bits Steering Logic
Circuit
O/P
Ckt
Buffer Empty Logic Circuit
TEOC
Timing
Generator
TCP
Status Word Register
SWE
TBMT
TSO
Start Bit
17. UART Transmitter
âUART sends TBMT, a transmit Buffer Empty signal to DTE to indicate
it is ready to receive data.
âSensing an active TBMT, DTE sends parallel data character to
transmit data lines (TD0 - TD7).
âIt strobes them into Transmit Buffer Register using Transmit Data
Strobe signal and TBMT becomes low.
âContents of Transmit Buffer Register are transferred to Transmit
shift Register when TEOC, Transmit End of Character, goes active to
indicate Transmit Shift Register is empty.
âParity generator generates parity as per data bits.
âData passes through steering logic circuit and picks Start, Stop and
Parity bits as decided by Control Word in Control Register.
âComplete word is now serially outputted on the Transmit Serial
Output TSO pin with bit rate equal to Transmit Clock frequency TCP.
âAt end of last bit, it activates TEOC.
18. UART Transmitter
âWhen data shifts from Transfer Buffer Register to Transmit Shift
Register, Buffer Empty Logic Circuit updates Status word register to
activate TBMT.
âActive TBMT signals DTE to load new word on Buffer Register.
â It will wait for active TEOC when last serial bit goes out and moves
to shift register.
âProcess continues.
20. UART Receiver
Receive Shift Register
Receive Buffer Register
Status Word Register
Receive
Timing
Circuit
Control
Register
Parity
Checker
Start Bit
Verify
RSI
RCP
RD7 RD0
RPE
RDAR
RFE RDA ROR
SWE
RDE
RSI â Receive serial input
RCP â Receive clock pulse
RPE â Receive parity error
RFE â Receive flag error
ROE â Receive overrun
RDA â Receive data available
SWE â Status word enable
RDAR â Receive data available reset
21. UART Receiver
â Control word defining number of stop bits, data bits and parity
information is same as used for transmitter.
â UART receiver ignores idle time 1s.
â When valid start bit is detected by start bit verification circuit, data
character is serially clocked in to Receive Shift Register.
â If parity is used, the parity bit is checked in Parity Check Circuit.
â After full data character is loaded in shift register, character is
parallel loaded into Receive Buffer Register.
â Receive Data Available (RDA) flag is set in Status Word Register.
â DTE monitors Status Word Register through Status Word Enable
SWEâ.
â When RDA goes high, it reads character from Receive Buffer
Register using Receive Data Enable RDEâ.
â DTE then activated RDARâ, Receive Data Available Reset, which
resets RDA pin.
â Process continuesâŚ
22. UART Receiver
â Status Word Register also used for diagnostic information.
â Receive Parity Error, RPE flag is set when received character has
parity error.
â Receive Framing Error RFE flag is set when the character is
received with improper number of stop bits.
â Receive Overrun, ROR flag is set when character in buffer is
overwritten by another character as DTE fails to check RDA and
download bits.
â Receive Clock for UART (RCP) is 16 times higher than receive data
rate.
â This allows start bit verification circuit to identify valid high-to-low
transition from among negative going noise spikes.
23. Start Bit
Verification
â Once a low is detected, verification circuit counts-off 7 clock
pulses and samples the line.
â If found still low, it is a valid start bit as noise spike will not hold
that long.
â If found high, it was a noise spike.
â Once a valid start bit received, verification circuit samples
incoming bits once every 16 clock cycle.
24. UART Receiver Timing Diagram
WORD 1 WORD 2 WORD 3
RSI
STATUS STATUS
RDA
RPE, RFE, ROR
SWE
RDE
RDAR
25. USRT Universal Synchronous Receiver/Transmitter
âUsed to transmit synchronous data format with clocking
information.
âFUNCTIONS:
âPerforms parallel to serial and serial to parallel conversion at
Transmitter and Receiver respectively.
âPerform error detection by inserting and checking parity bits at
Transmitter and Receiver respectively.
âInserts and detects sync characters at Transmitter and Receiver
respectively.
âUses a control word to accommodate options for parity and data
bits.
âControl word must be programmed into USRT control register prior
to transmission.
âControl word same as UART except for stop bits.
26. USRT Transmitter
Data Bus
DB0DB1DB7 DB6 DB5 DB4 DB3 DB2
Transmit Data Register Transmit Sync Register
TSS
Timing and
Control
Transmit
!
!
Control
Register
TCP
TDS
TBMT
SCT
NDB1
CS
NDB2
POE
NPB
Multiplexer
Transmit Shift Register TSO
27. USRT Transmitter
âTransmit clock signal (TCP) is set at desired bit rate.
âDesired SYNC character is loaded from parallel input pins (DB0-DB7)
into Transmit Sync Register by Transmit Sync Strobe TSS.
âData are loaded into Transmit Data Register from parallel input pins
(DB0-DB7) using Transmit Data Strobe TDS.
âNEXT character is extracted from Transmit Data Register if TDS pulse
occurs during presently transmitted character.
âOtherwise NEXT character is extracted from Transmit SYN Register
and SYN Character Transmitted flag (SCT) is set.
âTransmit Buffer Empty TBMT signal is used to request next character
from DTE.
âSerial output data appears on Transmit Serial Output TSO pin.
âControl Register stores Control word containing number of data and
parity bits per word and type of parity.
âCS selects the USART only when active low. CS high does not mean
standby, but means not selected that time.
29. USRT Receiver
âThe Receive Clock signal (RCP) is set at desired bit rate.
âDesired SYN character is preloaded into Receive Sync Register
through (DB0-DB7) using Receive SYN Strobe RSS.
âOn high-to-low transition of Receive Rest input (RR) in Timing and
Control Receive, receiver is placed into bitwise search mode -
âto examine serially received data bit-by-bit for SYN character.
âData is loaded into Receive Shift Register bitwise through RSI,
Receive Serial Input.
âComparator compares contents of Receive Shift Register with
contents of Receive SYN Register.
âOn receiving SYN, SYN Character Receive (SCR) output is set.
âSYN character is transferred to Receive Buffer Register and
receiver is placed in character mode.
âReceived next data is received bitwise but examined in character
mode and RDA is set.
30. USRT Receiver
âReceived data is checked for receiver overrun or receive parity
error and respective flags ROR or RPE are set if found with
problems.
âAll control signals SCR, RDA, ROR, RPE are available in Status
Word Register.
âCorrect data is outputted to DTE through pins (DB0-DB7) using
Receive Data Enable strobe RDE.
âReceive Data Available Reset RDAR is set to reset RDA pin.