1. MassimilianoBracco
Personal identifying data:
Address: rue de Nugerol n. 21
City: Le Landeron
Postal Code: 2525
Country: Switzerland
Email: max.bracco@libero.it
Birthday 13 December 1973
Birthplace: Johannesburg (South Africa)
Civil status: Married
Nationality: Italian
Job: Analog/Digital designer
Military status: I did the conscription in 2000.
Education:
 MEAD education Lausanne (August 24-28 2015): POWER MANAGEMENT
 MEAD education Lausanne (July 1-5 2013): MICRO-POWER ANALOG IC
DESIGN
 MEAD education Lausanne (August 27-31 2012): ADVANCED CMOS
ANALOG IC DESIGN
 December 2004: Marie Curie Training program at Mikron AG in Muenchen.
Project and realization of S.O.C. mixed signal ASICs for automotive applications.
 March 2003: Ph.D. degree in Electronics Engineering at University of Genoa
with a dissertation about: “Project and realization of microcircuits for digital
data elaboration”. During Ph.D. I followed :
 “Integrated systems architecture”, Prof. A. De Gloria.
 “Functional analysis for optimization”, Prof. T. Zolezzi.
 “Industrial electronics 2”, Prof. Rodolfo Zunino.
 December 1999: I earned my degree certificate in Physics (specialization subject:
microelectronics) at University of Genoa with grade 104/110 with a dissertation
about: “Project of a Controller Area Network (CAN)”.
 I followed a course about “Guidance for start-up company creation-5°
Edition” of 34 hours planned by “Provincia di Genova” at “Centro Ligure per la
Produttività” in Genova.
Publications

2. [1] M. Bracco, S. Ridella, and R. Zunino, “Digital implementation of Hierarchical Vector
Quantization”, IEEE Trans. on Neural Networks Special Issue on Hardware Implementations
vol. 14, pp. 1072–1084, Sep. 2003
[1] M. Bracco, S. Ridella, and R. Zunino, “A Model-Selection Approach to the VLSI Design
of Vector Quantizers”, Proc. 2003 International Joint Conference on Neural Networks,
Doubletree Hotel - Jantzen Beach, Portland, Oregon , USA, July 20-24, 2003.
Patent pending: simplified algorithm for digital data interpolation
Patent pending: resonant speaker to produce high volume alarm
Patent pending: power optimized quartz driver for wrist watches applications
Professional Experience (summary):
 Since 1st of April 2009 I am an analog/digital ASIC designer at ASULAB: research
and development department of the Swatch Group. Low power analog and digital
ASIC design for wrist watches applications or ultra-low power and low supply voltages
applications.
 From 10th of January 2005 to 28th of February 2009: digital designer at
Infineon Chip Card group: research and development division.
Responsible for sensors modules: concept, design and implementation of the digital
interface, integration of sensors modules into system, assembler programming for
silicon characterization and test.
 Power estimation simulations at system level.
 Top level mixed-signal simulations.
 Since 2008 responsible for VHDL regression test with Modelsim and in-house tool for
regression run and configuration.
 Some introductive Specman knowledge and experience.
 1 Year and 9 months (digital designer at Mikron AG): Marie Curie Fellowship for
ASIC mixed signal S.O.C. design using Cadence tools for simulation, place and route,
Design for Test, test patterns generation (Mentor tool).
 3 Year (Ph.D.): high speed S.O.C. ASICs (digital and mixed signal) using Cadence
and Synopsys tools for simulation and place and route. FPGA prototyping, test boards
design and realization. Prototypes test using tester machine.
 1 Year (Degree work): high speed FPGA to implement a digital CAN controller for
European Space Agency.
Professional Experience (in detail):

3. ASULAB:
 In charge to design a mixed mode chip in a 0.18u meter technology to drive and
control a mechanical wrist watch. The chip is composed of a low voltage low
power analogue driver circuit for quartz, a power on reset block, a smith trigger, an
analogue circuit to drive the active diodes to charge the capacitance for supply and
digital circuitry to compare the quartz and the dynamo frequencies. The whole
system must sink no more than 60nA with a supply voltage of 0.7V typical
constraint, the minimum supply voltage is 0.5V.
 LCD driver: my task was to develop the test pattern and circuitry for the production
test of the analogue part of the chip. To develop a mixed signal simulation flow
using AMS (ULTRASIM) by CADENCE to get test time evaluation and current
consumption estimations.
 Polyphonic chip: my task to evaluate the quality of the digital signal processing
chain and to develop Matlab and Modelsim models for that purpose. Analog DC-DC
circuit improvement along with top level responsibilities. Test pattern development
for digital audio chain.
 LCD driver: technology migration from 0.35u to 0.18u technology
 Feasibility study and first circuit implementation for an ultra-low voltage dc-dc stage
to start up at 0.3V for an energy harvester system in 0.18u technology.
 MEM switch: my task to contribute to the microelectronic architectural definition
based on MEM sensor and signal conditioning at very low power consumption
requirements.
INFINEON chip card group:
 I was responsible for design and implementation of the digital interface to sensors
modules, integration of the modules into system, assembler and Perl programming
for test and in field application and on silicon characterisation.
 Perform power estimation simulations for sub digital blocks using “Powertheatre” and
system mixed analogue-digital simulations at system level using “Nanosim” and
ADMS (Mentor).
 VHDL regression test with Modelsim and in-house tool for regression run and
configuration.
 I got also some introductive Specman knowledge and experience in testing some
sub-blocks of the system.
“Marie Curie” European Training Program
Systems on chip for automotive applications: microcontroller core, digital peripherals like
timers, memory interfaces, different output protocols and controllers.

4. I was involved in all the development steps of the project:
 definition of the datasheet
 circuit design and implementation
 simulation
 place and route
 back annotation simulations
 implementation of the test logic
 Testing of the prototypes on a test board.
 I wrote assembler codes for field applications and for test routines.
Programming languages
 Basic, QuickBasic, Fortran, C, Assembler, VHDL, HTML, C++, Verilog, Perl, Tcl
Hardware description languages
 VHDL, VERILOG, VHDL-A, VERILOG-A.
Operating systems
 Dos, Windows NT, Windows, Unix, Linux.
Tools
 ASIC design: Synopsys (simulation, timing analysis, synthesis), Silicon Ensemble
(place and route), Modelsim (simulation), Cadence tools for: simulation,
synthesis, place and route, Virtuoso (Cadence layout tools) , HDL designer
(formerly known as Renoir: VHDL development using schematic entry)
 Circuit design test: SpyGlass, Specman, Tetramax
 Power consumption estimation: PowerTheater, Nanosim, Ultrasim
 Top level simulations: Nanosim, ADMS, Ultrasim
 Automatic test pattern generation for scan chain logic: Fastscan
 Printed Circuit Boards design: Orcad
 System model simulation: Matlab
 FPGA digital circuits: Leonardo (timing analysis, synthesis, implementation),
Renoir (VHDL, Verilog description), Modelsim (simulation), ISE Xilinx (all-in-one
tool for Xilinx FPGA design and implementation)

5. Languages:
 Italian
 English
 German
 French