Who Is This Guy?

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Jasmin's profile in pictures and drawings...

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Who Is This Guy?

  1. 1. Who is this guy?<br />Present<br />San Diego<br />California<br />2000<br />1997<br />Ottawa<br />Canada<br />2009<br />2006<br />San Diego<br />California<br />Optical Networks Division<br />1997<br />1993<br />Ottawa<br />Canada<br />* nowMotorola/VideoDistributionDivision<br />* nowMitel/Communications Infrastructure Division<br />1993<br />1989<br />Sarajevo<br />Bosnia<br />Herzegovina<br />2006<br />2000<br />San Diego<br />California<br />www.energoinvest.com<br />1989<br />1984<br />BSEE<br />www.etf.unsa.ba<br />{ Experienced SoC ~ FPGA ~ ASIC ~ Embedded ~ High-Speed } Designer | Architect<br />
  2. 2. SoC Designer | Architect<br />SoC is the chip hosting microcomputer subsystem<br />It typically also sports significant 3rd party IP content<br />SoC is the art of partitioning & creating clean structure with natural, well defined (often standardized) interfaces and buses (AMBA/AXI/AHB/APB, CoreConnect, OpenCoreProtocol, Avalon,…)<br />It’s like my boards (of the `90s), now on the chip <br />A typical ASIC designer lacks the system, application and use-case perspective, which I describe as: <br /> ‘Design Functionality, not only RTL code’<br />
  3. 3. My SoC design/architecture sample<br />
  4. 4. FPGA Designer<br />FPGA is the front-end heaven of Logic Design<br />Logic (If-Then implications) is my strong attribute!<br />Typical ASIC designer produces too ‘cloudy’ RTL which threatens timing closure: FPGA RTL is harder to write!<br />FPGA expertise is also about befriending with underlying gate/clock/interconnect fabric, mega-macros, adapting to them & making choices within the given physicals<br />Xilinx is my specialty: V2Pro, Spartan3, V4, Virtex5<br />‘Programmable Imperative ~ Software Defined Silicon’ <br />C-to-Verilog and HPC4mare my passion (and future of electronics)<br />Check my blog: FPGA Day & Night(http://chili-chips.blogspot.com)<br />
  5. 5. My FPGA design sample<br />
  6. 6. ASIC Designer<br />While FPGA is Logic/RTL/Front-End centric, ASIC has significant Physical/Back-End/Fab workload <br />Tool complexity swells. Tools grow more important. Automation, scripting, processing and filtering of massive netlists and timing reports is often the key <br />I’ve used Synopsys tool flow, TCL, Perl, shell scripting<br />Completed projects in COT and ASIC engagement model (and variants)<br />Worked with standard-cell and <br /> full-custom flows; Transistor-level <br /> analog designers; Place-n-Route,<br /> Packaging guys; DFT gals<br />
  7. 7. My ASIC design sample<br />Hard-macro for DDR3 SDRAM PHY – Pure COT, mixed-signal project<br />
  8. 8. Embedded & High-Speed<br />Embedded is the computing system (CPU/MCU+mem) with few well defined functions which it excels in<br />Designing one needs good judgment for HW/SW partitioning & great deal of CS in addition to EE. I write firmware in ‘C’ and Assembly and have been through schematics/boards <br />Completed significant work in multi-Gbps serial & high-speed DDR connectivity, wearing both designer and user hat; At board, chip and IP level <br />
  9. 9. My Embedded Design Sample<br />First project: 1989/90 <br />ISDN BA Terminal Adapter as an add-on card for the PC ISA bus, based on Intel 80188 micro and Mitel ISDN chipset. I designed all the hardware and wrote device drivers and BIST in ASM86 as ‘C’ externs. Many more projects followed, more complex and higher-speed, but this one remained the dearest… <br />
  10. 10. Experience<br />Experience is the breadth of perspective.<br />It’s knowingwhat$, why? and how!<br />Experience is the insight that guides ~ <br /> ~ Doing it right in the first pass <br />It’s knowing what it takes:<br /> : Setting realistic goals and expectations.<br /> Thanks to experience, one can quickly acquire new domain skills, tools, methodologies…<br />
  11. 11. My Experience<br />20 years<br />in the electronics industry, <br />mostly as the key contributor on advanced, ‘Technology Frontier’ <br />and carrier-class <br />product developments<br />
  12. 12. A Snapshot of Professional Training<br />
  13. 13. A Snapshot of Professional Training (cont’d)<br />
  14. 14. References<br />1) Jim Lew-Digital Design Manager at AMCC<br />http://www.linkedin.com/pub/9/552/80a<br />Jasmin directly reported to Jim.<br />2) Shaw Yuan- Sr. Communication Systems Engineer at Entropic<br />http://www.linkedin.com/pub/2/106/2a9<br />Jasmin worked with Shaw on DSP aspects of FPGA-based proof-of-concept prototype platform for MoCA cable modem technology.<br />3) Omer Acikel- Digital Communication System Engineer at AMCC<br />http://www.linkedin.com/pub/5/a93/729<br />Jasmin worked with Omer on using FPGAs to accelerate Simulink/MATLAB sims of a DFE/FFE-based CDR block for 10Gbps long-reach SerDes.<br />4) LinkedIn Recommendations:<br />View Full Profile: http://www.linkedin.com/in/jasminibrahimovic<br />
  15. 15. Thank You!<br />Q&A<br />www.chili-chips.com<br />

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