• Measured parasitic resistance and capacitance of two cascoded NMOS layout in LNA. Reduced down the parasitic resistance to about 1 ohm using a multi-fingered and multi-contacted layout.
• Analyzed the Q-based tuning of RFIC LNA by adding an ideal capacitor between the gate and source of CS stage of cascoded LNA and the corresponding variation of linearity using Cadence SpectreRF simulations.
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PARASITICS REDUCTION FOR RFIC CMOS LAYOUT AND IIP3 VS Q-BASED DESIGN ANALYSIS USING IBM 130NM TECHNOLOGY
1. THE UNIVERSITY OF TEXAS AT DALLAS
ERIK JONSSON SCHOOL OF ENGINEERING & COMPUTER SCIENCE
EERF 6330 RFIC DESIGN Kenneth O.
SPRING 2016
PARASITICS REDUCTION FOR RFIC CMOS LAYOUT AND IIP3 VS Q-BASED
DESIGN ANALYSIS USING IBM 130NM TECHNOLOGY
BY ILANGO JEYASUBRAMANIAN (ixj150230)
2. LAYOUTFOR CASCODESTAGEOF TWO NMOS IN LNA:
PARASITIC RESISTANCECALCULATION:
Rpoly= 7 ohm/sq, RM1 =0.0709 ohm/sq , RM2,3 =0.0639 ohm/sq
Width of each NMOS = WNFET = 40um
Number of fingers = NF = 40
Width of each finger = WF = 1um
Length of each finger = LF = 0.12um
Widths of gate around the contact : WPCONT = 0.2um, Wp = 0.4um
Width of external gate between transistor and contact = Wext = 0.08um
Lp = 18.84um
Npcont = Lp/Wp = 47
Wcont = 0.16um
Rgp =
1
𝑁 𝑓
[
𝑊 𝑓𝑖𝑛𝑔𝑒𝑟
12∗𝐿
𝑅 𝑝𝑜𝑙𝑦 +
𝑊 𝑓𝑖𝑛𝑔𝑒𝑟
2∗𝐿
𝑅 𝑝𝑜𝑙𝑦 + (
𝑊 𝑓𝑖𝑛𝑔𝑒𝑟
𝑊 𝑝
+ 0.5)
𝑅 𝑝𝑜𝑙𝑦
2
]
Rgp =
1
40
[
1𝑢𝑚
12∗0.13𝑢𝑚
7 +
0.08
2∗0.12𝑢𝑚
7 + (
0.2
0.4
+ 0.5)
7
2
]
6. (b) For Qin =1.5:
Additional Cgs = CT – Cin = 0.4153pF
For Qin =1.5, IIP3 = 0.39dbm
For Qin =0.5:
Additional Cgs = CT – Cin = 1.3pF
For Qin =0.5, IIP3 = 13.59dbm
7. (c): IIP3(mW) vs Qin:
We know that IIP3 =( 8*(Vgs – Vt))/(4*Qin
2 *Zo*3𝜽) which causes the IIP3 increases as Qin decreases. Hence, the circuit
becomes more Linear as Qin decreases.
S-PARAMETER CALCULATION: