Detail of SD24 head and cable connection fixtureCable connection to SD24 ports is achieved by means of two 60mm longSMA semirigid cables soldered to a reference ground plane (FR4 pcb).Cables under test inner conductors are connected together by means ofshort soldered splices.3
S11/S22 (measure)Heavy distributed impedance discontinuities (up to more than 50mrho pp) arepointed out by the measurement.The cable is not symmetrical (S11 not equal to S22) due to these discontinuities4
OPTIMIZED SETUP MODEL(1) : Spicy SWAN schematicThis model utilizes an ERFC approximation of TDR waveform taking intoaccount SMA fixture effects.Connection spices are modeled by two equal TL (TSOLD1,TSOLD2).RG58 CU cable is modeled as a cascade of 366 X 5cm RL-TL cell.6
SETUP DISCONTINUITIES (soldered splices between semirigid fixture )can be used as TIME MARKERS.Comparing the measured S11 (red) to the simulated one (blue) the exactmatching of marker position is achieved adjusting the value of TD ofelementary RL_TL cell of the model. A slight reduction from nominal 25.3psto 24.75ps was needed for perfect match7
FIRST SPLICE MODEL OPTIMIZATIONZ0 and Td of TL model of the splice (TSOLD1) are optimized to matchthe first peak of actual measure . The same parameters are assigned tothe second splice (TSOLD2)8
Actual SD24 TDR HEAD (CSA 803) waveformThe following is the actual waveform generated by Ch1 and observed on Ch2. Theconnection is made using a wideband 40cm SMA cable. In this way the stepdispersion due to the fixture of RG58 cable is taken into account.The resulting risetime is 22.5ps between 20% and 80%, while the observed risetimeat Ch1 (generator) is 17ps.9
Normalized TDR waveform (0-2rho)This is 19-breakpoints PWL approximation of the previous SD24 waveform.The step amplitude has been normalized between 0 and 2rho for utilizationin the simulative DWS model (model 2)10
OPTIMIZED SETUP MODEL(2)This is the Spicy SWAN schematic of the simulative model (2) using the pwlapproximation of TDR step generator (VTDR).Splice models parameters are optimized , and the RG58 elementary RL-TLcell delay is optimized as well. The sim time step has been chosen to be 1/10of elementary cell delay (Tstep=2.475ps) to minimize overall delay errors.11
Spicy SWAN (DWS) results of model (2)The following are the plots of simulated S11 and S22 of previous setup.This sim requires about 30s with about 20K points and 28K model elements.13
The following slides show the differences betweenmeasured and simulated waveforms including setupeffects.14
The RL-TL cell model is practically symmetrical, while the actual cable isnot.Actual cable S11/S22 values are under-estimated with respect model values dueto distributed impedance discontinuities.Overall behavior after first reflection shows good agreement between model andmeaure15
16measuremodelSplice 1discontinuityDistributed impedancediscontinuitiesThe waveforms are not matched in time for better comparison.Distributed impedance discontinuities on the actual cable are wellvisible.
S21 edge comparison (model1)In this slide the absolute delays are taken into account (Splice markers matched)Measured 20%-80% risetime : 80ps vs 70ps of model. The measured waveform has aslower foot but a faster edge in the upper part. This is due probably to dielectric losses(slower foot). The faster upper part can be due to stranded conductors of the actual cable,19S21:measureS21:model
S21 edge comparison (model2)20In this slide the splice markers are NOT exactly matched to superimpose thewaveforms.The measured risetime is identical to that of model:80ps, but the shapedifferences of model 1 are confirmed: slower measured waveform foot andfaster upper portion of measured edgesMeasureModel
21measureRL-TL model5 Gbit/sec10 Gbit/secWCED: Worst Case Eye Diagrams : YELLOW 5Gbit/sec, RED 10Gbit/secEYE CLOSURE and ISI JITTER are slightly higher in the measure due todielectric losses not taken into account in the modelEYE shapes are more symmetrical in the measure: this can be also due todielectric losses not taken into account in the model
22Removing Splices from the simulative model, the simulated eye diagramgets more open and less similar to the eye calculated from actual measure(including splice effects). The dielectric loss effect (not considered in themodel) symmetrizes the eye diagram.
23S11PWL-BTM modelRL-TLS21BTMRL-TLAs can be pointed out from the plots the BTM is far more realistic than theRL-TL model. It is also 10-50 times FASTER (sim time under 1sec).
Conclusions The used setup is effective for a 1.83m long cable characterization The TDR incident pulse risetime (22ps) is fast enough to achieve good waveformresolution (80ps risetime at cable’s output) Actual cable shows sensible impedance discontinuities (S11) Actual cable is asymmetrical Theoretical cable delay is slightly overestimated RL-TL model gives good S11 estimate (without discontinuities) S21 edge risetime agreement is good (70-80ps) Dielectric losses have to be added to achieve better S21 waveform match (edgefoot too fast in the sim model) Skin effect losses are probably over-estimated (upper S21 edge too slow) EYE CLOSURE and ISI JITTER (5-10Gbit/sec) slightly higher in the measure due todielectric losses not taken into account in the model DWS is very effective in terms of accuracy and sim times (50X faster than MC10) BTM S-parameters modeling supported by DWS can take into account effects likedistributed discontinuities and asymmetricity of actual cable with a further speed-up factor of 10X to 50X (more than 3 orders of magnitude faster than MC10)24
25 Piero Belforte, Spartaco Caniggia, “CST coaxialcable models for SI simulations: a comparative study”,March 24th 2013 P. Belforte, S. Caniggia,, “Measurements andSimulations with1.83-m RG58 cable”, April 5th 2013