Designing a basic computer

1. K.HARIPRITHA
M.Sc[InfoTech]
Nadar Saraswathi college of arts and
science.Theni

2. Design of basic computer
Instruction code
Computer Register
Control Logic Gates
Instruction set completeness
Memory Reference instruction
Interrupt Initiated Input Output
Program controll Input Output

3. Hardware components of basic computer:
*A memory unit with 4096 words of 16 bits
each.
*Nine registers: AR,PC,DR,AC,IR,TR,
OUTR,INPR and SC.
*Seven flipflop: I,S,E,R,IEN,FGIandFGO.
*Two Decoder :3*8 operation decoder 4*16 timing
decoder.
*16 bit common bus.
*Control logic gates.
*Adder and logic circuits connected to the input of
AC.

4. •Program: A set of instructions that specify the operations,
operands, and the sequence by which processing has to occur.
•Instruction Code: A group of bits that tell the computer to
perform a specific operation ->macro-operation - usually
divided into operation code, operand address, addressing mode,
etc. - basic addressing modes Immediate, Direct, Indirect
• Simplest stored program organization.
opcode Address
15 12
11
0
Instructions (program)
Operands (data)
Memory 4096x16
Processor register
(Accumulator, AC)Binary Operand
15
0

5.  A processor register (CPU register) is one of a small set
of data holding places that are part of the computer
processor.
 A register may hold an instruction, a storage address,
or any kind of data (such as a bit sequence or individual
characters).
 Some instructions specify registers as part of the
instruction.

6. PC
AR
11
0
11 0
TR
IR
15
0
11 0
INPROUTR
7 0 7
0
Memory
4096 x 16
PC
DR
15
0
15
0
Register in basic
computer

7. DR 16 Data Register Holds
memory operand AR 12 Address Register
Holds address for memory AC 16 Accumulator
Processor register IR 16 Instruction
Register Holds instruction code PC
12 Program Counter Holds address of
instruction TR 16 Temporary Register
Holds temporary data INPR 8 Input Register
Holds input character OUTR 8 Output Register
Holds output character
•Some instructions specify registers as part
of the instruction.

8. Power on reset
circuit
Clock
Input device
R
CLK
INPR
16-bit
Processor
Common
bus
RD
WR
OUTR
DB
AB
RD
WR
4K*16
memory
Output device

9.  The input circuit from the two decoder the I
flip flop and bits 0 through 11 of IR .
 The other input to the control logic are:
AC bits 0 through 15 to check if AC=0
and to detect the sign bit in AC(15)
DR bits 0 through 15 to check if DR=0.

10. Control logic circuit:
 Signals to control inputs of the nine register.
 Signals to control read and write inputs
memory.
 Signals to set clear or complement flipflop.
 Signals for s2,s1 and s0 to be selected
register for a bus.
 Signals to control the AC adder and logic
circuit.

11. AND
ADD
LDA
STA
BUN
BSA
ISZ
0xxx 8xxx
2xxx Axxx
1xxx 9xxx
3xxx Bxxx
4xxx Cxxx
5xxx Dxxx
6xxx Exxx
Add memory word to
A Load AC from
memory
A Store content of AC
into memory
AND memory word to
AC
Branch
unconditionally
Branch and save
return address
Increment and skip if
zer
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
7800
7400
7200
7100
7080
7040
7020
7010
Clear AC
Clear E
Complement AC
Complement E
Circulate right AC and
E
Circulate left AC and E
Increment AC
Skip next instr. if AC

12.  A computer should have a set of instructions so that the user can construct
machine language programs to evaluate any function that is known to be
computable.
Instruction cycle:
Functional Instructions :
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory and the processor registers
- - LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ Input/Output
Instructions
- Input and output - INP, OUT

13.  An instruction that has one or more of its operand
addresses referring to a location in memory, as opposed
to one of the CPU registers or some other way of
specifying an operand. Such as
LDA,STA,BUN,ISZ,ADD,AND,BSA.

14. LDA: Load to AC
D2T4 : DR ¬ M[AR]
D2T5 : AC ¬ DR, SC ¬ 0
STA: Store AC
D3T4 : M[AR] ¬ AC, SC ¬ 0
BUN: Branch Unconditionally
D4T4 : PC ¬ AR, SC ¬ 0
BSA: Branch and Save Return Address
M[AR] ¬ PC, PC ¬ AR + 1
BSA:
D5T4: M[AR] ¬ PC, AR ¬ AR + 1
D5T5: PC ¬ AR, SC ¬ 0
ISZ: Increment and Skip-if-Zero
D6T4: DR ¬ M[AR] D6T5: DR ¬ DR + 1
D6T6: M[AR] ¬ DR, if (DR = 0) then (PC ¬ PC + 1), SC ¬ 0

15.  Open communication only when some data has to be passed
--> interrupt.
 - The I/O interface, instead of the CPU, monitors the I/O
device.
 - When the interface finds that the I/O device is ready for
data transfer, it generates an interrupt request to the CPU
 - Upon detecting an interrupt, the CPU stops momentarily
the task it is doing, branches to the service routine to
process the data transfer, and then returns to the task it was
performing.
* IEN (Interrupt-enable flip-flop)
 - can be set and cleared by instructions - when cleared, the
computer cannot be interrupted

16.  Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
I/O and Interrupt
Input
LOOP, SKI DEV
BUN LOOP
INP DEV
Output LOOP,
LD DATA LOP,
SKO DEV BUN
LOP OUT DEV

17. Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC FlipFlops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates
Adder and Logic circuit: Connected to AC
Control Logic Gates –
-Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit

18. THANK YOU