HDLs are standard text-based expressions of the structure of electronic systems and their behaviour over time. Like concurrent programming languages, HDL syntax and semantics include explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware.

1. VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603203.
Department Of Electronics and Communication Engineering
VALUE ADDED COURSE
On
HDL programming using EDA tools
Design of Combinational circuits in VHDL
Dr. Usha Bhanu.N,
Associate Professor, Department of ECE
12/29/2023 VAC VEC

2. Content of the Course
• Constructs in VHDL
• Loop Structure in VHDL
• Design of combinational circuits
• Logic gates
• Multiplexer
• Priority Encoder
• Half adder and Full adder
• Data Flip Flops
12/29/2023 VAC VEC

3. VLSI 3
If-Then Statement
Format
IF <condition1> THEN
{ sequence of statements}
ELSIF<condition2> THEN
{sequence of statements}
.
.
ELSE
{sequence f statements}
END IF;

4. VLSI 4
Example
PROCESS(sela,selb,a,b)
BEGIN
IF (sela = ‘1’ ) THEN
q <= a;
ELSIF selb =‘1’ THEN
q <= b;
ELSE
q <= c;
END IF;
END PROCESS;
C
B
SELB
A
Q
SELA

5. VLSI 5
If-Then Statements
 Conditions are evaluated in order from top to bottom
–Prioritization.
 First condition if true causes the corresponding
sequence of statements to be executed.
 If all conditions are false, then the sequence of
statements associated with the “ELSE” clause is
evaluated.

6. VLSI 6
Case Statement
 Conditions are evaluated at once –No
prioritization.
 All possible conditions must be considered.
 WHEN OTHERS clause evaluates all other
possible conditions that are not specifically
stated.

7. VLSI 7
Case statement
CASE expression IS
WHEN <condition1> =>
{ sequence of statements}
WHEN <condition2> =>
{ sequence of statements}
.
.
WHEN OTHERS => -- optional
{ sequence of statements}
END CASE;

8. VLSI 8
Example
PROCESS(sel,a,b,c,d)
BEGIN
CASE sel is
when “00” =>
q <= a;
when “01”=>
q <= b;
when “10” =>
q <= c;
when others =>
q <= d;
End Case;
End Process;
a
SEL
b
c
d
2
q

9. VLSI 9
Sequential LOOPS
 Infinite Loop
- Loops infinitely unless EXIT
statement exists.
 While Loop
- Conditional test to end loop.
 FOR Loop
- Iteration Loop.

10. VLSI 10
Infinite Loop
[loop_label}LOOP
--sequential statement
EXIT loop_label;
END LOOP;
loop
wait for 50 ns ;
clk_i <= not (clk_ i) ;
end loop ;

11. VLSI 11
While Loop
WHILE <condition> LOOP
--sequential statements
END LOOP;
while_loop : while true loop
wait for 50 ns ;
clk_i <= not (clk_ i) ;
end loop while_loop ;

12. VLSI 12
For Loop
FOR <identifier> IN <range> LOOP
--sequential statements
END LOOP;

13. VLSI 13
FOR LOOP using a variable : 4 bit Left
shifter
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity shift4 is
port( shft_lft : in std_logic;
d_in : in std_logic_vector(3 downto 0);
q_out : out std_logic_vector(7 downto 0));
End shift4;

14. VLSI 14
Architecture logic of shift4 is
Begin
Process(d_in,shft_lft)
Variable shft_var : std_logic_vector(7 downto 0);
Begin
shft_var(7 downto 4) := “0000”;
shft_var(3 downto 0) := d_in;
If shft_lft = ‘1’ then
for i in 7 downto 4 loop
shft_var(i) := shft_var(i – 4);
End loop;
Enables shift left
I is the index for the
for loop and does not
need to be declared
Shifts left by 4

15. VLSI 15
shft_var(3 downto 0) := “0000”;
Else
shft_var := shft_var;
End if;
q_out <= shft_var;
End process;
End logic;
Fills the LSBS with Zeros

16. VLSI 16
Variable Assignment Statement
Immediate Assignment
 target_variable := expression ;
 Always executed in ZERO SIMULATION TIME
 Used as temporary storages
 Can not be seen by other concurrent statements

17. VLSI 17
Signal Assignment Statement
 Defines a DRIVER of the Signal.
 target_signal <= [ transport ] expression [ after
time_expression ] ;

18. VLSI 18
An example of a two-input XNOR gate
is shown below.
entity XNOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XNOR2;

19. VLSI 19
architecture behavioral_xnor of XNOR2 is
-- signal declaration (of internal signals X, Y)
signal X, Y: std_logic;
begin
X <= A and B;
Y <= (not A) and (not B);
Z <= X or Y;
End behavioral_xnor;

20. VLSI 20
library ieee;
use ieee.std_logic_1164.all;
entity HA is
port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end entity;
architecture HA of HA is
begin
sum <= a xor b;
carry <= a and b;
end architecture;
Half adder Program in Behavioral Modelling

21. VHDL code for DFF
library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port (data, clk : in std_logic;
q : out std_logic);
end dff;
architecture behav of dff is
begin
process (clk) begin
if (clk'event and clk = '1') then
q <= data;
end if;
end process;
12/29/2023 VAC VEC

22. Priority Encoder Using an If-Then-Else
Statement
• An if-then-else statement is used to conditionally execute sequential
statements based on a value. Each condition of the if-then-else statement
is checked in order against that value until a true condition is found.
• Statements associated with the true condition are then executed and the
rest of the statement is ignored. If-then-else statements should be used to
imply priority on a late arriving signal. In the following examples, shown
• in Figure , signal c is a late arriving signal.
12/29/2023 VAC VEC

23. 12/29/2023 VAC VEC

24. 12/29/2023 VAC VEC

25. Multiplexers using case Statement
12/29/2023 VAC VEC