Bottom termination components (BTCs) are everywhere. Despite the fact that these package types have been around since the mid ‘90s and have penetrated into almost every product market, companies still struggle to achieve the high yields the packages promise. This presentation highlights the biggest mistakes and best practices to help conquer the BTC DEMInS: Design, Environment, Manufacturing, Inspection, and Stress.

1. BTC: Bottom Termination Component or Biggest Technical Challenge?
Cheryl Tulkoff, ctulkoff@dfrsolutions.com
Greg Caswell, gcaswell@dfrsolutions.com
DfR Solutions
SMTAI Sept 30-Oct 3 2014
Rosemont, Il
1

2. Abstract
Bottom termination components (BTCs) are everywhere.
Despite the fact that these package types have been around since the mid ‘90s and have penetrated into almost every product market, companies still struggle to achieve the high yields the packages promise.
This presentation highlights the biggest mistakes and best practices to help conquer the BTC DEMInS: Design, Environment, Manufacturing, Inspection, and Stress.
2

3. BTC Advantages: Size and Cost
Smaller, lighter and thinner than comparable leaded packages
Allows for greater functionality per volume
Reduces cost
Component manufacturers: More ICs per frame
OEMs: Reduced board size
Attempts to limit the footprint of lower I/O devices have previously been stymied for cost reasons
BGA materials and process too expensive
3

4. Major Growth in BTC Packaging
4

5. Manufacturer
BTC Name Used
Amkor
MLF: MicroLeadFrame
Fujitsu
SON: Small outline no leads; BCC: Bumped Chip Carrier
Carsem
MLP: MicroLeadframe Package
ASE
MCC: MicroChipCarrier
So Many Names!
Increasing in complexity, functionality & size!
QFN with Stacked Die, UniSem
5

6. BTC DEMInS Defined
Design: Using outdated pad, via, and solder mask practices
Environment: Ignoring flux residues and cleanliness challenges
Manufacturing: Running non-optimized stencils and reflow profiles
Inspection & Rework: Missing the best techniques for monitoring and avoiding failures
Stress: Overlooking flexure, coating, potting, and thermal cycling challenges
6

7. Design Guidelines
IPC-7093 Design and Assembly Process Implementation for Bottom Termination SMT Components
Difficult to keep up to date
Component Manufacturers
Don’t specialize in mfg
DfM Practices & Rules of Thumb
7

8. BTC Use Environment Challenges
Low or no standoff parts especially vulnerable to cleanliness and environment problems
Difficult to clean under
Short paths from lead to lead or lead to via
Power & ground in close proximity
Increased electrical field strength
Can result in leakage resistance, shorts, corrosion, electrochemical migration (ECM), dendritic growth
8

9. BTCs, ECM & Dendritic Growth
Large area, multi-I/O and low standoff can trap flux under BTCs
Processes should be requalified
Particular configurations could result in weak organic acid concentrations above maximum (150 – 200 ug/in2) for no cleans
Processes not using no-clean flux may experience dendritic growth unless cleaning process is updated
Changes in water temperature
Changes in saponifier
Changes to impingement jets
9

10. Design & Standoff Height
Pad geometry influences standoff height
Thermal via count, spacing, and fill impact both residues & standoff height
NSMD & SMD Pad Geometries
Solder "drain" through Unfilled Vias
TI
10

11. 11
BTC Bond Pad Design
Non Solder Mask Defined Pads Preferred (NSMD)
Copper etch process has tighter process control than solder mask process
Makes for more consistent, strong solder joints since solder bonds to both tops and sides of pads
Use solder mask defined pads (SMD) with care
Can be used to avoid bridging between pads, especially between thermal and signal pads.
Pads can significantly grow in size based on PCB manufacturer capabilities
NSMD
Images courtesy of Screaming Circuits

12. Pad Design & Residue Impact
Kyzen experiment
Varied standoff height & solder mask
No solder mask significantly improves cleanability
SMD pads performed worst
“QFN DESIGN CONSIDERATIONS TO IMPROVE CLEANING”, SMTAI 2013, Fort Worth, TX.
12
SMD
NoSM

13. Pad Design & Residue Impact
Ground Pad Design
Solder Mask Definition
# of Thermal Pad Vias
Standoff Height
Standard
No Solder Mask
25
3 mils
Square
Non Solder Mask
9
4 mils
Slot
None
Hexagon
Joint Experiment
Cleanability was assessed against factors in table below
# Vias impact standoff height
Standoff < 2mils resulted in heavy residues
Bixenman, Mike et al, “QFN DESIGN CONSIDERATIONS TO IMPROVE CLEANING”, SMTAI 2013, Fort Worth, TX.
13

14. Design Impacts Cleanability
MLF124 Dual Row MLF88 Singe Row
0.45
0.40
0.35
0.30
0.25
HEXAGON SLOT SQUARE STANDARD
NoSM NSMD
0.45
0.40
0.35
0.30
0.25
0 9 25
Component
Flux Residue Means
Ground Plane Pattern
Solder Mask Definition Via Holes
Main Effects Plot for Flux Residue Bridging Pads
Data Means
14 Bixenman, Mike et al, “QFN DESIGN CONSIDERATIONS TO IMPROVE CLEANING”, SMTAI 2013, Fort
Worth, TX.

15. BTCs & Voids
Voids in thermal pads have been a challenge
Reduce thermal transfer
Indium study showed via count & stencil design had significant impact on void formation
Jensen, Tim, “SOLUTIONS FOR HIP AND QFN VOIDING CHALLENGES”, SMTA Expo DFW March 2013
15

16. BTC Stencil Design
 Stencil thickness and aperture design is critical
 Excessive amount of paste can induce
float, lifting the BTC off the board
 Excessive voiding can also be induced
through inappropriate stencil design
 Follow manufacturer’s guidelines
 Goal is 2-3 mils of solder thickness
 Rules of thumb (thermal pad)
 Ratio of aperture/pad ~0.5:1
 Consider multiple, smaller apertures
(avoid large bricks of solder paste)
 Reduces propensity for solder balling
16

17. BTC Thermal Pad Stencil Design
BTC Thermal Aperture Designs
Ahmer Syed and WonJoon Kang, “Board level assembly and reliability considerations for QFN type packages”, SMTA International 2003.
17

18. Optimizing Stencil Design
18

19. BTC Rework
Can be difficult to replace a package and get adequate soldering of thermal / internal pads.
Mini-stencils, preforms, or rebump techniques can be used to get sufficient solder volume
Not directly accessible with soldering iron and wire
Portable preheaters used in conjunction with soldering iron can simplify small scale repair processes
Close proximity with capacitors often requires adjacent components to be resoldered / replaced as well
19

20. BTC Removal & Replacement
Automated repair equipment
Center thermal pad & multi row are challenging
Must provide paste or flux to site
Microstencils
Microsqueeges
20

21. 21
BTC Inspection
Extend bond pad 0.2 – 0.3 mm beyond package footprint
May or may not solder to cut edge
Allows for better visual inspection
Need X-ray for best results
Allows for verification of bridging, adequate solder coverage and void percentage
Cannot detect head in pillow or fractures

22. 22
BTC Joint Inspection
Goal is 2-3 mils of post-reflow solder thickness

23. 23
BTC Joint Inspection
•Convex or absence of fillet highly likely
•Edge of bond pad is not plated for solderability

24. BTC Side Fillets: MacDermid
Most BTCs have no side fillets
MacDermid process plates the flank
Improved inspectability
Potential reliability improvement
Toscano, Lenora et al, “A PROCESS FOR IMPROVED QFN RELIABILITY”, SMTA 2013, Fort Worth, TX.
24

25. BTC Flexure
Area array devices are known to have board flexure limitations
For SAC attachment, maximum microstrain can be as low as 500 ue
BTCs have an even lower level of compliance
Limited quantifiable knowledge in this area
Must be conservative during board build
IPC is working on a specification similar to BGAs
25

26. Excessive flexure can occur at multiple points in assembly
Mechanical Shock Events
26

27. BTCs & Bend Cycling
 Low degree of compliance
and large footprint can
also result in issues during
cyclic flexure events
 Example: IR tested a
5 x 6mm QFN to
JEDEC JESD22-B113
 Very low beta (~1)
 Suggests brittle fracture, possible along the interface
27

28. Thermal Cycling & Conformal
Coating on BTCs
 Care must be taken when using conformal coating over
QFN
 Coating can infiltrate under the QFN
 Small standoff height allows coating to cause lift
 Hamilton Sundstrand found a significant reduction in time
to failure (-55 / 125C)
 Uncoated: 2000 to 2500 cycles
 Coated: 300 to 700 cycles
 Also driven by solder joint
sensitivity to tensile stresses
 Damage evolution is far
higher than for shear stresses
Wrightson, SMTA Pan Pac 2007 28

29. QFN Warpage & Potting
Unpotted
Potted
Order of magnitude higher deformation and deformation concentrated over corner solder joints
29

30. Exorcise the BTC DEMInS!
BTC can be implemented reliably in products if DEMInS are respected!
30

31. Conclusions
Design
Select components where power & ground pins are not in close proximity
Limit the number of vias & fill them
Work with manufacturing to optimize pad and solder mask geometry
Environment
Carefully select & qualify soldering materials
Monitor the amount of flux residues & cleanliness under BTCs
31

32. Conclusions
Manufacturing
Optimize stencils to achieve 2-3 mils of standoff height and to allow for flux outgassing
Inspection & Rework
Extend outer bond pads to improve visual inspection
Use X-ray to inspect
Provide adequate spacing for repair & between BTCs & thermally sensitive components
Stress
Minimize flexure
Choose coatings, pottings, and underfills using CTE, Tg, and Modulus
Know the tradeoffs between thermal cycling & shock performance
32

33. Presenter Biography
Cheryl has over 22 years of experience in electronics manufacturing focusing on failure analysis and reliability. She is passionate about applying her unique background to enable her clients to maximize and accelerate product design and development while saving time, managing resources, and improving customer satisfaction.
Throughout her career, Cheryl has had extensive training experience and is a published author and a senior member of both ASQ and IEEE. She views teaching as a two-way process that enables her to impart her knowledge on to others as well as reinforce her own understanding and ability to explain complex concepts through student interaction. A passionate advocate of continued learning, Cheryl has taught electronics workshops that introduced her to numerous fascinating companies, people, and cultures.
Cheryl has served as chairman of the IEEE Central Texas Women in Engineering and IEEE Accelerated Stress Testing and Reliability sections and is an ASQ Certified Reliability Engineer, an SMTA Speaker of Distinction and serves on ASQ, IPC and iNEMI committees.
Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech and is currently a student in the UT Austin Masters of Science in Technology Commercialization (MSTC) program. She was drawn to the MSTC program as an avenue that will allow her to acquire relevant and current business skills which, combined with her technical background, will serve as a springboard enabling her clients to succeed in introducing reliable, blockbuster products tailored to the best market segment.
In her free time, Cheryl loves to run! She’s had the good fortune to run everything from 5k’s to 100 milers including the Boston Marathon, the Tahoe Triple (three marathons in 3 days) and the nonstop Rocky Raccoon 100 miler. She also enjoys travel and has visited 46 US states and over 20 countries around the world. Cheryl combines these two passions in what she calls “running tourism” which lets her quickly get her bearings and see the sights in new places.
33