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Gemma Bluetooth ® Module
CSR8640/CSR8645 Class2 Stereo ROM Module
BSM-640/645
Features
















Outl...
General Electrical Specification
Absolute Maximum Ratings:
Ratings

Min.

Max.

Storage Temperature

-40 ℃

+85 ℃

Supply ...
Regulator Enable
VREG_ENABLE, Switching Threshold

Min

Typ

Max

Unit

Rising threshold

1.0

-

-

V

Min

Typ

Max

Uni...
Resolution
Input Sample Rate,
Fsample

-

-

-

16

Bits

-

8

-

48

kHz

fin = 1kHz
B/W = 20Hz→Fsample/2
SNR

Fsample
8...
Analogue Gain

Analogue Gain Resolution = 3dB

-21

0

dB

-

Stereo separation (crosstalk)

-88

-

dB

Digital
Digital T...
Input bandwidth

-

100

-

kHz

Conversion time

1.38

1.69

2.75

μs

-

-

700

Samples/s

Sample rate(b)
(a) LSB size ...
Stereo high quality:
Slave

■ MP3

TBD

TBD

TBD

mA

TBD

■ 128kbps

TBD

TBD

mA

■ No sniff
Stereo high quality:
Slave
...
Block Diagram

RF Specification:

Temperature=+20℃

Transmitter
Min

Typ

Max

Bluetooth

Unit

Specification
Maximum RF t...
Δf2max Minimum Modulation

-

TBD

-

115

Δf1avg/Δf2avg

-

TBD

-

≥0.80

Initial carrier frequency tolerance

-

TBD

-...
BTM-640/645 Pin Functions
No.

Pin Name

Pin Type

Supply Domain

1

SPKR_R_N

Analogue

2

SPKR_R_P

Analogue

3

SPKR_L_...


SPI_CLK:SPI clock



PCM1_CLK: PCM1
synchronous data clock

Bi-directional

PIO_POWER

Programmable input/output line
...
right
45.

MIC_BP

Analogue

VDD_AUDIO(1.35V)

Microphone input positive, right

46.

MIC_AN

Analogue

VDD_AUDIO(1.35V)

...
1. Serial Interface
1.1 USB Interface
BTM-640/650 has a full-speed (12Mbps) USB interface for communicating with other com...
BTM-640/645 has 1 general-purpose analogue interface pin, AIO[0]. Typically, this connects to a thermistor for
battery pac...
then latches the regulators on, it is then permitted to release the voltage regulator enable pin.
The status of the VREGEN...
4. Battery Charger
4.1 Battery Charger hardware Operating Modes
The battery charger hardware is controlled by the VM. The ...
Figure 4.2.2: Optional Ancilliary Circuits
In Figure 4.2.2, Optional fast charge,400mΩ = 500m. Connect VBAT_SENSE to VBAT ...
Dimension
3

SW4
PIO20

R7 1K0

1

0R

C2

C4

0.1u

U1
XC6209F332MRN
Vout 5
Vin

1V8_SMPS 3
C6

C5

10uF

SP1

SW5

CE

4

BTP

3V3...
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Bsm640 bsm645 data sheet v 02

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Gemma Technology Inc. (Taiwan)
With the Bluetooth SIG Association to promote Bluetooth Technology in the world, Nowadays, Bluetooth stereo has generally been in the PC, mobile phones and a variety of handheld devices as a standard transmission interface of the wireless source.
So from 2007, Company began to transfer from traditional multimedia speaker maker to Bluetooth multimedia speaker; we expect to create a more convenient wireless applications, hope that consumers can enjoy the rich sound at an affordable price.
We, Gemma Inc hired R&D members specialized in developing and manufacturing wireless Bluetooth devices and integrated with our acoustic experts to come out high audio output speakers. We are innovative Bluetooth stereo speaker provider in this field, and keep on offering better products and Bluetooth solutions.

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Bsm640 bsm645 data sheet v 02

  1. 1. Gemma Bluetooth ® Module CSR8640/CSR8645 Class2 Stereo ROM Module BSM-640/645 Features                Outline The module is a Max.4dBm( Class2 ) module. Fully Qualified Bluetooth v4.0. Integrated Switched-Mode Regulator. Integrated Battery Charger. Embedded Kalimba DSP Co-Processor. Integrated 16-bit Stereo Audio CODEC 93dB SNR for DAC. CSR’s latest CVC technology for narrowband and wideband voice connections including wind noise reduction. Wideband speech supported by HFP v1.6 Profile and mSBC codec. Multipoint HFP connection to 2 phones for voice. Multipoint A2DP connection enables a headset(A2DP) connection to 2 A2DP source device for music playback. SBC, MP3, AAC, Faststream(BTM640), APTX(BTM645) decoder support. HSP v1.2/ HFP v1.6/ A2DP v1.2/ AVRCP v1.4 Voice prompts (SPI Flash) RoHS compliant. Small outline. 13.4 x13.4 x2.7mm(8M SPI Flash) 13.4 x13.4 x1.9mm(64K EEPROM) Applications    Stereo Wireless Headsets. Wired stereo headsets and headphones. Portable stereo speakers. V02 2012.09.27
  2. 2. General Electrical Specification Absolute Maximum Ratings: Ratings Min. Max. Storage Temperature -40 ℃ +85 ℃ Supply Voltage (VCHG) -0.4V 5.75V Supply Voltage (VREG_ENABLE,VBAT_SENSE) -0.4V 4.2V Supply Voltage (LED[2:0]) -0.4V 4.4V Supply Voltage (PIO_POWER) -0.4V 3.6V Operating Temperature range -20 ℃ +75 ℃ Supply Voltage (VBAT) 2.7V 4.25V Supply Voltage (VCHG) 4.75V / 3.10 V 5.25V Supply Voltage (VREG_ENABLE,VBAT_SENSE) 0V 4.2V Supply Voltage (LED[2:0]) 1.10V 4.25V Supply Voltage (PIO_POWER)* 1.7V 3.6V Recommended Operating Condition: Operating Condition 1.8V Switch-mode Regulator 1.8V Switch-mode Regulator Min Typ Max Unit Input voltage (VBAT) 2.70 3.70 4.25 V Output voltage (1V8_SMPS) 1.70 1.80 1.90 V Transient settling time - 30 - μs Load current - - 185 mA - - 25 mA - 90 - % 3.63 4.00 4.00 MHz - 200 - μs 0.005 - 5 mA Current available for external use - - 5 mA Peak conversion efficiency - 85 - % 100 - 200 kHz Normal Operation Current available for external use, stereo audio with 16Ω load Peak conversion efficiency Switching frequency (a) Low-power Mode, Automatically Entered in Deep Sleep Transient settling time Load current Switching frequency (a) More current available for audio loads above 16Ω.
  3. 3. Regulator Enable VREG_ENABLE, Switching Threshold Min Typ Max Unit Rising threshold 1.0 - - V Min Typ Max Unit 4.75 / 3.10 5.00 5.25 V Min Typ Max Unit Charge current Itrickle , as percentage of fast charge current 8 10 12 % Vfast rising threshold - 2.9 - V Vfast rising threshold trim step size - 0.1 - V Vfast falling threshold - 2.8 - V Fast Charge Mode Min Typ Max Unit 194 200 206 mA Battery Charger Battery Charger Input voltage, VCHG (a) (a) Reduced specification from 3.1 to 4.75. Full specification > 4.75V. Trickle Charge Mode Charge current during constant Max, headroom > 0.55V Current mode, Ifast Min, headroom > 0.55V Reduced headroom charge current, mA 50 - 100 % - 10 - mA Vfloat threshold, calibrated 4.16 4.20 4.24 V Standby Mode Min Typ Max Unit Voltage hysteresis on VBAT, Vhyst 100 - 150 mV Error Charge Mode Min Typ Max Unit As a percentage of Ifast Mid, headroom=0.15V 10 I-CTRL charge current step size Headroom (a) error rising threshold 30 - 50 mV Headroom (a) error threshold hysteresis 20 - 30 mV External Charge Mode Min Typ Max Unit Fast charge current, Ifast 200 - 500 mA Control current into CHG_EXT 0 - 20 mA Voltage on CHG_EXT 0 5.75 V External pass device hfe - 50 - - 195 200 205 mV (a) Headroom=VCHG-VBAT Sense voltage, between VBAT_SENSE and VBAT at maximum current (a) In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical characteristics are listed in this table. Stereo Codec: Analogue to Digital Converter Analogue to Digital Converter Parameter Conditions Min Typ Max Unit
  4. 4. Resolution Input Sample Rate, Fsample - - - 16 Bits - 8 - 48 kHz fin = 1kHz B/W = 20Hz→Fsample/2 SNR Fsample 8kHz - 92 - dB (20kHz max) 16kHz - 89 - dB A-Weighted 32kHz - 88 - dB 44.1kHz - 88 - dB 48kHz - 88 - dB 8kHz - 0.0036 - % 48kHz - 0.0052 - % -24 - 21.5 dB -3 - 42 dB - -86 - dB Min Typ Max Unit THD+N < 1% 1.6Vpk-pk input fin = 1kHz THD+N Fsample B/W = 20Hz→Fsample/2 (20kHz max) 1.6Vpk-pk input Digital gain Digital gain resolution = 1/32 Pre-amplifier setting = 0dB, 9dB, 21dB Analogue gain or30dB Analogue setting = -3dB to 12dB in 3dB steps Stereo separation (crosstalk) Stereo Codec: Digital to Analogue Converter Digital to Analogue Converter Parameter Conditions Resolution - - - 16 Bits - 8 - 96 kHz Output Sample Rate, Fsample fin = 1kHz Fsample Load 48kHz 100kΩ - 92 - dB 48kHz 32Ω - 93 - dB 48kHz 16Ω - 93 - dB Fsample Load 8kHz 100kΩ - 0.0019 - % fin = 1kHz 8kHz 32Ω - 0.0024 - % B/W = 20Hz→20kHz 8kHz 16Ω - 0.0032 - % 0dBFS input 48kHz 100kΩ - 0.0026 - % 48kHz 32Ω - 0.0036 - % 48kHz 16Ω - 0.0052 - % -24 - 21.5 dB B/W = 20Hz→20kHz SNR A-Weighted THD+N < 0.1% 0dBFS input THD+N Digital Gain Digital Gain Resolution = 1/32
  5. 5. Analogue Gain Analogue Gain Resolution = 3dB -21 0 dB - Stereo separation (crosstalk) -88 - dB Digital Digital Terminals Min Typ Max Unit VIL input logic level low -0.4 - 0.4 V VIH input logic level high 0.7xPIO_POWER - PIO_POWER+0.4 V - - 25 ns - - 0.4 V 0.75xPIO_POWER - - V - - 5 ns -150 -40 -10 uA Strong pull-down 10 40 150 uA Weak pull-up -5 -1.0 -0.33 uA Weak pull-down 0.33 1.0 5.0 uA CI input Capacitance 1.0 5.0 pF Input Voltage Tr/Tf Output Voltage VOL output logic level low, IOL = 4.0mA VIH output logic level high, IOH = -0.4mA Tr/Tf Input and Tristate Currents Strong pull-up LED Driver Pads LED Driver Pads Min Typ Max Unit High impedance state - - 5 μA Current sink state - - 10 mA IPAD = 10mA - - 0.55 V VPAD < 0.5V - - 40 Ω - 0 - V - 0.8 - V VIL input logic level low - 0 - V VIH input logic level high - 0.8 - V Current, IPAD LED pad voltage, VPAD LED pad resistance VOL output logic level low (a) VOH output logic level high (a) (a) LED output port is open-drain and requires a pull-up Auxiliary ADC Auxiliary ADC Min Typ Max Unit Resolution - - 10 Bits Input voltage range(a) 0 - 1.35 V Accuracy INL -1 - 1 LSB (Guaranteed monotonic) DNL 0 - 1 LSB -1 - 1 LSB -0.8 - 0.8 % Offset Gain error
  6. 6. Input bandwidth - 100 - kHz Conversion time 1.38 1.69 2.75 μs - - 700 Samples/s Sample rate(b) (a) LSB size = VDD_AUX/1023 (b) The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function. Auxiliary DAC Min Resolution - Typ Max Unit om Auxiliary DAC 10 Bits 1.35 1.40 V - 1.35 V 1.35 1.40 V 1.32 2.64 mV -1.32 0 1.32 mV -1 0 1 LSB - Supply voltage, VDD_DAC - - 250 ns Average Unit 1.30 Output voltage range 0 Full-scale output voltage 1.30 0 on .c LSB size Offset Integral non-linearity Settling time(a) Power Consumption ys (a) The settling time does not include any capacitive load Connection Slave SCO HV3 30 TBD mA Slave eSCO EV3 30 TBD mA Slave eSCO 2EV3 60 TBD mA Slave eSCO 2EV3 30 TBD mA Slave Packet Type Packet Size Current SCO 2-mic CVC HV3 30 TBD mA eSCO 2-mic CVC 2EV3 60 TBD mA 2-mic CVC 2EV3 30 TBD mA TBD TBD TBD mA TBD TBD TBD mA w w Slave w Slave .ra DUT Role eSCO Stereo high quality: Slave ■ SBC ■ 350kbps ■ No sniff Stereo high quality: Slave ■ SBC ■ 350kbps ■ Sniff
  7. 7. Stereo high quality: Slave ■ MP3 TBD TBD TBD mA TBD ■ 128kbps TBD TBD mA ■ No sniff Stereo high quality: Slave ■ MP3 ■ 128kbps ■ Sniff Slave ACL Sniff = 100ms - - TBD mA Slave ACL Sniff = 500ms - - TBD mA Slave ACL Sniff = 1280ms - - TBD mA Master SCO HV3 30 TBD mA Master eSCO EV3 30 TBD mA Master eSCO 2EV3 60 TBD mA Master eSCO 2EV3 30 TBD mA Master SCO 2-mic CVC HV3 30 TBD mA Master eSCO 2-mic CVC 2EV3 60 TBD mA Master eSCO 2-mic CVC 2EV3 30 TBD mA Master ACL Sniff = 100ms - - TBD mA Master ACL Sniff = 500ms - - TBD mA Master ACL Sniff = 1280ms - - TBD mA Note: Current consumption values are taken with: ■ VBAT pin = 3.7V ■ RF TX power set to 0dBm ■ No RF retransmissions in case of eSCO ■ Microphones and speakers disconnected, with internal microphone bias circuit set to minimum current level ■ Audio gateway transmits silence when SCO/eSCO channel is open ■ LEDs disconnected
  8. 8. Block Diagram RF Specification: Temperature=+20℃ Transmitter Min Typ Max Bluetooth Unit Specification Maximum RF transmit power - TBD - -6 to +4 dBm RF power control range - TBD - ≥16 dB RF power range control resolution - TBD - - dB 20dB bandwidth for modulated carrier - TBD - ≤1000 kHz Adjacent channel transmit power F = F0 ± - TBD - ≤-20 dBm - TBD - ≤-40 dBm - TBD - ≤-40 dBm - TBD - 140<f1avg<175 kHz 2MHz Adjacent channel transmit power F = F0 ± 3MHz Adjacent channel transmit power F = F0 ± > 3MHz Δf1avg Maximum Modulation
  9. 9. Δf2max Minimum Modulation - TBD - 115 Δf1avg/Δf2avg - TBD - ≥0.80 Initial carrier frequency tolerance - TBD - ±75 kHz Drift Rate - TBD - ≤20 kHz/50μ Drift (single slot packet) - TBD - ≤25 kHz Drift (five slot packet) - TBD - ≤40 kHz 2nd Harmonic Content - TBD - ≤-30 dBm 3rd Harmonic Content - TBD - ≤-30 dBm kHz Receiver Freque Min Typ Max Bluetooth ncy Specificatio (GHz) Unit n ≤-70 dBm ≥-20 dBm - ≤11 dB TBD - ≤0 dB - TBD - ≤0 dB - TBD - ≤-20 dB - TBD - ≤-30 dB - TBD - ≤-40 dB - TBD - ≤-40 dB - TBD - ≤-9 dB - TBD - ≥-39 dBm - TBD - Sensitivity at 0.1% BER 2.402 - TBD - for all packet types 2.441 - TBD - 2.480 - TBD - Maximum received signal at 0.1% BER - TBD C/I co-channel - TBD Adjacent channel selectivity C/I - F = F0 + 1MHz Adjacent channel selectivity C/I F = F0 - 1MHz Adjacent channel selectivity C/I F = F0 + 2MHz Adjacent channel selectivity C/I F = F0 - 2MHz Adjacent channel selectivity C/I F = F0 - 3MHz Adjacent channel selectivity C/I F = F0 + 5MHz Adjacent channel selectivity C/I F = FImage Maximum level of intermodulation interferers Spurious output level dBm/ Hz
  10. 10. BTM-640/645 Pin Functions No. Pin Name Pin Type Supply Domain 1 SPKR_R_N Analogue 2 SPKR_R_P Analogue 3 SPKR_L_N Analogue 4 SPKR_L_P Analogue 5 GND GND 6. RF_IO Analogue 7. GND GND Common Ground 8. GND GND Common Ground 9. GND GND Common Ground 10. AIO0 Bi-directional VDD_AUX(1.35V) 11. PIO16 Bi-directional PIO_POWER Programmable input/output line 12. PIO17 Bi-directional PIO_POWER Programmable input/output line 13. RST# Input with strong PIO_POWER Reset if low. Pull low for 14 LED0 15 LED1 VDD_AUDIO_DRV (1V8_SMPS) VDD_AUDIO_DRV (1V8_SMPS) VDD_AUDIO_DRV (1V8_SMPS) VDD_AUDIO_DRV (1V8_SMPS) Speaker output negative, left Speaker output positive, left Signal) Analogue programmable input/output line minimum 5ms to cause a reset PIO_POWER PIO_POWER output Bi-directional Speaker output positive, right Connect to 50 ohm Antenna (RF output Open drain Speaker output negative, right Common Ground pull-up Open drain Pin Description PIO_POWER LED Driver LED Driver Programmable input/output line Altemative functions: 16.  PIO4 SPI_CSB:chip select for SPI, active low  PCM1_SYNC: PCM1 synchronous data sync Bi-directional PIO_POWER Programmable input/output line Altemative functions:  PIO2 SPI_MOSI:SPI data input  17. PCM1_IN: PCM1 synchronous data input 18. PIO5 Bi-directional PIO_POWER Programmable input/output line Altemative functions:
  11. 11.  SPI_CLK:SPI clock  PCM1_CLK: PCM1 synchronous data clock Bi-directional PIO_POWER Programmable input/output line Altemative functions:  PIO3 SPI_MISO:SPI data output  19. PCM1_OUT: PCM1 synchronous data output 20. PIO_POWER VDD Positive supply for PIO 21. VREG_ENABLE Analogue Regulator enable input 22. 23. SPI/PCM# VCHG Input with weak pull-down SPI/PCM# select input: Charger input  0=PCM/PIO interface  PIO_POWER 1=SPI Lithium ion/polymer battery charger input 24. GND 25. CHG_EXT 26. GND Common Ground VBAT_SENSE External charger control. Otherwise leave unconnected. Battery charger sense input Lithium ion/polymer battery 27. VBAT Battery terminal positive terminal. Battery +ve charger output and input to switch-mode regulator 28. 1V8_SMPS VDD 1V8 Output 29. PIO6 Bi-directional PIO_POWER Programmable input/output line 30. PIO7 Bi-directional PIO_POWER Programmable input/output line 31. PIO18 Bi-directional PIO_POWER Programmable input/output line 32. PIO19 Bi-directional PIO_POWER Programmable input/output line 33. PIO21 Bi-directional PIO_POWER Programmable input/output line 34. PIO20 Bi-directional PIO_POWER Programmable input/output line 35. PIO9 Bi-directional PIO_POWER Programmable input/output line 36. GND GND 37. PIO0 Bi-directional PIO_POWER Programmable input/output line 38. PIO1 Bi-directional PIO_POWER Programmable input/output line 39. PIO8 Bi-directional PIO_POWER Programmable input/output line 40. USB_DN Bi-directional 3V3_USB USB data minus 41. USB_DP Bi-directional 3V3_USB USB data plus 42. LED2 Open drain PIO_POWER 43 MIC_BIAS Analogue VBAT/3V3_USB Microphone bias 44. MIC_BN Analogue VDD_AUDIO(1.35V) Microphone input negative, Common Ground output LED Driver
  12. 12. right 45. MIC_BP Analogue VDD_AUDIO(1.35V) Microphone input positive, right 46. MIC_AN Analogue VDD_AUDIO(1.35V) Microphone input negative, left 47. MIC_AP Analogue VDD_AUDIO(1.35V) Microphone input positive, left 48. GND GND Common Ground
  13. 13. 1. Serial Interface 1.1 USB Interface BTM-640/650 has a full-speed (12Mbps) USB interface for communicating with other compatible digital devices. The USB interface on BTM-640/645 acts as a USB peripheral, responding to requests from a master host controller. BTM-640/645 contains internal USB termination resistors and requires no external resistor matching. BTM-640/645 supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification), supports USB standard charger detection and fully supports the USB Battery Charging Specification , available from http://www.usb.org. For more information on how to integrate the USB interface on BTM-640/645 see the Bluetooth and USB Design Considerations Application Note. As well as describing USB basics and architecture, the application note describes: ■ Power distribution for high and low bus-powered configurations ■ Power distribution for self-powered configuration, which includes USB VBUS monitoring ■ USB enumeration ■ Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of ferrite beads ■ USB suspend modes and Bluetooth low-power modes: ■ Global suspend ■ Selective suspend, includes remote wake ■ Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend ■ Suspend mode current draw ■ PIO status in suspend mode ■ Resume, detach and wake PIOs ■ Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend modes and USB VBUS voltage consideration ■ USB termination when interface is not in use ■ Internal modules, certification and non-specification compliant operation 1.2 Programming and Debug Interface BTM-640/645 provides a debug SPI interface for programming, configuring (PS Keys) and debugging the BTM640/645. Access to this interface is required in production. Ensure the 4 SPI signals and the SPI/PCM# line are brought out to either test points or a header. To use the SPI interface, the SPI/PCM# line requires the option of being pulled high externally. 1.2.1 Multi-slave Operation Avoid connecting BTM-640/645 in a multi-slave arrangement by simple parallel connection of slave MISO lines. When BTM640/645 is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, BTM-640/645 outputs 0 if the processor is running or 1 if it is stopped. 2. interfaces 2.1 Analogue I/O Ports, AIO
  14. 14. BTM-640/645 has 1 general-purpose analogue interface pin, AIO[0]. Typically, this connects to a thermistor for battery pack temperature measurements during charge control. 2.2 LED Drivers BTM-640/645 includes a 3-pad synchronised PWM LED driver for driving RGB LEDs for producing a wide range of colours. All LEDs are controlled by firmware. The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series with a current-limiting resistor. Figure 2.1: LED Equivalent Circuit From Figure 2.1 it is possible to derive Equation 2.1 to calculate ILED. If a known value of current is required through the LED to give a specific luminous intensity, then the value of RLED is calculated. Equation 2.1: LED Current For the LED pads to act as resistance, the external series resistor, RLED, needs to be such that the voltage drop across it, VR, keeps VPAD below 0.5V. Equation 2.2 also applies. VDD = VF + VR + VPAD Equation 2.2: LED PAD Voltage Note: The LED current adds to the overall current. Conservative LED selection extends battery life. 3. Power Control and Regulation 3.1 Voltage Regulator Enable When using the integrated regulators the voltage regulator enable pin, VREG_ENABLE, enables the BTM-640/645 and the following regulators: ■ 1.8V switch-mode regulator ■ 1.35V switch-mode regulator ■ Low-voltage VDD_DIG linear regulator ■ Low-voltage VDD_AUX linear regulator The VREG_ENABLE pin is active high. BTM-640/645 boots-up when the voltage regulator enable pin is pulled high, enabling the regulators. The firmware
  15. 15. then latches the regulators on, it is then permitted to release the voltage regulator enable pin. The status of the VREGENABLE pin is available to firmware through an internal connection. VREGENABLE also works as an input line. 3.2 Reset, RST# BTM-640/645 is reset from several sources: ■ RST# pin ■ Power-on reset ■ USB charger attach reset ■ Software configured watchdog timer The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. Rayson recommends applying RST# for a period >5ms. At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate. 3.3 Digital Pin States on Reset Table 3.3.1 shows the pin states of BTM-640/645 on reset. Pin Name / Group I/O Type Full Chip Reset USB_DP Digital bidirectional N/A USB_DN Digital bidirectional N/A PIO[0] Digital bidirectional PUS PIO[1] Digital bidirectional PUS PIO[2] Digital bidirectional PDW PIO[3] Digital bidirectional PDW PIO[4] Digital bidirectional PDW PIO[5] Digital bidirectional PDW PIO[6] Digital bidirectional PDS PIO[7] Digital bidirectional PDS PIO[8] Digital bidirectional PUS PIO[9] Digital bidirectional PDS PIO[16] Digital bidirectional PUS PIO[17] Digital bidirectional PDS PIO[18] Digital bidirectional PDW PIO[19] Digital bidirectional PDW PIO[20] Digital bidirectional PDW PIO[21] Digital bidirectional PDW Table 3.3.1: Pin States on Reset Note: PUS = Strong pull-up PDS = Strong pull-down PUW = Weak pull-up PDW = Weak pull-down
  16. 16. 4. Battery Charger 4.1 Battery Charger hardware Operating Modes The battery charger hardware is controlled by the VM. The battery charger has 5 modes: ■ Disabled ■ Trickle charge ■ Fast charge ■ Standby: fully charged or float charge ■ Error: charging input voltage, VCHG, is too low The battery charger operating mode is determined by the battery voltage and current. The internal charger circuit can provide up to 200mA of charge current, for currents higher than this the BTM640/BTM645 can control an external pass transistor 4.2 External Mode The external mode is for charging higher capacity batteries using an external pass device. The current is controlled by sinking a varying current into the CHG_EXT pin, and the current is determined by measuring the voltage drop across a resistor, Rsense, connected in series with the external pass device, see Figure 4.2.1. The voltage drop is determined by looking at the difference between the VBAT_SENSE and VBAT pins. The voltage drop across Rsense is typically 200mV. The value of the external series resistor determines the charger current. This current can be trimmed with a PS Key. In Figure 4.2.1, R1 (220mΩ) and C1 (4.7μF) form a RC snubber that is required to maintain stability across all battery ESRs. The battery ESR must be <1.0Ω Figure 4.2.1: Battery Charger External Mode Typical Configuration
  17. 17. Figure 4.2.2: Optional Ancilliary Circuits In Figure 4.2.2, Optional fast charge,400mΩ = 500m. Connect VBAT_SENSE to VBAT if not using this circuit.
  18. 18. Dimension
  19. 19. 3 SW4 PIO20 R7 1K0 1 0R C2 C4 0.1u U1 XC6209F332MRN Vout 5 Vin 1V8_SMPS 3 C6 C5 10uF SP1 SW5 CE 4 BTP 3V3 VBAT R3 0805 package Q1 C3 C7 VBUS 1u0 0.1u 1u0 VOLAMP_GND VBAT C9 2u2 LUMBURG 3 2 1 BSM640_BSM645 R10 0R 15N R11 0R C17 15p L5 15N C16 2u2 R13 2K2 C18 2u2 MIC_BN E1 ANTENNA SPKR_B_N SPKR_B_P SPKR_A_N SPKR_A_P MIC_BP C19 STAR SP3 MIC 15p C20 C21 DNI C22 DNI AIO0 PIO16 1 2 3 4 5 6 7 8 9 10 11 12 AMP 47p Connect VBAT_SENSE to VBAT if Not Using This Circuit 48 47 46 45 44 43 42 41 40 39 38 37 MIC_BIAS Option Fast Charge 400mR = 500mA GND MIC_AP MIC_AN MIC_BP MIC_BN MIC_BIAS LED_2 USB_DP USB_DN PIO8 PIO1 PIO0 C MIC_AP SPRK_RN SPRK_RP SPKR_LN SPKR_LP GND RF_IO GND GND GND AIO_0 PIO16 PIO17 U2 BSM640/BSM645 GND PIO9 PIO20 PIO21 PIO19 PIO18 PIO7 PIO6 1V8_SMPS VBAT VBAT_SENSE CHG_EXT 36 35 34 33 32 31 30 29 28 27 26 25 C PIO20 PIO21 PIO19 PIO18 PIO7 1V8_SMPS VBAT 1V8_SMPS VBAT VBAT_SENSE CHG_EXT C13 0.1u U3 USB mini VBUS USB_DN USB_DP C26 1u0 AMP_GND J6 C27 1u0 1 3 4 2 C30 PHONOJACK STEREO-14 3V3 C32 1u0 1 11 5 17 6 2 2 1u0 C28 LOUT CON SHDN 47p 30k R22 12k C31 2u2 PIO_POWER R23 0R SPKR_A_P SPI_PCMB_SEL VBAT 16 LINP R20 15 14 SPKR_A_N R24 12k C33 2u2 R26 R27 R28 1K0 1K5 1K8 5 MAX9722AETE R30 30k D1 LN03402 R25 DNI LED 3V3 3V3 High for SPI Low for PCM VBAT R29 C34 47p R17 DNI PIO_POWER 1V8_SMPS R19 0R SW7 PIO_POWER VREG_ENABLE A LED2 2 LED1 4 LED0 6 10k ON/OFF Title <Title> BSM640/BSM645 Size Document Number Custom<Doc> Date: 5 B USB / Charger Interface C29 LINN A GND 3V3 R21 0R SVDD SVDD 12 SPKR_B_P 1 2 3 4 5 4 SGND AUDIO_OUT_L 1 2 3 4 5 VBUS 4 SVSS PVSS PAD 13 9 2u2 MISO CSB MOSI CLK R18 12k PVDD 1u0 SPKR_B_N C25 7 2u2 VBUS DD+ ID GND GND RINP ROUT PGND C24 1 2 3 4 5 6 B RINN R16 12k 8 1 10 3 J4 3 AUDIO_OUT_R R15 30k RSTB LED0 LED1 CSB MOSI CLK MISO PIO_POWER VREG_ENABLE SPI_PCMB_SEL 47p U4 13 14 15 16 17 18 19 20 21 22 23 24 VBUS C23 30k R14 C14 10u GND C12 DNI C15 DNI R12 0R D 4u7 7 15p MIC_AP MIC_AN MIC_BP MIC_BN MIC_BIAS LED2 USB_DP USB_DN C11 2u2 STAR SP2 J3 C8 Optional Ancilliary Circuits R9 2K2 C10 L3 15nH L4 R4 200mR/1%/0603 400mR/1%/0805 MIC_AN RST# LED_0 LED_1 PIO4 PIO2 PIO5 PIO3 PIO_POWER VREG_ENABLE SPI/PCMB# VCHG GND LUMBURG R4 0603 package 3V3 Power L2 15nH R8 0R 3 2 1 R3 BCX51 STAR Keys J2 VBUS 0.1u VOL+ SW6 Low Reset C1 10uF R6 1K0 PIO7 REW R5 1K0 PIO21 D 2 1 L1 VBAT R2 1K0 VBAT VBAT_SENSE PIO19 VBAT J1 1 2 SW2 FWB R1 1K0 RSTB 2 CHG_EXT SW3 PIO18 MFB PIO_POWER GND 4 SW1 VBAT 5 4 3 2 Rev <RevCode> Gemma Thursday, September 27, 2012 Sheet 1 1 of 1

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