COA_UNIT-1new[1].pdf

Please read this disclaimer before proceeding:
This document is confidential and intended solely for the educational purpose of
RMK Group of Educational Institutions. If you have received this document
through email in error, please notify the system manager. This document
contains proprietary information and is intended only to the respective group /
learning community as intended. If you are not the addressee you should not
disseminate, distribute or copy through e-mail. Please notify the sender
immediately by e-mail if you have received this document by mistake and delete
this document from your system. If you are not the intended recipient you are
notified that disclosing, copying, distributing or taking any action in reliance on
the contents of this information is strictly prohibited.

22CB301
COMPUTER
ORGANIZATION AND
ARCHITECTURE
Department: Computer Science and Business
Systems
Batch/Year: 2020-202 / II Year
Created by:
Ms.S.Deepa, Assistant Professor / CSBS
Date: 07.08.2023

Table of Contents
Sl.
No.
Topics Page
No.
1. Contents 5
2. Course Objectives 6
3. Pre Requisites (Course Name with Code) 7
4. Syllabus (With Subject Code, Name, LTPC details) 8
5. Course Outcomes (6) 10
6. CO-PO/PSO Mapping 11
7.
Lecture Plan (S.No., Topic, No. of Periods, Proposed date,
Actual Lecture Date, pertaining CO, Taxonomy level, Mode of
Delivery)
13
8. Activity based learning 14
9.
Lecture Notes ( with Links to Videos, e-book reference, PPTs,
Quiz and any other learning materials )
15
10.
Assignments ( For higher level learning and Evaluation) 60
11. Part A Q & A (with K level and CO) 69
12. Part B Qs (with K level and CO) 72
13.
Supportive online Certification courses (NPTEL, Swayam,
Coursera, Udemy, etc.,)
73
14. Real time Applications in day to day life and to Industry 74
15.
Contents beyond the Syllabus ( COE related Value added
courses)
75
16. Assessment Schedule ( Proposed Date & Actual Date) 76
17. Prescribed Text Books & Reference Books 77
18. Mini Project 78

Course Objective
To know the basic principles and operations of digital computers.
To design Arithmetic and Logic Unit for various fixed- and floating-point
operations.
To develop pipeline architectures for RISC Processors.
To understand Parallel Processor and Various Memory systems.
To understand the peripheral devices and their characteristics.

Pre Requisites
20IT101 - Fundamentals of Computer Science
20EC0241 - Principles of Electronics Engineering
20IT201 - Data Structures and Algorithms

Syllabus
22CB301 COMPUTER ORGANIZATION AND ARCHITECTURE L T P C
3 0 0 3
UNIT I BASIC STRUCTURE OF COMPUTERS & MACHINE
INSTRUCTIONS 9
Functional blocks of a computer: CPU, memory, input-output subsystems, control
unit. Instruction set architecture of a CPU: Registers, instruction execution cycle,
RTL interpretation of instructions, addressing modes, instruction set. Outlining
instruction sets of some common CPUs.
UNIT II DATA REPRESENTATION & COMPUTER ARITHMETIC
9
Data representation: Signed number representation, fixed and floating point
representations, character representation.
Computer arithmetic: Integer addition and subtraction, ripple carry adder, carry
look-ahead adder, etc. multiplication – shift-and-add, Booth multiplier, carry save
multiplier, etc. Division restoring and non-restoring techniques, floating point
arithmetic, IEEE 754 format.
UNIT III BASIC PROCESSING & CONTROL UNIT 9
CPU control unit design: Hardwired and micro-programmed design approaches,
design of a simple hypothetical CPU.
Pipelining: Basic concepts of pipelining, throughput and speedup, pipeline
hazards.

UNIT IV PARALLEL PROCESSING & MEMORY 9
Parallel Processors: Introduction to parallel processors, Concurrent access to
memory and cache coherency.
Memory system design: Semiconductor memory technologies, memory
organization.
Memory organization: Memory interleaving, concept of hierarchical memory
organization, cache memory, cache size vs. block size, mapping functions,
replacement algorithms, write policies.
UNIT V I/O System 9
Peripheral devices and their characteristics: Input-output subsystems, I/O device
interface, I/O transfers – program controlled, interrupt driven and DMA, privileged
and non-privileged instructions, software interrupts and exceptions. Programs and
processes – role of interrupts in process state transitions, I/O device interfaces –
SCSI, USB

Course Outcomes
Understand the basic principles and operations of digital computers.
Design Arithmetic and Logic Unit.
Perform fixed- and floating-point operations
Develop pipeline architectures for RISC Processors.
Understand Parallel Processor Architectures
Understand Various Memory systems & I/O interfacings

CO-PO/PSO Mapping
COs
POs/PSOs
PO1
PO2
PO3
PO4
PO5
PO6
PO7
PO8
PO9
PO10
PO11
PO12
PSO1
PSO2
PSO3
CO1 3 3 3 - - - - - - - - - 3 2 1
CO2 3 2 2 - - - - - - - - - 3 2 1
CO3 3 2 2 - - - - - - - - - 3 2 1
CO4 3 2 2 - - - - - - - - - 3 2 1
CO5 3 2 2 - - - - - - - - - 3 2 1
C06 3 2 2 - - - - - - - - - 3 2 1

Unit I
BASIC STRUCTURE OF
COMPUTERS & MACHINE
INSTRUCTIONS

Lecture Plan
UNIT - I
S.
No.
Topic
Scheduled
Date
Actual Date
of Completion
CO
Mode of
Delivery
Taxonomy
Level
1 Functional Units 20.08.2021 CO1 PPT K1
2
Instruction Execution
Cycle
24.08.2021 CO1 PPT K1
3
Instruction Set
Architecture
25.08.2021 CO1 PPT K2
4
Instruction Format,
Addressing modes
26.08.2021 CO1 PPT K2
5 Registers, RTL 27.08.2021 CO1 PPT K2
6 MIPS Addressing 31.08.2021 CO1 PPT K2
7
Outlining instruction sets
of some common CPUs
1.09.2021 CO1 PPT K2
8 ARM, X86 Instruction Set 2.09.2021 CO1 PPT K2

Activity Based Learning
Cross word puzzles
Quiz

Functional blocks of a computer
Computer Architecture is concerned with the way hardware components are
connected together to form a computer system. It acts as the interface between
hardware and software. It helps us to understand the functionalities of a system.
Architecture involves Logic (Instruction sets, Addressing modes, Data types, Cache
optimization)
Computer Organization is concerned with the structure and behavior of a
computer system as seen by the user. It deals with the components of a connection
in a system. It Organization tells us how exactly all the units in the system are
arranged and interconnected. Organization involves Physical Components (Circuit
design, Adders, Signals, Peripherals)
Computer hardware
Computer hardware consists of electronic circuits, displays, magnetic and optic
storage media and also the communication facilities.

Computer Types
A computer can be defined as a fast electronic calculating machine that accepts
the (data) digitized input information process it as per the list of internally stored
instructions and produces the resulting information.
List of instructions are called programs & internal storage is called computer
memory.
Digital computers have evolved into many different types that vary widely in size,
cost, computational power, and intended use
Modern computers can be divided roughly into four general categories:
1. Embedded computers are integrated into a larger device or system in order to
automatically monitor and control a physical process or environment. They are used
for a specific purpose rather than for general processing tasks. Typical applications
include industrial and home automation, appliances, telecommunication products,
and vehicles. Users may not even be aware of the role that computers play in such
systems.
2. Personal computers have achieved widespread use in homes, educational
institutions, and business and engineering office settings, primarily for dedicated
individual use. They support a variety of applications such as general computation,
document preparation, computer-aided design, audiovisual entertainment,
interpersonal communication, and Internet browsing. A number of classifications are
used for personal computers.
Desktop computers serve general needs and fit within a typical personal
workspace.

Workstation computers offer higher computational capacity and more
powerful graphical display capabilities for engineering and scientific work.
Portable and Notebook computers provide the basic features of a personal
computer in a smaller lightweight package. They can operate on batteries to
provide mobility.
3. Servers and Enterprise systems are large computers that are meant to be shared
by a potentially large number of users who access them from some form of personal
computer over a public or private network. Such computers may host large
databases and provide information processing for a government agency or a
commercial organization.
4. Supercomputers and Grid computers normally offer the highest performance.
They are the most expensive and physically the largest category of computers.
Supercomputers are used for the highly demanding computations needed in weather
forecasting, engineering design and simulation, and scientific work. They have a
high cost. Grid computers provide a more cost-effective alternative. They combine a
large number of personal computers and disk storage units in a physically
distributed high-speed network, called a grid, which is managed as a coordinated
computing resource. By evenly distributing the computational workload across the
grid, it is possible to achieve high performance on large applications ranging from
numerical computation to information searching. There is an emerging trend in
access to computing facilities, known as cloud computing.
Personal computer users access widely distributed computing and storage server
resources for individual, independent, computing needs. The Internet provides
the necessary communication facility. Cloud hardware and software service
providers operate as a utility, charging on a pay-as-you-use basis.

Functional Units of a Computer
The basic architecture of computer was developed by John Von Neumann in
1945. Later we call it as Von Neuman Architecture which consists of Control
Unit, Arithmetic and logic unit, Memory Unit, Registers and Inputs/Outputs. His
architecture based on the stored-program computer concept, where instruction
data and program data are stored in the same memory
A modern computer consists of five functionally independent main parts: input,
memory, arithmetic and logic, output, and control units, as shown in Figure
The input unit accepts coded information from human operators using devices
such as keyboards, or from other computers over digital communication lines.
The information received is stored in the computer’s memory, either for later use
or to be processed immediately by the arithmetic and logic unit.
The processing steps are specified by a program that is also stored in the
memory.
Finally, the results are sent back to the outside world through the output unit.
All of these actions are coordinated by the control unit. An interconnection
network provides the means for the functional units to exchange information and
coordinate their actions.
Arithmetic and logic circuits, in conjunction with the main control circuits, refer as
the processor.
Input and output equipment is often collectively referred to as the input-output
(I/O) unit.

1.Input Device
It is a computer hardware peripheral devices where computers accept coded
information . The most common input device is the keyboard. Whenever a key is
pressed, the corresponding letter or digit is automatically translated into its
corresponding binary code and transmitted to the processor.
Many other kinds of input devices for human-computer interaction are available,
including the touchpad, mouse, joystick, and trackball. These are often used as
graphic input devices in conjunction with displays.
Microphones can be used to capture audio input which is then sampled and
converted into digital codes for storage and processing.
Similarly, cameras can be used to capture video input.
Digital communication facilities, such as the Internet, can also provide input to a
computer from other computers and database servers.

2.Output Device
The output unit is the counterpart of the input unit. Its function is to send
processed results to the outside world. A familiar example of such a device is a
printer. Most printers employ either photocopying techniques, as in laser printers,
or ink jet streams. Such printers may generate output at speeds of 20 or more
pages per minute. However, printers are mechanical devices, and as such are
quite slow compared to the electronic speed of a processor.
Some units, such as graphic displays, provide both an output function, showing
text and graphics, and an input function, through touchscreen capability. The dual
role of such units is the reason for using the single name input/output (I/O) unit
in many cases.

3. Memory unit
The function of the memory unit is to store programs and data.
Types of Memory
Volatile - storage that retains data only if it is receiving power
Non-Volatile - a form of memory that retains data even in the absence of a
power source
There are two classes of storage, called primary memory(Volatile) and secondary
memory(Non-Volatile)
Primary Memory - It also called main memory, is a fast memory that operates
at electronic speeds. Programs must be stored in this memory while they are
being executed.
The memory consists of a large number of semiconductor storage cells, each
capable of storing one bit of information. These cells are rarely read or written
individually. Instead, they are handled in groups of fixed size called words. The
memory is organized so that one word can be stored or retrieved in one basic
operation. The number of bits in each word is referred to as the word length of
the computer, typically 16, 32, or 64 bits.
To provide easy access to any word in the memory, a distinct address is
associated with each word location. Addresses are consecutive numbers, starting
from 0, that identify successive locations. A particular word is accessed by
specifying its address and issuing a control command to the memory that starts
the storage or retrieval process.

Instructions and data can be written into or read from the memory under the
control of the processor. It is essential to be able to access any word location in
the memory as quickly as possible.
A memory in which any location can be accessed in a short and fixed amount of
time after specifying its address is called a random-access memory (RAM).
The time required to access one word is called the memory access time. This time
is independent of the location of the word being accessed. It typically ranges from
a few nanoseconds (ns) to about 100 ns for current RAM units.
Secondary Memory - Although primary memory is essential, it tends to be
expensive and does not retain information when power is turned off.
Thus additional, less expensive, permanent secondary storage is used when large
amounts of data and many programs have to be stored, particularly for
information that is accessed infrequently.
Access times for secondary storage are longer than for primary memory.
A wide selection of secondary storage devices is available, including magnetic
disks, optical disks (DVD and CD), and flash memory devices.

Cache Memory
As an adjunct to the main memory, a smaller, faster RAM unit, called a cache, is
used to hold sections of a program that are currently being executed, along with
any associated data.
The cache is tightly coupled with the processor and is usually contained on the
same integrated-circuit chip.
The purpose of the cache is to facilitate high instruction execution rates.
At the start of program execution, the cache is empty. All program instructions
and any required data are stored in the main memory.
As execution proceeds, instructions are fetched into the processor chip, and a
copy of each is placed in the cache.
When the execution of an instruction requires data located in the main memory,
the data are fetched and copies are also placed in the cache.
Now, suppose a number of instructions are executed repeatedly as happens in a
program loop.
If these instructions are available in the cache, they can be fetched quickly during
the period of repeated use.
Similarly, if the same data locations are accessed repeatedly while copies of their
contents are available in the cache, they can be fetched quickly.
4. Arithmetic and Logic Unit
Most computer operations are executed in the arithmetic and logic unit (ALU) of
the processor. Any arithmetic or logic operation, such as addition, subtraction,
multiplication, division, or comparison of numbers, is initiated by bringing the
required operands into the processor, where the operation is performed by the
ALU.

For example, if two numbers located in the memory are to be added, they are
brought into the processor, and the addition is carried out by the ALU. The sum
may then be stored in the memory or retained in the processor for immediate
use.
When operands are brought into the processor, they are stored in high-speed
storage elements called registers. Each register can store one word of data.
Access times to registers are even shorter than access times to the cache unit on
the processor chip.
5. Control Unit
The memory, arithmetic and logic, and I/O units store and process information
and perform input and output operations. The operation of these units must be
coordinated in some way.
This is the responsibility of the control unit. The control unit is effectively the
nerve center that sends control signals to other units and senses their states.
I/O transfers, consisting of input and output operations, are controlled by
program instructions that identify the devices involved and the information to be
transferred.
Control circuits are responsible for generating the timing signals that govern the
transfers and determine when a given action is to take place.
Data transfers between the processor and the memory are also managed by the
control unit through timing signals.
It is reasonable to think of a control unit as a well-defined, physically separate
unit that interacts with other parts of the computer.
A large set of control lines (wires) carries the signals used for timing and
synchronization of events in all units.

The operation of a computer can be summarized as follows:
The computer accepts information in the form of programs and data through an
input unit and stores it in the memory.
Information stored in the memory is fetched under program control into an
arithmetic and logic unit, where it is processed.
Processed information leaves the computer through an output unit.
All activities in the computer are directed by the control unit.
QUIZ
1.Which memory device generally made up of semiconductors
1.RAM
2.Hard disk
3.Floppy disk
2.ALU makes the use of _____________ to store intermediate results
1.Accumulator
2.Stack
3.Heap
3. Source Program is usually in __________
1.Hiigh level language
2.Machine level language
3.Natural language
Refer:

Instruction Set Architecture (ISA)
Introduction
Instruction set architecture is the part of the processor that is visible to the
programmer or compiler designer. They are the parts of a processor design that
need to be understood in order to write assembly language, such as the machine
language instructions and registers.
The ISA serves as the boundary between software and hardware.
The key role of the Central Processing Unit (CPU) is to perform the calculations, to
issue the commands, to coordinate all other hardware components, and executing
programs including operating system, application programs etc. on your computer.
But CPU is primarily the core hardware component; you must speak to it in the
core binary machine language. The words of a machine language are known as
instructions, and its syntax is known as an instruction set.
Instruction set: Instruction set is the collection of machine language
instructions that a particular processor understands and executes. In other words,
a set of assembly language mnemonics represents the machine code of a
particular computer.
Therefore, if we define all the instructions of a computer, we can say we have
defined the instruction set. It should be noted here that the instructions available
in a computer are machine dependent, that is, a different processors have
different instruction sets.
Elements of an instruction:
As the purpose of instruction is to communicate to CPU what to do, it requires a
minimum set of communication. This, each instruction consists of several fields.
The most common fields found in instruction formats are
What operation to perform?(Opcodes)
On what operands(Operands)

Opcode: (What operation to perform?)
An operation code field termed as opcode that specifies the operation to be
performed.
Operands: (Where are the operands?)
An address field of operand on which data processing is to be performed.
An operand cap reside in the memory or a processor register or can be
incorporated within the operand field of instruction as an immediate
constant.
Therefore a mode field is needed that specifies the way the operand or its
address is to be determined.
Instruction format. : Instruction is represented as a sequence of bits. A layout of
an instruction is termed as instruction format. Instruction formats are primarily
machine dependent. A CPU instruction set can use many instruction formats at a
time. Even the length of opcode varies in the same processor.
The opcode size is 6 bits. So, in general it will have 2^6 = 32 operations.
There are two bits for addressing modes. Therefore, there are 2^2 = 4 different
addressing modes possible for this machine.
The last field (8 - 3 1 bits = 24 bits) here is the operand or the address of
operand field.
In case it is an address of operand in memory, then the maximum memory size
supported by this machine is 2^24 = 16 MB

In general, the Instruction Set Architecture (ISA) of a processor can be
differentiated using five categories:
Operand Storage in the CPIJ - Where are the operands kept other than the
memory?
Number of explicitly named operands - How many operands are named in an
instruction?
Operand location - Can any ALU instruction operand be located in memory? Or
must all operands be kept internally in the CPU registers?
Operation - What operations are provided in the ISA?
Type and size of operands - What is the type and size of each operand and how is
it specified?
Operand Data Types
Operand types usually give operand size implicitly.

Addresses: Operands residing in memory are specified by their memory address
and operands residing in registers are specified by a register address. Addresses
provided in the instruction are operand references.
Numbers: All machine languages include numeric data types. Numeric data usually
use one of three representations:
Floating-point numbers-single precision (1 sign bit, 8 exponent bits, 23
mantissa bits) and double precision (1 sign bit, 11 exponent bits, 52
mantissa bits).
Fixed Point Integers(Signed or Unsigned)
Binary Coded Decimal Numbers
Characters: A common form of data is text or character strings. Characters are
represented in numeric form, mostly in ASCII (American Standard Code for
Information Exchange). Another Code used to encode characters is the Extended
Binary Coded Decimal Interchange Code (EBCDIC).
Logical data: Each word or byte is treated as a single unit of data. When an n-bit
data unit is considered as consisting of n 1 -bit items of data with each item having
the value 0 or 1, then they are viewed as logical data. Such bit-oriented data can be
used to store an array of Boolean or binary data variables where each variable can
take on only the values 1 (true) and 0 (false). One simple application of such a data
may be the cases where we manipulate bits of a data item. For example, in floating-
point addition we need to shift mantissa bits.
Instruction Execution Cycle
The main execution process is done by the processor. The processing of
instruction involves two steps, instruction fetch and instruction execution. Each
instruction is fetched from the memory separately and executed. Depending on
the nature of the instruction its execution may deal with a number of operations.

An instruction cycle refers to the processing of a particular instruction. Each instruction cycle
goes through the following phases during its processing:
1. Fetching instruction from memory.
2. Decoding the instruction.
3. Reading the effective address from memory in case of indirect address.
4. Executing the instruction
After the above four steps are completed, the control switches back to the first step and
repeats the same process for the next instruction. Hence, the cycle continues until a HALT
condition is met.
Memory- Processor Interface
The processor-memory interface is a circuit which manages the transfer of data between
the main memory and the processor.
If a word is to be read from the memory, Read control signal.
the interface sends the address of that word to the memory
The interface waits for the word to be retrieved, then transfers it to the appropriate
processor register
If a word is to be written into memory, Write control signal.
The interface transfers both the address and the word to the memory along.

In addition to the ALU and the control circuitry, the processor contains a number
of registers used for several different purposes.
The instruction register (IR) holds the instruction that is currently being
executed. Its output is available to the control circuits, which generate the timing
signals that control the various processing elements involved in executing the
instruction.
The program counter (PC) is another specialized register. It contains the
memory address of the next instruction to be fetched and executed. During the
execution of an instruction, the contents of the PC are updated to correspond to
the address of the next instruction to be executed. It is customary to say that the
PC points to the next instruction that is to be fetched from the memory.

GPR(general-purpose registers) R0 through Rn−1, often called processor
registers. They serve a variety of functions, including holding operands that have
been loaded from the memory for processing
Accumulator (AC) and multiplier quotient (MQ): It is a special register to
hold temporarily operands and results of ALU operations. For example, the result
of multiplying two 40-bit numbers is an 80-bit number; the most significant 40
bits are stored in the AC and the least significant in the MQ.
The other two registers which facilitate communication with memory are:
Memory address registers(MAR) : It is connected to System Bus address
lines. It specifies the address of a read or write operation in memory.
Memory Buffer Register(MBR) or Memory Data Register(MDR): It is
connected to the data lines of the system bus. It holds the memory value to
be stored, or the last value read from the memory.
Register and its functions listed with size in the below table

Operating Steps
A program must be in the main memory in order for it to be executed. It is often
transferred there from secondary storage through the input unit.
Execution of the program begins when the PC is set to point to the first
instruction of the program. The contents of the PC are transferred to the memory
along with a Read control signal. When the addressed word (in this case, the first
instruction of the program) has been fetched from the memory it is loaded into
register IR. At this point, the instruction is ready to be interpreted and executed.
Instructions such as Load, Store, and Add perform data transfer and arithmetic
operations. If an operand that resides in the memory is required for an
instruction, it is fetched by sending its address to the memory and initiating a
Read operation. When the operand has been fetched from the memory, it is
transferred to a processor register.
After operands have been fetched in this way, the ALU can perform a desired
arithmetic operation, such as Add, on the values in processor registers. The result
is sent to a processor register.
If the result is to be written into the memory with a Store instruction, it is
transferred from the processor register to the memory, along with the address of
the location where the result is to be stored, then a Write operation is initiated.
At some point during the execution of each instruction, the contents of the PC are
incremented so that the PC points to the next instruction to be executed.
Thus, as soon as the execution of the current instruction is completed, the
processor is ready to fetch a new instruction.

In addition to transferring data between the memory and the processor, the
computer accepts data from input devices and sends data to output devices.
Thus, some machine instructions are provided for the purpose of handling I/O
transfers.
Interrupt
Normal execution of a program may be preempted if some device requires urgent
service. For example, a monitoring device in a computer-controlled industrial
process may detect a dangerous condition.
In order to respond immediately, execution of the current program must be
suspended. To cause this, the device raises an interrupt signal, which is a request
for service by the processor.

The processor provides the requested service by executing a program called
an interrupt-service routine. Because such diversions may alter the internal
state of the processor, its state must be saved in the memory before
servicing the interrupt request.
Normally, the information that is saved includes the contents of the PC, the
contents of the general-purpose registers, and some control information.
When the interrupt-service routine is completed, the state of the processor
is restored from the memory so that the interrupted program may continue.
Register Transfer Language
We need to describe the transfer of information from one location in a computer
to another. Possible locations that may be involved in such transfers are memory
locations, processor registers, or registers in the I/O subsystem. Most of the time,
we identify such locations symbolically with convenient names.
For example, names that represent the addresses of memory locations may be
LOC, PLACE, A, or VAR2. Predefined names for the processor registers may be R0
or R5. Registers in the I/O subsystem may be identified by names such as
DATAIN or OUTSTATUS.
To describe the transfer of information, the contents of any location
are denoted by placing square brackets around its name.
R2 ← [LOC]
Thus, the expression means that the contents of memory location LOC
are transferred into processor register R2.

Consider the operation that adds the contents of registers R2 and R3, and places
their sum into register R4. This action is indicated as
R4 ← [R2] + [R3]
This type of notation is known as Register Transfer Notation (RTN). Note that the
right hand side of an RTN expression always denotes a value, and the left-hand
side is the name of a location where the value is to be placed, overwriting the old
contents of that location.
Some notations mentioned in the below table
Register Transfer Operations:
The operation performed on the data stored in the registers are referred to as
register transfer operations.

There are different types of register transfer operations:
1. Simple Transfer
R2 <- R1
The content of R1 are copied into R2 without affecting the content of R1. It is an
unconditional type of transfer operation.
2. Conditional Transfer
It indicates that if P=1, then the content of R1 is transferred to R2. It is a
unidirectional operation
3. Simultaneous Operations
If 2 or more operations are to occur simultaneously then they are separated with
comma (,).
If the control function P=1, then load the content of R1 into R2 and at the same
clock load the content of R2 into R1.

Addressing Modes
In general, a program operates on data that reside in the computer’s memory.
These data can be organized in a variety of ways that reflect the nature of the
information and how it is used.
Programs are normally written in a high-level language, which enables the
programmer to conveniently describe the operations to be performed on various
data structures.
When translating a high-level language program into assembly language, the
compiler generates appropriate sequences of low-level instructions that
implement the desired operations.
The different ways for specifying the locations of instruction operands are known
as addressing modes.

we examine the most common addressing techniques here
Immediate
Direct
Indirect
Register
Register indirect
Displacement
Stack
NOTE: EA-(Effective address). The address of the operand is known as the
effective address. It will be either a main memory address or a register
Immediate Addressing
The simplest form of addressing is immediate addressing, in which the operand
value is present in the instruction
Operand = A
This mode can be used to define and use constants or set initial values of
variables. Typically, the number will be stored in twos complement form; the
leftmost bit of the operand field is used as a sign bit.
When the operand is loaded into a data register, the sign bit is extended to the
left to the full data word size.
In some cases, the immediate binary value is interpreted as an unsigned
nonnegative integer.

The advantage of immediate addressing is that no memory reference other than
the instruction fetch is required to obtain the operand, thus saving one memory
or cache cycle in the instruction cycle.
The disadvantage is that the size of the number is restricted to the size of the
address field, which, in most instruction sets, is small compared with the word
length.
Direct Addressing
A very simple form of addressing is direct addressing, in which the address field
contains the effective address of the operand:
EA=A
The technique was common in earlier generations of computers but is not
common on contemporary architectures. It requires only one memory reference
and no special calculation. The obvious limitation is that it provides only a limited
address space.
Indirect Addressing
With direct addressing, the length of the address field is usually less than the
word length, thus limiting the address range. One solution is to have the address
field refer to the address of a word in memory, which in turn contains a full-length
address of the operand. This is known as indirect addressing:
EA = (A)
As defined earlier, the parentheses are to be interpreted as meaning contents
of.
The obvious advantage of this approach is that for a word length of N, an address
space of is now available
The disadvantage is that instruction execution requires two memory references to
fetch the operand: one to get its address and a second to get its value.

Consider following example for Direct and Indirect Addressing
In First figure, Addressing mode is 0, which indicates direct addressing.
Operand is ADD.
Address is 300. This indicates the address of the operand.
The instruction is stored in the 22nd location. The control jumps to the 300th
location to access the operand
In Second figure, Addressing mode is 1, which indicates indirect addressing.
Operand is ADD.
Address is 200. This indicates the address of the operand. The control goes to the
address 200 to get the address of the operand. Here, the address is 1200. The
operand found in this address location is added to the data in accumulator.
In the first figure the effective address is 300 and in the second figure it is 1200.

Register addressing
It is similar to direct addressing. The only difference is that the address field
refers to a register rather than a main memory address
EA = R
To clarify, if the contents of a register address field in an instruction is 5, then
register R5 is the intended address, and the operand value is contained in
R5.Typically, an address field that references registers will have from 3 to 5 bits,
so that a total of from 8 to 32 general-purpose registers can be referenced.
The advantages of register addressing are only a small address field is needed in
the instruction, and no time-consuming memory references are required
The disadvantage of register addressing is that the address space is very limited.
If register addressing is heavily used in an instruction set, this implies that the
processor registers will be heavily used. Because of the severely limited number
of registers (compared with main memory locations), their use in this fashion
makes sense only if they are employed efficiently.

If every operand is brought into a register from main memory, operated on once,
and then returned to main memory, then a wasteful intermediate step has been
added. If, instead, the operand in a register remains in use for multiple operations,
then a real savings is achieved
Register Indirect Addressing
It is analogous to indirect addressing. In both cases, the only difference is
whether the address field refers to a memory location or a register. Thus, for
register indirect address,
EA = R
The advantages and limitations of register indirect addressing are basically the
same as for indirect addressing. In both cases, the address space limitation
(limited range of addresses) of the address field is overcome by having that field
refer to a wordlength location containing an address. In addition, register indirect
addressing uses one less memory reference than indirect addressing.

Displacement Addressing
A very powerful mode of addressing combines the capabilities of direct addressing
and register indirect addressing. It is known by a variety of names depending on
the context of its use, but the basic mechanism is the same. We will refer to this
as displacement addressing:
EA = A+(R)
Displacement addressing requires that the instruction have two address fields, at
least one of which is explicit. The value contained in one address field(value = A)
is used directly. The other address field, or an implicit reference based on opcode,
refers to a register whose contents are added to A to produce the effective
address.
We will describe three of the most common uses of displacement addressing:
Relative addressing
Base-register addressing
Indexing
RELATIVE ADDRESSING For relative addressing, also called PC-relative
addressing, the implicitly referenced register is the program counter (PC). That is,
the next instruction address is added to the address field to produce the EA.

The method of calculating the EA is the same for both base-register addressing
and indexing, and in both cases the register reference is sometimes explicit and
sometimes implicit (for different processor types).
Typically, the address field is treated as a twos complement number for this
operation. Thus, the effective address is a displacement relative to the address of
the instruction.
BASE-REGISTER ADDRESSING For base-register addressing, the
interpretation is the following: The referenced register contains a main memory
address, and the address field contains a displacement (usually an unsigned
integer representation) from that address. The register reference may be explicit
or implicit. Base-register addressing also exploits the locality of memory
references. It is a convenient means of implementing segmentation.
In some implementations, a single segment-base register is employed and is used
implicitly. In others, the programmer may choose a register to hold the base
address of a segment, and the instruction must reference it explicitly.
In this latter case, if the length of the address field is K and the number of
possible registers is N, then one instruction can reference any one of N areas of
2^kwords.
INDEXING For indexing, the interpretation is typically the following: The address
field references a main memory address, and the referenced register contains a
positive displacement from that address. Note that this usage is just the opposite
of the interpretation for base-register addressing. It is more than just a matter of
user interpretation

. Because the address field is considered to be a memory address in indexing, it
generally contains more bits than an address field in a comparable base-register
instruction. Also, we shall see that there are some refinements to indexing that
would not be as useful in the base-register context.
The method of calculating the EA is the same for both base-register addressing
and indexing, and in both cases the register reference is sometimes explicit and
sometimes implicit (for different processor types).
An important use of indexing is to provide an efficient mechanism for performing
iterative operations. Consider, for example, a list of numbers stored starting at
location A. Suppose that we would like to add 1 to each element on the list. We
need to fetch each value, add 1 to it, and store it back.
Because index registers are commonly used for such iterative tasks, it is typical
that there is a need to increment or decrement the index register after each
reference to it. Because this is such a common operation, some systems will
automatically do this as part of the same instruction cycle. This is known as
autoindexing.
EA=A+(R)
(R) is (R) + 1
If indexing is performed after the indirection, it is termed postindexing
EA=(A)+(R)
If the indexing is performed before the indirection is preindexing
EA=(A+(R))

Stack Addressing
A stack is a linear array of locations. It is sometimes referred to as a pushdown
list or last-in-first-out queue.
The stack is a reserved block of locations. Items are appended to the top of the
stack so that, at any given time, the block is partially filled. Associated with the
stack is a pointer whose value is the address of the top of the stack.
Alternatively, the top two elements of the stack may be in processor registers, in
which case the stack pointer references the third element of the stack(in below
figure).
The stack pointer is maintained in a register. Thus, references to stack locations in
memory are in fact register indirect addresses.
The stack mode of addressing is a form of implied addressing. The machine
instructions need not include a memory reference but implicitly operate on the
top of the stack.

Check Your Progress (State True or False)
An instruction set is a collection of all the instructions a CPU can execute
Instructions can take different formats.
The opcode field of an instruction specifies the address field of operand on which
data processing is to be performed.
The operands placed in processor registers are fetched faster than that of
operands placed in memory.
Operands must refer to data and cannot be data.
Reference Video
https://www.youtube.com/watch?v=GRInNLx3Tug
https://www.youtube.com/watch?v=U7elB4HpY3M

Types of Instructions
Computer instructions are the translation of high level language code to machine
level language programs. Thus, from this point of view the machine instructions
can be classified under the following categories
Data Transfer Instructions
These instructions transfer data from one location in the computer to another
location without changing the data content. The most common transfers are
between:
processor registers and memory,
processor registers and I/O,
processor registers themselves.
These instructions need:
the location of source and destination operands and
the mode of addressing for each operand.
These symbols are used for understanding purposes only, the actual instructions
are binary. Different computers may use different mnemonic for the same
instruction

Data Transfer Mnemonic codes
Data Processing Instructions
These instructions perform arithmetic and logical operations on data. Data
manipulation Instructions can be divided into three basic types:
1. Arithmetic: The four basic operations are ADD, SUB, MUL and DIV. An
arithmetic instruction may operate on fixed-point data, binary or decimal data etc.
The other possible operations include a variety of single-operand instructions, for
example ABSOLUTE, NEGATE, INCREMENT, DECREMENT.
The execution of arithmetic instructions requires bringing in the operands in the
operational registers so that the data can be processed by ALU. Such functionality
is implemented generally within instruction execution steps
2.Logical: AND. OR, NOT, XOR operate on binary data stored in registers
3. Shift: Shift operation is used for transfer of bits either to the left or to
the right. It can be used to realize simple arithmetic operation or data
communication/recognition etc,

Shift operation is of three types
Logical shifts LOGICAL SHIFT LEFT and LOGICAL SHIFT RIGHT insert zeros to the
end bit position and the other bits of a word are shifted left or right respectively.
The end bit position is the leftmost bit for shift right and the right most bit
position for the shift left. The bit shifted out is lost.
Arithmetic shifts ARITHMETIC SHIFT LEFT and ARITHMETIC SHIFT RIGHT are
the same as LOGICAL SHIFT LEFT and LOGICAL SHIFT RIGHT except that the
sign bit it remains unchanged. On an arithmetic shift right, the sign bit is
replicated into the bit position to its right. On an arithmetic shift left, a logical shift
left is performed on all bits but the sign bit, which is retained. The arithmetic left
shift and a logical left shift when performed on numbers represented in two's
complement notation cause multiplication by 2 when there is no overflow.
Arithmetic shift right corresponds to a division by 2 provided there is no
underflow.
Circular shifts ROTATE LEFT and ROTATE RIGHT. Bits shifted out at one end of
the word are not lost as in a logical shift but are circulated back into the other
end.

Program Control Instructions
These instructions specify conditions for altering the sequence of program
execution or in other words the content of PC (program counter) register. PC
points to memory location that holds the next instruction to be executed. The
change in value of-PC as a result of execution of control instruction like BRANCH
or JUMP causes a break in the sequential execution of instructions. The most
common control Instructions are
➢ Sequential
➢ Branch
➢ Loop
➢ Procedure or Function call
RISC and CISC
They are two different styles of instruction sets. We introduced RISC first because
it is simpler and easier to understand. Having looked at some basic features of
both styles, we should summarize their main characteristics.
RISC style is characterized by:
Simple addressing modes
All instructions fitting in a single word
Fewer instructions in the instruction set, as a consequence of simple
addressing modes
Arithmetic and logic operations that can be performed only on operands in
processor registers

Load/store architecture that does not allow direct transfers from one
memory location to another; such transfers must take place via a processor
register
Simple instructions that are conducive to fast execution by the processing
unit using techniques such as pipelining which comes in unit III
Programs that tend to be larger in size, because more, but simpler
instructions are needed to perform complex tasks
CISC style is characterized by:
More complex addressing modes
More complex instructions, where an instruction may span multiple words
Many instructions that implement complex tasks
Arithmetic and logic operations that can be performed on memory operands
as well as operands in processor registers
Transfers from one memory location to another by using a single Move
instruction
Programs that tend to be smaller in size, because fewer, but more complex
instructions are needed to perform complex tasks
Before the 1970s, all computers were of CISC type. An important objective was to
simplify the development of software by making the hardware capable of
performing fairly complex tasks, that is, to move the complexity from the software
level to the hardware level. This is conducive to making programs simpler and
shorter, which was important when computer memory was smaller and more
expensive to provide. Today, memory is inexpensive and most computers have
large amounts of it.

RISC-style designs emerged as an attempt to achieve very high performance by
making the hardware very simple, so that instructions can be executed very
quickly in pipelined fashion as will be discussed in Unit III.
This results in moving complexity from the hardware level to the software level.
Sophisticated compilers were developed to optimize the code consisting of simple
instructions. The size of the code became less important as memory capacities
increased.
While the RISC and CISC styles seem to define two significantly different
approaches, today’s processors often exhibit what may seem to be a compromise
between these approaches.
For example, it is attractive to add some non-RISC instructions to a RISC
processor in order to reduce the number of instructions executed, as long as the
execution of these new instructions is fast.
Consider Instruction Set comes from MIPS Technologies, and is an elegant
example of the instruction sets designed since the 1980s. it stands for
microcomputer without interlocked pipeline stages
Three other popular instruction sets.
ARMv7 is similar to MIPS. More than 9 billion chips with ARM processors were
manufactured in 2011, making it the most popular instruction set in the world.
The second example is the Intel x86, which powers both the PC and the cloud of
the PostPC Era.
ARMv8, which extends the address size of the ARMv7 from 32 bits to 64 bits.
This similarity of instruction sets occurs because all computers are
constructed from hardware technologies based on similar underlying
principles and because there are a few basic operations that all computers must
provide

Moreover, computer designers have a common goal: to find a language that
makes it easy to build the hardware and the compiler while maximizing
performance and minimizing cost and energy.
MIPS Instruction set

Operations of the computer Hardware
Every computer must be able to perform arithmetic. The MIPS assembly language
notation
Add a,b,c
This instructs a computer to add the two variables b & c and to put their sum in a.
This notation is rigid in that each MIPS arithmetic instruction performs only one
operation and must always have exactly three variables.
For example, suppose we want to place the sum of four variables b, c, d, and e
into variable a. The following sequence of instructions adds the four variables:
add a, b, c # b + c -> a
add a, a, d # b + c +d -> a
add a, a, e # b + c +d +e -> a
Thus, it takes three instructions to sum the four variables. #- comment line in
MIPS
Note that unlike other programming languages, each line of this language can
contain at most one instruction. Another difference from C is that comments
always terminate at the end of a line.
The natural number of operands for an operation like addition is three: the two
numbers being added together and a place to put the sum. Requiring every
instruction to have exactly three operands, no more and no less, conforms to the
philosophy of keeping the hardware simple: hardware for a variable number of
operands is more complicated than hardware for a fixed number. This situation
illustrates the first of three underlying principles of hardware design:
Design Principle 1: Simplicity favors regularity.
.

We can now show, in the two examples that follow, the relationship of programs
written in higher-level programming languages to programs in this more primitive
notation
Compiling Two C Assignment Statements into MIPS
This segment of a C program contains the five variables a, b, c, d, and e.
a = b + c;
d = a – e;
The translation from C to MIPS assembly language instructions is performed by
the compiler. Show the MIPS code produced by a compiler.
A MIPS instruction operates on two source operands and places the result in one
destination operand. Hence, the two simple statements above compile directly
into these two MIPS assembly language instructions:
add a, b, c
sub d, a, e
Operands of the Computer Hardware
Unlike programs in high-level languages, the operands of arithmetic instructions
are restricted; they must be from a limited number of special locations built
directly in hardware called registers. Registers are primitives used in hardware
design that are also visible to the programmer when the computer is completed,
so you can think of registers as the bricks of computer construction.
The size of a register in the MIPS architecture is 32 bits; groups of 32 bits occur
so frequently that they are given the name word in the MIPS architecture. One
major difference between the variables of a programming language and registers
is the limited number of registers, typically 32 on current computers, like MIPS.

The reason for the limit of 32 registers may be found in the second of our three
underlying design principles of hardware technology:
Design Principle 2: Smaller is faster
A very large number of registers may increase the clock cycle time simply because
it takes electronic signals longer when they must travel farther. Guidelines such as
“smaller is faster” are not absolutes; 31 registers may not be faster than 32. Yet,
the truth behind such observations causes computer designers to take them
seriously. In this case, the designer must balance the craving of programs for
more registers with the designer’s desire to keep the clock cycle fast.
MIPS Registers
Problem
1. A somewhat complex statement contains the five variables f, g, h, i, and j:
f = (g + h) – (i + j); What might a C compiler produce?
2. Assume variable h is associated with register $s2 and the base address of
the array A is in $s3. What is the MIPS assembly code for the C assignment
statement below

X86 Instructions:
Designers of instruction sets sometimes provide more powerful operations than
those found in ARM and MIPS. The goal is generally to reduce the number of
instructions executed by a program. The danger is that this reduction can occur at
the cost of simplicity, increasing the time a program takes to execute because the
instructions are slower. This slowness may be the result of a slower clock cycle
time or of requiring more clock cycles than a simpler sequence.
The x86 is equipped with a variety of addressing modes intended to allow the
efficient execution of high-level languages

There are six segment registers; the one being used for a particular reference
depends on the context of execution and the instruction Each segment register
holds an index which holds the starting address of the corresponding segments
Associated with each user-visible segment register is a segment descriptor
register (not programmer visible), which records the access rights for the
segment as well as the starting address and limit (length) of the segment. In
addition, there are two registers that may be used in constructing an address: the
base register and the index register
X86 Addressing modes
Immediate mode, the operand is included in the instruction. The operand can
be a byte, word, or doubleword of data.
Register operand mode, the operand is located in a register. For general
instructions, such as data transfer, arithmetic, and logical instructions, the
operand can be one of the 32-bit general registers (EAX, EBX, ECX,EDX,ESI, EDI,
ESP, EBP),
one of the 16-bit general registers (AX, BX, CX, DX, SI, DI, SP, BP), or one of the
8- bit general registers (AH, BH, CH, DH, AL, BL, CL, DL). There are also some
instructions that reference the segment selector registers (CS, DS, ES, SS, FS,
GS).
The remaining addressing modes reference locations in memory. The memory
location must be specified in terms of the segment containing the location and the
offset from the beginning of the segment. In some cases, a segment is specified
explicitly; in others, the segment is specified by simple rules that assign a
segment by default.

Displacement mode, the operand’s offset is contained as part of the instruction
as an 8-, 16-, or 32-bit displacement. With segmentation, all addresses in
instructions refer merely to an offset in a segment.
The displacement addressing mode is found on few machines because, it leads to
long instructions. In the case of the x86, the displacement value can be as long as
32 bits, making for a 6-byte instruction. Displacement addressing can be useful
for referencing global variables.
The remaining addressing modes are indirect, in the sense that the address
portion of the instruction tells the processor where to look to find the address.
The base mode specifies that one of the 8-, 16-, or 32-bit registers contains the
effective address. This is equivalent to what we have referred to as register
indirect addressing.
In the base with displacement mode, the instruction includes a displacement
to be added to a base register, which may be any of the general-purpose
registers. Examples of uses of this mode are as follows
Used by a compiler to point to the start of a local variable area. For example,
the base register could point to the beginning of a stack frame, which
contains the local variables for the corresponding procedure.
Used to index into an array when the element size is not 1, 2, 4, or 8 bytes
and which therefore cannot be indexed using an index register. In this case,
the displacement points to the beginning of the array, and the base register
holds the results of a calculation to determine the offset to a specific element
within the array.
Used to access a field of a record. The base register points to the beginning
of the record, while the displacement is an offset to the field.

In the scaled index with displacement mode, the instruction includes a
displacement to be added to a register, in this case called an index register. The
index register may be any of the general-purpose registers except the one called
ESP, which is generally used for stack processing.
In calculating the effective address, the contents of the index register are
multiplied by a scaling factor of 1, 2, 4, or 8, and then added to a displacement.
This mode is very convenient for indexing arrays. A scaling factor of 2 can be
used for an array of 16-bit integers. A scaling factor of 4 can be used for 32-bit
integers or floating-point numbers. Finally, a scaling factor of 8 can be used for an
array of double-precision floating-point numbers.
The base with index and displacement mode sums the contents of the base
register, the index register, and a displacement to form the effective address.
Again, the base register can be any general-purpose register and the index
register can be any general-purpose register except ESP.
As an example, this addressing mode could be used for accessing a local array on
a stack frame. This mode can also be used to support a two-dimensional array; in
this case, the displacement points to the beginning of the array, and each register
handles one dimension of the array.
The based scaled index with displacement mode sums the contents of the
index register multiplied by a scaling factor, the contents of the base register, and
the displacement. This is useful if an array is stored in a stack frame; in this case,
the array elements would be 2, 4, or 8 bytes each in length. This mode also
provides efficient indexing of a two-dimensional array when the array elements
are 2, 4, or 8 bytes in length.

Finally, relative addressing can be used in transfer-of-control instructions. A
displacement is added to the value of the program counter, which points to the
next instruction. In this case, the displacement is treated as a signed byte, word,
or doubleword value, and that value either increases or decreases the address in
the program counter.
X86 Instruction Format
The x86 is equipped with a variety of instruction formats. Instructions are made
up of from zero to four optional instruction prefixes, a 1- or 2-byte opcode, an
optional address specifier (which consists of the ModR/m byte and the Scale
Index byte) an optional displacement, and an optional immediate field.

Instruction prefixes: The instruction prefix, if present, consists of the LOCK
prefix or one of the repeat prefixes. The LOCK prefix is used to ensure exclusive
use of shared memory in multiprocessor environments. The repeat prefixes
specify repeated operation of a string, which enables the x86 to process strings
much faster than with a regular software loop.
Segment override: Explicitly specifies which segment register an instruction
should use, overriding the default segment-register selection generated by the
x86 for that instruction
Operand size: An instruction has a default operand size of 16 or 32 bits, and the
operand prefix switches between 32-bit and 16-bit operands.
Address size: The processor can address memory using either 16- or 32-bit
addresses. The address size determines the displacement size in instructions and
the size of address offsets generated during effective address calculation. One of
these sizes is designated as default, and the address size prefix switches between
32-bit and 16-bit address generation.
Opcode: The opcode field is 1, 2, or 3 bytes in length. The opcode may also
include bits that specify if data is byte- or full-size (16 or 32 bits depending on
context), direction of data operation (to or from memory), and whether an
immediate data field must be sign extended.
The ModR/m byte specifies whether an operand is in a register or in memory; if
it is in memory, then fields within the byte specify the addressing mode to be
used. The ModR/m byte consists of three fields: The Mod field (2 bits) combines
with the r/m field to form 32 possible values: 8 registers and 24 indexing modes;
the Reg/Opcode field (3 bits) specifies either a register number or three more bits
of opcode information; the r/m field (3 bits) can specify a register as the location
of an operand, or it can form part of the addressing-mode encoding in
combination with the Mod field.

SIB: The Scale field (2 bits) specifies the scale factor for scaled indexing; the
Index field (3 bits) specifies the index register; the Base field (3 bits) specifies the
base register.
Displacement: When the addressing-mode specifier indicates that a
displacement is used, an 8-, 16-, or 32-bit signed integer displacement field is
added.
Immediate: Provides the value of an 8-, 16-, or 32-bit operand.
ARM Architecture
ARM is the most popular instruction set architecture for embedded devices, with
more than 9 billion devices recently. There is a similar core of instruction sets for
arithmetic-logical and data transfer instructions for MIPS and ARM. e principal
difference is that MIPS has more registers and ARM has more addressing modes
LOAD/STORE ADDRESSING Load and store instructions are the only
instructions that reference memory. This is always done indirectly through a base
register plus offset.

DATA PROCESSING INSTRUCTION ADDRESSING Data processing
instructions use either register addressing of a mixture of register and immediate
addressing. For register addressing, the value in one of the register operands may
be scaled using one of the five shift operators defined in the preceding paragraph.
BRANCH INSTRUCTIONS The only form of addressing for branch instructions is
immediate addressing. The branch instruction contains a 24-bit value. For address
calculation, this value is shifted left 2 bits, so that the address is on a word
boundary. Thus the effective address range is ;32 MB from the program counter.
ARM Instruction Formats
All instructions in the ARM architecture are 32 bits long and follow a regular
format. The first four bits of an instruction are the condition code. The next three
bits specify the general type of instruction. For most instructions other than
branch instructions, the next five bits constitute an opcode and/or modifier bits
for the operation. The remaining 20 bits are for operand addressing. The regular
structure of the instruction formats eases the job of the instruction decode units

Assignments
1. A processor’s instruction set consists of 200 instructions where the instructions
encode both the number of operands and the operand addressing modes, and
uses a variable length instruction format. The instruction set permits 0 operand,
1 operand and 2 operand instructions. Assuming there are 64 registers, 1G of
addressable memory, and immediate data that can be from -1,048,576 and
+1,048,575, and assuming we can have no more than 1 memory reference
(which will be a direct memory reference) in any instruction, what are the ranges
of instruction lengths from smallest to largest? How does your answer change if
the memory reference can be a base displacement reference?
2. A processor uses a fixed length 32-bit instruction format. The processor has 98
instructions. Instructions can have 0, 1, 2 or 3 operands. The instruction format
is: Op code Num ops Mode 1 Op1 Mode 2 Op2 Mode3 Op3 Assume there are 10
addressing modes. Answer the following questions.
a. To use 3 operands, the operands must all be registers. How many
registers should we equip this processor to have?
b. One mode is an immediate datum in two’s complement. For this mode,
there are two operands, a register and the immediate datum. If the processor has
64 registers, what is the largest immediate datum.
c. The load/store instructions have two operands, a register to store (or
currently storing) the datum, and a memory location specified using a base-
displacement mode. The base is specified as an address and the displacement is
specified in a register. Assuming there are 32 registers, what is the largest memory
address that can be specified (the base)?
d. Redo part c assuming that the first operand is stored in register R0 so
that it can be omitted from the instruction so that you only have to reference the
base-displacement information. Also assume 16 registers instead of 32. What is the
largest memory address that can be specified (the base)? Op code is 7 bits, mode is
4 bits

Part A – Q & A(with K level and CO)
1.What are the five classic components of a computer? CO1, K1
Processor(CPU)
Main memory
Secondary memory
Input devices
Output devices
2.What is instruction set Architecture? CO1, K2
An instruction set architecture (ISA) defines the set of basic operations a
computer must support. This includes the functional definition of operations and
precise descriptions of how to invoke and access them. The ISA serves as the
boundary between the software and hardware.
3.Define Computer architecture. CO1, K2
Computer architecture is a set of rules and methods that describe the
functionality, organization, and implementation of computer systems.
4. Define – Stored Program Concepts. CO1,K2
In the stored program concept, both the instructions and the data (that the
instructions operate on) are stored in the computer memory itself. Then the
processor reads the instructions and data from memory, executes then result is
written to the memory.
5. What are the fields in an MIPS instruction? CO1, K1
op: Basic operation of the instruction, traditionally called the opcode.
■ rs: The first register source/destination operand.
■ rt: The second register source/destination operand.

6. List the different addressing modes. CO1,K1
Immediate addressing, where the operand is a constant within the instruction
itself
Register addressing, where the operand is a register
Base or displacement addressing, where the operand is at the memory location
whose address is the sum of a register and a constant in the instruction
PC-relative addressing, where the branch address is the sum of the PC and a
constant in the instruction
Pseudo direct addressing, where the jump address is the 26 bits of the instruction
concatenated with the upper bits of the PC
7.What are the different types of operands? Give examples. CO1, K2
Registers: add $s0,$1,$s2
Memory : lw $s0,12($s3)
Immediate data : addi $s0,$s1,10
8.For the following C statement, what is the corresponding MIPS assembly code? f =
g + (h − 5). C01, K3
subi t0,h,5 add f,g,t0

9..For the following MIPS assembly instructions above, what is a corresponding C
statement? add g, h i,j and store in f CO1, K3
Ans: f=g+h+i+j
Add f,g,h
Add f,f,i
Add f,f,j
10. List out the fields of lw MIPS instructions. CO1, K2
Immediate type : lw destination register, source offset address(base address
register)
lw = opcode, rt= destination register , base address register = rs & offset address
= immediate.
11. How 32 bit data is loaded to a register? CO1, K2
Using lui opcode upper 16 bits are loaded. Then lower 16 bits are loaded using ori
opcode to the same register.

Part B Qs (with K level and CO)
Explain the operational concept of a computer in detail. (13) CO1, K2
Explain the various components of computer System with neat diagram (13).
CO1,K2
Explain operations and operands of computer Hardware in detail (13) CO1, K2
Discuss the Logical operations and control operations of computer (13) CO1,K2
Explain Branching operations with example. CO1, K2
Explain in detail about Instruction Execute cycle with diagram
Explain the following addressing modes in detail with diagram. CO1, K2
i)Immediate addressing ii)Register addressing, iii)Base or displacement
addressing, iv)PC-relative addressing v)Pseudo direct addressing

Online Certifications
COURSERA : COMPUTER ARCHITECTURE
https://www.coursera.org/learn/comparch
UDEMY : DESIGN OF A CPU
https://www.udemy.com/topic/computer-architecture/
NPTEL : COMPUTER ARCHITECTURE AND ORGANIZATION
https://nptel.ac.in/courses/106/105/106105163/

Real time Applications in day to day
life and to Industry
Latest Smart TVs
GPS Navigation Systems
Almost all Modern Day Smart Phones
Missile Guidance Systems
Space Exploration (Rovers)
Automobiles (ABS, Airbags)
Industries (Assembly Robots)
Road Safety Systems (Traffic Monitoring and Collision Alert Systems)

Contents beyond the Syllabus
Cloud Computing
https://www.youtube.com/watch?v=RWgW-CgdIk0

Assessment Schedule
Assessment I
Proposed Date : 22.09.2021
Actual Date : 22.09.2021

Text Books & References
TEXT BOOKS
1. Computer System Architecture M. M. Mano: 3rd ed., Prentice Hall of India,
New Delhi, 2017.
2. Computer Organization and Design: The Hardware/Software Interface, David
A. Patterson and John L. Hennessy, 2007
3. Computer Organization and Embedded Systems, Carl Hamacher, 2012.
REFERENCES
1. Computer Architecture and Organization, John P. Hayes.
2. Computer Organization and Architecture: Designing for Performance,
William Stallings.
3. Computer System Design and Architecture, Vincent P. Heuring and Harry F.
Jordan.

Mini Project Suggestions
Design and computer architecture: Design a processor with
minimum number of instructions, so that it can do the basic
arithmetic and logic operations
Design a instruction set for a limited functionality machine
having all instructions of 8-bits fixed length only, including
opcode and operands.
Write/create a tool for benchmarking of a hardware (CPU).

COA_UNIT-1new[1].pdf

Recommended

Recommended

More Related Content

Similar to COA_UNIT-1new[1].pdf

Similar to COA_UNIT-1new[1].pdf (20)

Recently uploaded

Recently uploaded (20)

COA_UNIT-1new[1].pdf