1. YUQI YANG
1993 Plymount St, Mountain View, CA 94043
Home: 862 371 9804
yuqiyang87@gmail.com
SUMMARY
I do ASIC Design, FPGA implementation and Simulation.
Familiar with C, VHDL, and Verilog language.
Matlab, HSPICE simulation were extensively used to design projects and other important
simulations. I have had good experience with designing software's such as Mentor graphics and
Cadence.
SKILLS AND TOOLS
 ASIC verification Cadence
 FPGA programming Hspice
 PCB layout ModelSim
 Matlab programming Mentor Graphics
 VHDL and Verilog programming QtSpim
 Static timing analysis Xlinx
WORK EXPERIENCE
ZTE CORPORATION(11/2009-03/2012)
Telecommunication Engineer
Supported the deployment of communication and control systems in rail and transit environments,
with a particular emphasis on Electronics Security Systems (ESS) including Closed Circuit
Television (CCTV) and Access Control Systems.
Provide design work for rail transit communications systems •Plans, schedules, conducts, and
coordinates assigned engineering work; monitors work for compliance to applicable codes,
accepted engineering practices, and government standards; •Ensures effective communication and
coordination on assigned projects between all disciplines and all other project participants.
PROJECT
SOFTWARE TPM USING ECC FOR EMBEDDED SYSTEM
 Designed a new method to implement Software Based TPM using ECC. This project was
designed using VHDL model to create schematics in IC schematic and layouts in IC
station.
 Optimized the design using Leonardo Spectrum. The system is implemented using an
uni-processor first and then it is extended to multiprocessor using pipe-lining technique.
This project tests us with the advanced level of VLSI knowledge. The main intention was
to reduce the iterations used in the algorithm computations.
EDUCATION
MASTER: ELECTRIC ENGINEERING
New Jersey Institute of Technology, Newark, NJ, US 2012-2014
GPA:3.65
BACHELOR: ELECTRIC ENGINEERING 2005-2009
Huazhong University of Science and Technology China