4. History of Trench-MOSFET
development
• Timeline of Trench-MOSFET
4
… ...
1993
First Trench-MOSFET
Siliconix
introduces industry-first
POWER MOSFETs
Base on Trench Technology
2000
Trench-MOSFET version II
2009
TrenchFET Gen III
Vishay
Develop the TrenchFET Gen III
2015
TrenchFET Gen IV2005
Siliconix
becomes a wholly owned subsidiary of Vishay
Developing TrenchFET
TrenchFET version II
2015
TI
NexFET
8. VDMOS-vertical double diffused
MOSFET
• Improve the current capability of the power MOSFET
• Advantage
• High breakdown voltage.
• Large Current Density.
• Disadvantage
• JFET effect
• Large Cgd
8
9. Trench-MOSFET
• Advantage:
• Low Rds(on)
As for VDMOS, Rds(on) = R(Source diffusion resistance)
+ R(Channel resistance) + R(Accumulation resistance) +
R(JFET component-resistance) + R(drift region resistance) +
R(substrate resistance) + R(wire resistance)
Removed JFET implies no R(JFET component-resistance).
And it is easy to make cell pitch smaller.
• Disadvantage:
• Large value of built-in capacitors
• Large capacitance from gate-to-
drain (Cgd).
9
10. 10
Cbuild-in Cgd
No JFET structure
Generate the advantage of
VDMOS High Breakdown
Voltage
Large value of built-
in capacitors
Large capacitance
from gate-to-drain
Fig.Trench-MOSFET structure[13]
12. The latest trench technology - TRENCHFET®
GEN IV
12
Latest Trench-MOSFET Vishay TrenchFET Gen IV
Package
(small to large)
Configuration VDS (V)
RDS(on) @ 4.5 V
(mΩ)
Qgd (nC)
ID Max.
(A)
PowerPAIR 3 x 3 N-type DUAL 30 Min 7-Max 13.8
Max 1.8-Min
0.7
30
ThinPower PAK1212-8 N-type SINGLE 30 12 1.6 38.3
PowerPAK1212-8 N-type SINGLE 30 Min 3.1-Max 12.5 Max 4-Min 1.6 20-40
So-8 N-type SINGLE 30 4.4 4 31.3
PowerPaKSo-8 N-type SINGLE
30,
40,60
Min 1.35-Max
13.5
Max 8.6-Min
1.6
20-100
PowerPAIR 6 x 5
skyFET
N-type DUAL PLUS INTEGRATED
SCHOTTKY
30 Min 1.75-Max 10
Max 5-Min
0.75
16-60
D2PAK(TO-263) N-type SINGLE 60 2.6 7.1 120
TO-220 N-type SINGLE 60 2.8 7.1 120
14. Lateral Double Diffused MOSFET
(LDMOS)
14
Fig. Lateral MOSFET structure representing the channel region under very small drain bias
voltages[9]
15. 15
Fig. Lateral MOSFET structure representing the channel region under channel pinch-off conditions and above
channel pinch-off conditions[9]
16. NexFET
• Cons
• The Trench-FET channel density is very high, leading to low channel
resistance. But the direct overlap of gate to drain results in large Cgd,
slowing down the switching speed, leading to high switching loss.
• Pros
• NexFET can reduce parasitic capacitances Cgd and Cgs, while achieving
similar specific RDS(ON), like in the Trench-FET technology.
16
17. The improvement from NexFET
• The gate has the minimum overlap with source and drain
regions and effectively shielded by the source metal.
• Low resistivity polycide gate material – reduced gate
resistance.
• Thick top reduces the metal resistance and prevents
electro-migration effects.
• The gate portions are minimized which reduce Cgs and
Cgd values.
• The field plate introduces a shielding effect which reduces
Cgd
• Shield effect helps to push the electric field distribution
towards the drain sinker.
17
Fig. Schematic cross-section of the first generation
NexFET[10]
18. • The current flow pass through the lateral
channel into the substrate.
• A heavily-doped drain sinker helps to direct
the current flow reach drain.
• Vertical current flow makes this device
suitable for carrying high current density.
• The heavily doped drain sinker region is very
helpful to achieve smaller resistance in chip
scale parts than conventional VDMOSFET.
18
Fig. Drain Down (right) NexFET Power
MOSFETs[11]
The Current Flow Of NexFET
19. Regions to support breakdown
• The one is the underneath of the
source contact
• Another one is along the LDD, N-
epitaxial layer and sinker region.
19
Fig. Schematic cross-section of the new
low voltage NexFET[12]
20. • Current flows through the
following path,
• Source Terminal on the substrate
• Vertical Sinker
• Metallization layer
• N+ Source Region
• Forwarded to drain terminal by
the LDD region.
20
Fig. Source Down (right) NexFET Power
MOSFETs[11]
21. Stack-Die Technique
• Stack-die Power Module Package technique
reduces the parasitic inductance and
resistance
• Structure of Stack-Die:
• Integration of high-side (HS) and low-
side (LS) transistors.
• Thick copper clips
• high-current connections such as input
and switching node terminals
• Substantially reduces the RDS(ON) of the
power block.
21
Fig. SEM image of NexFET Power Block[11]
27. Radiation Effects - Failures
• Total Ionizing Dose (TID)
• Total amount of radiation energy imparted to the electronic
device.
• TID CMOS structure vulnerability effects
• Change in Threshold Voltage (ΔVth ∝ tox
2)
• Sub threshold leakage current.
• Single Event Effects (SEE) – device status altering events.
• Single Event Upsets (SEU) - Heavy ion induced leakage current
turning on the self sustaining parasitic BJT
• Single Event Transients (SET) – Reversible transient glitch in
combinational logic caused by excessive charge formation
• Single Event Gate Rupture (SEGR) – Electrically overstressed
gate.
27
28. Effects of Radiation-on VDMOSFET
• Semiconductor Material (Lattice Displacement)
• Penetrating heavy ions create ehps in the
semiconductor through transfer of energy or Coulomb
Scattering[4] and Compton scattering[4].
• Redistribution of Electric field - ‘Funneling Effect’ to
maintain charge neutrality easier with higher electron
mobility (1350 cm2/V-s)[3].
• Gate MO (Ionization)
• Lower hole mobility (~10-4-10-11)[3]
• Trapped charges at various energy levels moving
towards SiO2-Si interface.
• MOSFET Drain is shorted to the base – parasitic
transistor is turned on.
28
N- Epi
Poly Gate
N+
N+P+ N+ P+
P-P-
29. Effects of Radiation-on P-LDMOSFET
• Advantage over VDMOS
• Benefits from the same layer
position of the Gate, Base and
Drain.
• Lower gate charge – higher
switching frequency (up to 1-2
GHz)[5]
• Compatible with TID hardened
CMOS fabrication process.
29
P-Epi
P+
SiO2
Poly Si
LDD N+P+ N+
P-Body
Source
Gate
Drain
32. Radiation Hardening
• Hardening process
• Hardened by Design (HBD) – provides better cost to performance.
-Combines current CMOS intrinsic hardness along with special transistor design
technology
• Layout Level enhancement Technologies
• Circuit Level enhancement Technologies
• Hardening by Process (HBP)
• Hard reset by watchdog timer
• Redundant circuits
32
33. Layout Level Enhancement
– Removal of Edge Leakage Current
• Annular gate/Enclosed Gate
Transistor
• Thin gate MO removes threshold voltage shifts. But due to
Ionizing radiation, the positive charge trapping gives rise to
various leakage current from drain source.
• Also, the presence of gate MO between transistors provides
path for intertransistional current that can be eliminated by
enclosing the gate with drain or source.[6][7]
• Enclosed Source Transistor
• Removal of leakage current by removing the edge.
• H Gate Transistor
• Dog Bone Transistor
33
[8]
[6]
34. Circuit level Enhancement
• Redundant circuits
• P1 and N1 works as a typical inverter
when Vi is ‘high’. And when Vi is
‘low’ the additional circuit output is
high, and N1 has a negative VGS. This
ensures the transistor is fully
turned-off reducing leakage current.
34
[1]
37. Benefits of Super-Junction
• Low RDS(on) and switching loss.
• Higher Breakdown Voltage for the same die size due to more
distributed electric field.
• Faster Switching due to smaller lightly doped region.
37
38. Low Voltage Super-Junction - Challenges
• Resistance of lightly doped
region is very small for low
voltages.
• So, low voltage super junction is
not very effective for reducing
RDS(ON).
38
39. Low Voltage Super-Junction – nextPower
MOSFET
39
• Combines the benefits of a LMOS
with that of a Trench MOS.
• Less cell density unlike Trench
MOSFET
• Low Qg and low QGD, Cout
• Better Safe Operating Area.
• Low RDS(on).
[16]
43. References
1. A. J. Womac “The Characterization of a CMOS Radiation Hardened by Design Circuit Technique”, Master’s
Thesis, University of Tennessee, Knoxville, 2013
2. M. M. Landowski “Design and Modeling of Radiation Hardened lateral Power MosFETs”, Master’s Thesis,
University of Central Florida, 2008
3. D. A. Neamen, “Semiconductor Physics and Devices: Basic Principles”, 4th ed., New York, NY: McGraw-Hill,
2012.
4. R. Lacoe, "CMOS Scaling, Design Principles and Hardening-by-Design Methodologies”, in IEEE NSREC,
Monterey, 2003.
5. A. A. Tanany “A Study of Switched Mode Power Amplifiers using LDMOS”, Master’s Thesis, University of
Gavle, 2007.
6. L. Zhi, N. Hongying, Y. Hongbo, L. Youbao “Design of a total-dose radiation hardened monolithic CMOS DC–
DC boost converter”, Journal of Semiconductors, Vol. 32, No. 7, pp. 075006-1 – 075006-6, Jul 2011.
7. L. J. Bissey, K. G. Duesman, W. M. Farnworth “Annular gate and technique for fabricating an annular gate”,
United States Patent, No. US 6,794,699 B2, Sept. 2004.
8. J. D. Cressier, H. A. Mantooth, “Extreme Environment Electronics”, CRC Press
43
44. References
9. B. J Baliga “Fundamentals of Power Semiconductor Devices”, Power Semiconductor Research Center North
Carolina State University, USA
10. J. Wang, J. Korec, S. Xu, “Low Voltage NexFET with Record Low Figure of Merit”, Texas Instruments
Incorporated, Power Stage BU Bethlehem, PA, USA
11. B. Yang, et.al, “NexFET Generation 2, New Way to Power”, Texas Instruments Incorporated
12. J. Wang, J. Korec, S. Xu, ”Low Voltage NexFET with Record Low Figure of Merit”, Texas Instruments
Incorporated, Power Stage BU, Bethlehem, PA, USA
13. J. Korec “Low Voltage Power MOSFETs – Design, Performance and Applications”, Vol. 7, Springer, ISBN:
978-1-4419-9319-9, 2011
14. J. Korec, C. Bull “History of FET technology and the Move to NexFETTM”, Bodo’s Power system, May 2009,
pp. 44-46.
15. S. Sapp, R. Sodhi, S. Sekhawat, “New Power Semiconductors Cut Data Center Energy”, Fairchild
Semiconductors, Oct. 2009.
16. P. Rutter, S. T. Peake “Low Voltage Superjunction Power MOSFET: An Application Optimized Technology ”,
26th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2011, pp. 491 – 497.
44
