Modified architecture of MAC using VLsI technology in verilog 2nd review.pptx

FPGA BASED IMPLEMENTATION OF AREA EFFICIENT
MAC UNIT USING VEDIC SQUARE AND KOGGE STONE
ADDER
PROJECT MEMBERS:
1. Ms.S.Arthi(810018106008)
2.Ms.R.Brindha(810018106010)
3.Ms.M.Kaviya(810018106032)
PROJECT GUIDE:
Dr.S.Subathradevi,
Asst.Prof/ECE,
Anna University,BITCampus,
Trichy, 620024.

OBJECTIVE
The aim of this project is to design a MAC unit
circuit which consumes lower area by using vedic square and
kogge stone adder.

In this project work we propose a new
architecture for an efficient MAC (Multiplier Accumulator
Unit) unit with low area consumption which includes vedic
square as an alternate component in the MAC unit. Here, we
use vedic square based on the principle of duplex property of
Urdhva Tiryagbhya sutra. One MAC unit is implemented by
vedic multiplier and kogge stone adder. Another MAC unit is
implemented by vedic multiplier and kogge stone adder. Here
we comparing these two MAC units. Hence, speed is increased
and area is decreased by means of decreased toggling of gates
in vedic square. The overall performance of MAC unit is
determined by three parameters, namely speed, power and area.
The proposed architecture of high speed and low area
consumption MAC unit will contribute immensely to the future
DSP systems.
ABSTRACT

MAC UNIT
(using vedic multiplier and kogge stone adder)
output

MAC UNIT
(using vedic square and kogge stone adder)

WORK PLAN
MODULES
ON FIRST
REVIEW
ON SECOND
REVIEW
ON THIRD
REVIEW
MODULE 1
VEDIC MULTIPLIER
(BITS:4,8)
VEDIC MULTIPLIER
(BITS:16)
VEDIC MULTIPLIER
(BITS:32)
MODULE 2
KOGGE STONE
ADDER
(BITS:8,16)
KOGGE STONE
ADDER
(BITS:32)
KOGGE STONE
ADDER
(BITS:64)
MODULE 3
MAC UNIT
(USING VEDIC MUL
AND KSA)
MAC UNIT
(USING VEDIC MUL
AND KSA)
MAC UNIT
(USING VEDIC MUL
AND KSA)
MODULE 4
VEDIC SQUARE
(BITS: 4,8)
VEDIC SQUARE
(BITS: 16)
VEDIC SQUARE
(BITS: 32)
MODULE 5
KOGGE STONE
ADDER
(BITS :8,16)
KOGGE STONE
ADDER
(BITS :32)
KOGGE STONE ADDER
(BITS : 64)
MODULE 6
MAC UNIT
(USING VEDIC
SQUARE AND KSA)
MAC UNIT
(USING VEDIC
SQUARE AND KSA)
MAC UNIT
(USING VEDIC
SQUARE AND KSA)

COMPLETED MODULE
VEDIC MULTIPLIER AND KOGGE STONE ADDER
Half adder - synthesized and simulated.
Full adder- synthesized and simulated.
4-bit vedic multiplier and kogge stone adder- synthesized and simulated.
Mac unit using vedic multiplier and kogge stone adder- synthesized and
simulated.
simulated.
simulated.
simulated.

COMPLETED MODULE
VEDIC SQUARE AND KOGGE STONE ADDER
Half adder - synthesized and simulated.
Full adder- synthesized and simulated.
4-bit vedic square and kogge stone adder- synthesized and simulated.
Mac unit using vedic square and kogge stone adder- synthesized and
simulated.
simulated.
simulated.
simulated.

MAC UNIT
4 BIT 8 BIT
slices LUT’s
Delay
in ns
slices LUT’s
Delay in
ns
Vedic multiplier 20/4656 36/9312 14.079 107/4656 193/9312 25.713
Kogge stone adder 8/4656 14/9312 12.540 20/4656 36/9312 19.909
MAC UNIT (vedic
mul & kogge stone
adder)
35/4656 61/9312 149/4656 266/9312
Vedic square 3/4656 6/9312 6.422 21/4656 36/9312 14.183
Kogge stone
adder
8/4656 14/9312 12.540 20/4656 36/9312 19.909
MAC UNIT
(vedic squ &
kogge stone
adder)
14/4656 26/9312 49/4656 92/9312

MAC UNIT
16 bit 32 bit
slices LUT’s
Delay
in ns
slices LUT’s
Delay in
ns
vedic multiplier 441/4656 771/9312 45.984
1869/4
656
3259/931
2
82.077
kogge stone adder 47/4656 87/9312 23.035
98/465
6
179/9312 23.134
MAC unit (vedic mul
& ksa)
517/4656 920/9312
2043/4
656
3601/931
2
Vedic square 70/4656 122/9312 24.394
244/46
56
424/9312 44.396
Kogge stone adder 47/4656 87/9312 23.035
98/465
6
179/9312 23.134
MAC unit (vedic
square & ksa)
152/4656 281/9312
416/46
56
759/9312

TOOLS USED
1) Xilinx is a software tool used.
2) HDL Verilog code is used.

REFERENCES
[1] Gitika Bhatia, Karanbir Singh Bhatia, “An Efficient MAC Unit Low Area Consumption”
International Conference on Advances in Recent Technologies in Communication and
Computing, 2015, pp. 186-355
[2] D. C. Chen, L. M. Guerra, E. H. Ng, M. Potkonjak, D. P. Schultz, and J. M. Rabaey, “An
integrated system for rapid prototyping of high performance algorithm specific data paths,”
International Conference on Application Specific Array Processors, Aug 1992, pp. 134-148
[3] Aminul Islam, M.W. Akram, S.D. Pable, Mohd. Hasan, "Design and Analysis of Robust Dual
Threshold CMOS Full Adder Circuit in 32nm Technology”, International Conference on
Advances in Recent Technologies in Communication and Computing, 2010, pp. 418-420
[4] Deepa Sinha, Tripti Sharma, K.G.Sharma, Prof B.P Singh, “Design and Analysis of low Power
1-bit Full Adder Cell”, International Conference on Electronics Computer Technology
(ICECT), Vol. 2, 2011, pp. 303-305

[5] Nabihah Ahmad, Rezaul Hasan, “A new Design of XOR-XNOR gates for Low
Power application”, International Conference on Electronic Devices, Systems and
Applications (ICEDSA), 2011, pp. 45-49
[6] R.Uma, “4-Bit Fast Adder Design: Topology and Layout with Self-Resetting Logic
for Low Power VLSI Circuits”, International Journal of Advanced Engineering
Sciences and Technology, Vol No. 7, Issue No. 2, 2011, pp. 29-37
[7] David J. Willingham and izzet Kale, “A Ternary Adiabatic Logic (TAL)
Implementation of a Four-Trit Full-Adder, NORCHIP, 2011, pp. 1-4
[8] Padma Devi, Ashima Girdher and Balwinder Singh, “Improved Carry Select Adder
with Reduced Area and Low Power
Consumption”, International Journal of Computer Application, Vol 3. Issue.4, June
2010, pp. 14-18 .

Modified architecture of MAC using VLsI technology in verilog 2nd review.pptx

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