With ever increasing demand of speed, accuracy and space we need better hardware and software. Software can be made better by making faster algorithms. As far as arithmetic algorithms are concerned in digital hardware, division is the least used one, computers experience performance degradation if division is ignored. There are various fields in digital world which demand excessive multiplication and division. For them algorithms based on Vedic Mathematics have proved to be much faster than other algorithms and there is further room for improvement also, which attracts further attention from researchers working on these algorithms.

1. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
1 NITTTR, Chandigarh EDIT-2015
Binary Division Algorithms based on Vedic
Mathematics: A Review
1
Satnam Singh Shergill, 2
Arvind Kumar
1,2
Dept. of Electronics and Communication, U.I.E.T., P.U., Chandigarh
ABSTRACT – With ever increasing demand of speed,
accuracy and space we need better hardware and software.
Software can be made better by making faster algorithms. As
far as arithmetic algorithms are concerned in digital
hardware, division is the least used one, computers experience
performance degradation if division is ignored. There are
various fields in digital world which demand excessive
multiplication and division. For them algorithms based on
Vedic Mathematics have proved to be much faster than other
algorithms and there is further room for improvement also,
which attracts further attention from researchers working on
these algorithms.
I. INTRODUCTION
Today the computers have evolved very much since their
creation. However, one thing has not changed. The main
function of computers is to do the mathematical operations
to run programs. Computers process lots of binary numbers
based addition, multiplication and division. In comparison
to other mathematical operations, division is the least used
operation. However, if we ignore division, there will be
performance.
With increasing reliance on technology in every field like
payment through NFC, cloud data storage etc. we need
better cryptographic solutions, and elliptic curve
cryptography is one of them. But elliptic curve
cryptography involves calculations on about 200-600 digits
and for those calculations to be economical we need
arithmetic algorithms to be fast and less space consuming.
Improving division algorithm is one those tasks.
Also, with the ever rising quality of image and video
signals, we need faster algorithms to absorb the effect of
more calculation delays associated with their processing.
Digital Signal Processing is another area which requires
faster processing of high number of bits.
So, there is always need for faster and better algorithms in
computing world.
And algorithms based on Vedic Mathematics have proved
to be much faster than other algorithms and there is further
room for improvement also, which attracts further attention
from researchers working on these algorithms.
II. RELATED WORK
Prabir Saha et al [1]
used Nikhilam Navatascaramam
Dasatah (NND) sutra of Vedic Mathematics to develop a
Vedic Divider Architecture for binary numbers and it was
implemented on spice spectre through existing 90nm
CMOS technology. Comparison of new architecture was
done with digit recurrence, convergence and series
expansion based architectures and found improvement of
50%, 45% and 41% respectively in vedic architecture.
Furthermore power consumption was less by 44%, 35%
and 27% respectively. They calculated that EDP(Energy
Delay Product) was reduced by 73% compared with series
expansion based architecture(the best architecture reported
so far).
Diganta Sengupta et al[2]
used Nikhilam Navatascaramam
Dasatah (NND) sutra and Parvartya Yojayet sutra to
develop a division algorithm for BCD numbers. Their
work involved adjusting the divisor and then carrying out
other steps of algorithm in which each partial remainder
needed to be normalized. To calculate the time taken for
division, each division was iterated 10,000 times at each
run of the program and compared the time taken by the
algorithm with that of Non Restore Type division
algorithm for the same set of divisors and dividends. It was
found that for 2 digit divisor and dividend vedic division
took 0.150µs whereas Non Restore Type division took
0.800µs. For 15 digit dividend and 6 digit divisor vedic
division took 2.490µs and Non Restore Type division took
49.290µs. It was seen that the difference in time taken
increased with the increase in number of digits proving
vedic division much better in division involving large
number of digits.
Soma BhanuTej[3]
of IBM Systems and Technology Group
applied Parvartya Yojayet sutra of Vedic Mathematics to
develop a high performance divider and comparison of
static timing analysis was done between vedic divider and
conventional divider. A 32 bit dividend and 16 bit divisor
binary vedic divider was synthesised using 180nm and
32nm standard cell libraries on Cadence nclauch and
comparison was done with conventional divider and it was
found that vedic divider saved power in the range of
109mW and was ~7 times faster and area occupied was
~13 times lesser than conventional divider.
Ratiranjan Senapati et al[4]
implemented Parvartya Yojayet
sutra vedic divider using Xilinx ISE on 90nm CMOS
technology. They implemented 8 bit binary dividend by 4
bit binary divisor circuitry and found that propagation
delay was only ~19.9ns and consumed ~34mW power.
Compared to repetitive subtraction method this algorithm
had ~46% less propagation delay and consumed ~27% less
power.
Shantanu Oke et al[5]
used another Vedic Mathematics
sutra called Dhwajam sutra to develop Distinctive Division
Achitecture and the algorithms was implemented on Xilinx
8.1 ISE and they tested the results on Spartan 3 FPGA
platform also. Comparing their algorithm with Newton-
Raphson algorithm, it was stated that their algorithm was
much less complex and needed less number of steps and
their was no need of look up table in their algorithm as was
their in Newton-Raphson and SRT algorithm.
R. Thamil Chelvan and S. Roobini Priya[6]
implemented
RSA encryption/ decryption algorithm using Dhvajanka
sutra also called Dhwajam sutra for fixed and floating
point binary numbers. They implemented the algorithm on
FPGA using Xilinx Spartan library using Verilog HDL. It
was found that gate delay for RSA circuitry using 8x8

2. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 2
overlay multiplier architecture and 16 bit by 16 bit vedic
division was 1.507 µs whereas for Restoring Type division
algorithm the gate delay was 2.838 µs and for Non Restore
Type division algorithm it was 2.828 µs.
Najib Ghatte et al[7]
used Vedic Mathematics to implement
a IEEE 754 single precision floating point division
algorithm using Verilog HDL and simulations were done
using ModelSim SE Plus 6.5. It was then synthesised for
VirtexTM
-5 FPGA family device XC5VLX30. It was
found that there was about 12% improvement in utilization
of the resources as compared to Restoring/ Non Restoring
type division algorithms. The combinational delay was just
5.405ns and power consumption was reduced to 2mW
whereas traditional ALU’s consume more power.
Surabhi Jain et al[8]
developed high speed deconvolution
algorithm using Binary division algorithms based on Vedic
Mathematics. They used Nikhilam and Parvartya sutra and
implementation was done on Xilinx ISE using Verilog
HDL. Simulated results showed a reduction in delay of
19% as compared to conventional methods.
III. CONCLUSION
In this work, our focus was on the application of Vedic
Mathematics for binary fixed point and floating point
divisions. The work done by the authors referred to in this
work has proven that Vedic Division algorithms can be
used for the development of faster and less power
consuming devices and also it has been shown that the area
consumed is less in Vedic Division implementations as
compared to other algorithms which makes these
algorithms more suitable for mobile application because
mobile devices need to have required functionality at the
least possible power and space consumption.
REFERENCES
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
(2011) ‘Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI
Applications’, International Symposium on Electronic System Design.
Diganta Sengupta, Mahamuda Sultana and Atal Chaudhuri (2013) ‘
Vedivision – A Fast BCD Division Algorithm Facilitated by Vedic
Mathematics’, International Journal of Computer Science & Information
Technology, Vol. 5, No. 4, pp.67-80.
Soma BhanuTej, IBM Systems and Technology Group, Bangalore, India.
Ratiranjan Senapati, Bandan Kumar Bhoi, Manoranjan Pradhan (2013)
‘Novel Binary Divider Architecture for high speed VLSI applications’,
Proceedings of 2013 I.E.E.E. Conference on Information and
Communication Technologies.
Shantanu Oke, Suraj Lulla, Prathamesh Lad (2014) ‘VLSI (FPGA)
Design for Distinctive Division Architecture using the Vedic Sutra
‘Dhwajam’’, International Conference on Devices, Circuits and
Systems(ICDCS).
R. Thamil Chelvan, S. Roobini Priya (2013), ‘Implementation of Fixed
And Floating Point Division Using Dhvajanka Sutra’, International
Journal of VLSI and Embedded Systems-IJVES, Vol. 04, Issue 02, pp.
234-237.
Najib Ghatte, Shilpa Patil, Deepak Bhoir (2014) ‘Single Precision
Floating Point Division’, IRF International Conference.
Surabhi Jain, Mukul Pancholi, Harsh Garg, Sandeep Saini (2014) ‘Binary
Division Algorithm and High Speed Deconvolution Algorithm(Based on
Ancient Indian Vedic Mathematics)’, IEEE.