This document summarizes a research paper that proposes applying principles of Vedic mathematics to optimize the design of multipliers, squarers, and cubers. It begins by providing background on multipliers and their importance in electronic systems. It then reviews related work applying Vedic mathematics to multiplier design. The document outlines the methodology for performing multiplication, squaring, and cubing according to Vedic mathematics principles. It presents simulation and synthesis results comparing the proposed Vedic designs to traditional array-based designs, finding improvements in speed, power, and area. The document concludes that Vedic mathematics provides an effective approach for optimizing the design of these fundamental arithmetic components.
ALU Using Area Optimized Vedic MultiplierIJERA Editor
The load on general processor is increasing. For Fast Operations it is an extreme importance in Arithmetic Unit. The performance of Arithmetic Unit depends greatly on it multipliers. So, researchers are continuous searching for new approaches and hardware to implement arithmetic operation in huge efficient way in the terms of speed and area. Vedic Mathematics is the old system of mathematics which has a different technique of calculations based on total 16 Sutras. Proposed work has discussion of the quality of Urdhva Triyakbhyam Vedic approach for multiplication which uses different way than actual process of multiplication itself. It allows parallel generation of elements of products also eliminates undesired multiplication steps with zeros and mapped to higher level of bit using Karatsuba technique with processors, the compatibility to various data types. It is been observed that lot of delay is required by the conventional adders which are needed to have the partial products so in the work it is further optimized the Vedic multiplier type Urdhva Triyakbhyam by replacing the traditional adder with Carry save Adder to have more Delay Optimization. The proposed work shows improvement of speed as compare with the traditional designs. After the proposal discussion of the Vedic multiplier in the paper, It is been used for the implementation of Arithmetic unit using proposed efficient Vedic Multiplier it is not only useful for the improve efficiency the arithmetic module of ALU but also it is useful in the area of digital signal processing. The RTL entry of proposed Arithmetic unit done in VHDL it is synthesized and simulated with Xilinx ISE EDA tool. At the last the proposed Arithmetic Unit is validated on a FPGA device Vertex-IV.
An advancement in the N×N Multiplier Architecture Realization via the Ancient...VIT-AP University
Multiplication is an crucial unfussy, basic
function in arithmetic procedures and Vedic mathematics is a
endowment prearranged for the paramount of human race,
due to the capability it bestows for quicker intellectual
computation. This paper presents the effectiveness of Urdhva
Triyagbhyam Vedic technique for multiplication which cuffs
a distinction in the authentic actual development of
multiplication itself. It facilitates parallel generation of
partial products and eradicates surplus, preventable
multiplication steps. The anticipated N×N Vedic multiplier is
coded in VHDL (Very High Speed Integrated Circuits
Hardware Description Language), synthesized and simulated
using Xilinx ISE Design Suite 13.1. The projected
architecture is a N×N Vedic multiplier whilst the VHDL
coding is done for 128×128 bit multiplication process. The
result shows the efficiency in terms of area employment and
rapidity
Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using ...VIT-AP University
In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per this proposed architecture, for two 32-bit numbers; the multiplier and multiplicand, each are grouped as 16-bit numbers so that it decomposes into 16×16 multiplication modules. It is also illustrated that the further hierarchical decomposition of 8×8 modules into 4×4 modules and then 2×2 modules will have a significant VHDL coding of for 32x32 bits multiplication and their used FPGA family Virtex 7 low power implementation by Xilinx Synthesis 16.1 tool done. The synthesis results show that the computation time for calculating the product of 32x32 bits is delay 29.256 ns. (11.499ns logic, 11.994ns route) (48.9% logic, 51.1% route).
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Introducing the Concept of Back-Inking as an Efficient Model for Document Ret...IJITCA Journal
Today, many institutions and organizations are facing serious problem due to the tremendously increasing
size of documents, and this problem is further triggering the storage and retrieval problems due to the
continuously growing space and efficiency requirements. This problem is becoming more complex with
time and the increase in the size and number of documents in an organization. Therefore, there is a
growing demand to address this problem. This demand and challenge can be met by developing a
technique to enable specialized document imaging people to use when there is a need for storing
documents images. Thus, we need special and efficient storage techniques for this type of information
storage (IS) systems.
In this paper, we present an efficient storage technique for electronic documents. The proposed technique
uses the Information Pixels concept to make the technique more efficient for certain image formats. In
addition, we shall see how Storing Information Pixels Addresses ( SIPA ) method is an efficient method for
document storage and as a result makes the document image storage relatively efficient for most image
formats.
ALU Using Area Optimized Vedic MultiplierIJERA Editor
The load on general processor is increasing. For Fast Operations it is an extreme importance in Arithmetic Unit. The performance of Arithmetic Unit depends greatly on it multipliers. So, researchers are continuous searching for new approaches and hardware to implement arithmetic operation in huge efficient way in the terms of speed and area. Vedic Mathematics is the old system of mathematics which has a different technique of calculations based on total 16 Sutras. Proposed work has discussion of the quality of Urdhva Triyakbhyam Vedic approach for multiplication which uses different way than actual process of multiplication itself. It allows parallel generation of elements of products also eliminates undesired multiplication steps with zeros and mapped to higher level of bit using Karatsuba technique with processors, the compatibility to various data types. It is been observed that lot of delay is required by the conventional adders which are needed to have the partial products so in the work it is further optimized the Vedic multiplier type Urdhva Triyakbhyam by replacing the traditional adder with Carry save Adder to have more Delay Optimization. The proposed work shows improvement of speed as compare with the traditional designs. After the proposal discussion of the Vedic multiplier in the paper, It is been used for the implementation of Arithmetic unit using proposed efficient Vedic Multiplier it is not only useful for the improve efficiency the arithmetic module of ALU but also it is useful in the area of digital signal processing. The RTL entry of proposed Arithmetic unit done in VHDL it is synthesized and simulated with Xilinx ISE EDA tool. At the last the proposed Arithmetic Unit is validated on a FPGA device Vertex-IV.
An advancement in the N×N Multiplier Architecture Realization via the Ancient...VIT-AP University
Multiplication is an crucial unfussy, basic
function in arithmetic procedures and Vedic mathematics is a
endowment prearranged for the paramount of human race,
due to the capability it bestows for quicker intellectual
computation. This paper presents the effectiveness of Urdhva
Triyagbhyam Vedic technique for multiplication which cuffs
a distinction in the authentic actual development of
multiplication itself. It facilitates parallel generation of
partial products and eradicates surplus, preventable
multiplication steps. The anticipated N×N Vedic multiplier is
coded in VHDL (Very High Speed Integrated Circuits
Hardware Description Language), synthesized and simulated
using Xilinx ISE Design Suite 13.1. The projected
architecture is a N×N Vedic multiplier whilst the VHDL
coding is done for 128×128 bit multiplication process. The
result shows the efficiency in terms of area employment and
rapidity
Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using ...VIT-AP University
In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per this proposed architecture, for two 32-bit numbers; the multiplier and multiplicand, each are grouped as 16-bit numbers so that it decomposes into 16×16 multiplication modules. It is also illustrated that the further hierarchical decomposition of 8×8 modules into 4×4 modules and then 2×2 modules will have a significant VHDL coding of for 32x32 bits multiplication and their used FPGA family Virtex 7 low power implementation by Xilinx Synthesis 16.1 tool done. The synthesis results show that the computation time for calculating the product of 32x32 bits is delay 29.256 ns. (11.499ns logic, 11.994ns route) (48.9% logic, 51.1% route).
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Introducing the Concept of Back-Inking as an Efficient Model for Document Ret...IJITCA Journal
Today, many institutions and organizations are facing serious problem due to the tremendously increasing
size of documents, and this problem is further triggering the storage and retrieval problems due to the
continuously growing space and efficiency requirements. This problem is becoming more complex with
time and the increase in the size and number of documents in an organization. Therefore, there is a
growing demand to address this problem. This demand and challenge can be met by developing a
technique to enable specialized document imaging people to use when there is a need for storing
documents images. Thus, we need special and efficient storage techniques for this type of information
storage (IS) systems.
In this paper, we present an efficient storage technique for electronic documents. The proposed technique
uses the Information Pixels concept to make the technique more efficient for certain image formats. In
addition, we shall see how Storing Information Pixels Addresses ( SIPA ) method is an efficient method for
document storage and as a result makes the document image storage relatively efficient for most image
formats.
Design of Low Power Vedic Multiplier Based on Reversible LogicIJERA Editor
Reversible logic is a new technique to reduce the power dissipation. There is no loss of information in reversible logic and produces unique output for specified inputs and vice-versa. There is no loss of bits so the power dissipation is reduced. In this paper new design for high speed, low power and area efficient 8-bit Vedic multiplier using Urdhva Tiryakbhyam Sutra (ancient methodology of Indian mathematics) is introduced and implemented using Reversible logic to generate products with low power dissipation. UT Sutra generates partial product and sum in single step with less number of adders unit when compare to conventional booth and array multipliers which will reduce the delay and area utilized, Reversible logic will reduce the power dissipation. An 8-bit Vedic multiplier is realized using a 4-bit Vedic multiplier and modified ripple carry adders. The proposed logic blocks are implemented using Verilog HDL programming language, simulation using Xilinx ISE software
Optimising Data Using K-Means Clustering AlgorithmIJERA Editor
K-means is one of the simplest unsupervised learning algorithms that solve the well known clustering problem. The procedure follows a simple and easy way to classify a given data set through a certain number of clusters (assume k clusters) fixed a priori. The main idea is to define k centroids, one for each cluster. These centroids should be placed in a cunning way because of different location causes different result. So, the better choice is to place them as much as possible far away from each other.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of an Efficient 64 bit MACIJERA Editor
The design of optimized 64 bit multiplier and accumulator (MAC) unit is implemented in this paper. MAC unit plays major role in many of the digital signal processing (DSP) applications. The MAC unit is designed with the combinations of multipliers and adders. In the proposed method MAC unit is implemented using Vedic multiplier and the adder is done with ripple carry adder .The components are reduced by implementing Vedic multiplier using the techniques of Vedic mathematics that have been modified to improve performance. a high speed processor depends significantly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. The area is optimized effectively using Vedic multiplier .The total design implemented using Xilinx.
ENHANCING MULTIPLIER SPEED IN FAST FOURIER TRANSFORM BASED ON VEDIC MATHEMATICSVLSICS Design
Vedic mathematics is an ancient system of mathematics which has a unique technique of calculations based
on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam
Navatashcaramam Dashatah, and Anurupye Vedic mathematical algorithms. These algorithms gives
minimum delay and used for multiplication of all types of numbers. The performance of high speed multiplier
is designed and compared using these sutras for various NxN bit multiplications and implemented on the
FFT of the DSP processor. Anurupye sutra on FFT is made efficient than Urdhva tiryabhyam and Nikhilam
Navatashcaramam Dashatah sutras by more reduction in computation time. This gives the method for
hierarchical multiplier design. Logic verification of these designs is verified by simulating the logic circuits
in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL coding.
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth
multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device.
FPGA IMPLEMENTATION OF HIGH SPEED BAUGH-WOOLEY MULTIPLIER USING DECOMPOSITION...eeiej_journal
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the
speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3
device.
Relation between Type-II Discrete Sine Transform and Type -I Discrete Hartley...IJERA Editor
In this paper, a relation for finding type-II discrete sine transform (DST) from type-I discrete Hartley transform (DHT) has been derived. The transform length N is taken as even. Using this relation, the (N - 1) output components of DST can be realized from DHT. The DHT is one of the transforms used for converting data in time domain into frequency domain using only real values.
Graph Theory Based Approach For Image Segmentation Using Wavelet TransformCSCJournals
This paper presents the image segmentation approach based on graph theory and threshold. Amongst the various segmentation approaches, the graph theoretic approaches in image segmentation make the formulation of the problem more flexible and the computation more resourceful. The problem is modeled in terms of partitioning a graph into several sub-graphs; such that each of them represents a meaningful region in the image. The segmentation problem is then solved in a spatially discrete space by the well-organized tools from graph theory. After the literature review, the problem is formulated regarding graph representation of image and threshold function. The boundaries between the regions are determined as per the segmentation criteria and the segmented regions are labeled with random colors. In presented approach, the image is preprocessed by discrete wavelet transform and coherence filter before graph segmentation. The experiments are carried out on a number of natural images taken from Berkeley Image Database as well as synthetic images from online resources. The experiments are performed by using the wavelets of Haar, DB2, DB4, DB6 and DB8. The results are evaluated and compared by using the performance evaluation parameters like execution time, Performance Ratio, Peak Signal to Noise Ratio, Precision and Recall and obtained results are encouraging.
Improving Performance of Back propagation Learning Algorithmijsrd.com
The standard back-propagation algorithm is one of the most widely used algorithm for training feed-forward neural networks. One major drawback of this algorithm is it might fall into local minima and slow convergence rate. Natural gradient descent is principal method for solving nonlinear function is presented and is combined with the modified back-propagation algorithm yielding a new fast training multilayer algorithm. This paper describes new approach to natural gradient learning in which the number of parameters necessary is much smaller than the natural gradient algorithm. This new method exploits the algebraic structure of the parameter space to reduce the space and time complexity of algorithm and improve its performance.
A Time-Area-Power Efficient High Speed Vedic Mathematics Multiplier using Com...Kumar Goud
Abstract: With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
Keywords—4:2 Compressor, 7:2 Compressor, Booth’s multiplier, high speed multiplier, modified Booth’s multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Efficient High Speed Vedic Multiplierijsrd.com
Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large.
Design of Low Power Vedic Multiplier Based on Reversible LogicIJERA Editor
Reversible logic is a new technique to reduce the power dissipation. There is no loss of information in reversible logic and produces unique output for specified inputs and vice-versa. There is no loss of bits so the power dissipation is reduced. In this paper new design for high speed, low power and area efficient 8-bit Vedic multiplier using Urdhva Tiryakbhyam Sutra (ancient methodology of Indian mathematics) is introduced and implemented using Reversible logic to generate products with low power dissipation. UT Sutra generates partial product and sum in single step with less number of adders unit when compare to conventional booth and array multipliers which will reduce the delay and area utilized, Reversible logic will reduce the power dissipation. An 8-bit Vedic multiplier is realized using a 4-bit Vedic multiplier and modified ripple carry adders. The proposed logic blocks are implemented using Verilog HDL programming language, simulation using Xilinx ISE software
Optimising Data Using K-Means Clustering AlgorithmIJERA Editor
K-means is one of the simplest unsupervised learning algorithms that solve the well known clustering problem. The procedure follows a simple and easy way to classify a given data set through a certain number of clusters (assume k clusters) fixed a priori. The main idea is to define k centroids, one for each cluster. These centroids should be placed in a cunning way because of different location causes different result. So, the better choice is to place them as much as possible far away from each other.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of an Efficient 64 bit MACIJERA Editor
The design of optimized 64 bit multiplier and accumulator (MAC) unit is implemented in this paper. MAC unit plays major role in many of the digital signal processing (DSP) applications. The MAC unit is designed with the combinations of multipliers and adders. In the proposed method MAC unit is implemented using Vedic multiplier and the adder is done with ripple carry adder .The components are reduced by implementing Vedic multiplier using the techniques of Vedic mathematics that have been modified to improve performance. a high speed processor depends significantly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. The area is optimized effectively using Vedic multiplier .The total design implemented using Xilinx.
ENHANCING MULTIPLIER SPEED IN FAST FOURIER TRANSFORM BASED ON VEDIC MATHEMATICSVLSICS Design
Vedic mathematics is an ancient system of mathematics which has a unique technique of calculations based
on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam
Navatashcaramam Dashatah, and Anurupye Vedic mathematical algorithms. These algorithms gives
minimum delay and used for multiplication of all types of numbers. The performance of high speed multiplier
is designed and compared using these sutras for various NxN bit multiplications and implemented on the
FFT of the DSP processor. Anurupye sutra on FFT is made efficient than Urdhva tiryabhyam and Nikhilam
Navatashcaramam Dashatah sutras by more reduction in computation time. This gives the method for
hierarchical multiplier design. Logic verification of these designs is verified by simulating the logic circuits
in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL coding.
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth
multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device.
FPGA IMPLEMENTATION OF HIGH SPEED BAUGH-WOOLEY MULTIPLIER USING DECOMPOSITION...eeiej_journal
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the
speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3
device.
Relation between Type-II Discrete Sine Transform and Type -I Discrete Hartley...IJERA Editor
In this paper, a relation for finding type-II discrete sine transform (DST) from type-I discrete Hartley transform (DHT) has been derived. The transform length N is taken as even. Using this relation, the (N - 1) output components of DST can be realized from DHT. The DHT is one of the transforms used for converting data in time domain into frequency domain using only real values.
Graph Theory Based Approach For Image Segmentation Using Wavelet TransformCSCJournals
This paper presents the image segmentation approach based on graph theory and threshold. Amongst the various segmentation approaches, the graph theoretic approaches in image segmentation make the formulation of the problem more flexible and the computation more resourceful. The problem is modeled in terms of partitioning a graph into several sub-graphs; such that each of them represents a meaningful region in the image. The segmentation problem is then solved in a spatially discrete space by the well-organized tools from graph theory. After the literature review, the problem is formulated regarding graph representation of image and threshold function. The boundaries between the regions are determined as per the segmentation criteria and the segmented regions are labeled with random colors. In presented approach, the image is preprocessed by discrete wavelet transform and coherence filter before graph segmentation. The experiments are carried out on a number of natural images taken from Berkeley Image Database as well as synthetic images from online resources. The experiments are performed by using the wavelets of Haar, DB2, DB4, DB6 and DB8. The results are evaluated and compared by using the performance evaluation parameters like execution time, Performance Ratio, Peak Signal to Noise Ratio, Precision and Recall and obtained results are encouraging.
Improving Performance of Back propagation Learning Algorithmijsrd.com
The standard back-propagation algorithm is one of the most widely used algorithm for training feed-forward neural networks. One major drawback of this algorithm is it might fall into local minima and slow convergence rate. Natural gradient descent is principal method for solving nonlinear function is presented and is combined with the modified back-propagation algorithm yielding a new fast training multilayer algorithm. This paper describes new approach to natural gradient learning in which the number of parameters necessary is much smaller than the natural gradient algorithm. This new method exploits the algebraic structure of the parameter space to reduce the space and time complexity of algorithm and improve its performance.
A Time-Area-Power Efficient High Speed Vedic Mathematics Multiplier using Com...Kumar Goud
Abstract: With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
Keywords—4:2 Compressor, 7:2 Compressor, Booth’s multiplier, high speed multiplier, modified Booth’s multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Efficient High Speed Vedic Multiplierijsrd.com
Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large.
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...iosrjce
This paper anticipated the design of a novel Vedic Multiplier using the techniques of Ancient Indian
Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly
on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in
general processors. Currently the speed of the multipliers is limited by the speed of the adders used for partial
product addition. In this paper, we proposed an 8-bit multiplier using the new methodology of Vedic
Mathematics called as Urdhva-Tiryagbhyam sutra which is used for generating the partial products. The partial
product addition in Vedic multiplier is realized using carry-skip technique. This paper depicts the design of an
efficient 8×8 binary arithmetic multiplier by using Vedic Mathematics. From various multiplication techniques,
Urdhva-Tiryagbhyam sutra is being implemented because this sutra is applicable to all cases of algorithms for
N×N bit numbers and the minimum delay is obtained. A 4×4 Vedic Multiplier is designed using 9 –full adder
and a special 4-bit adder which is having reduced delay. Then 8-bit multiplier is designed using four 4-bit
multiplier and 3-ripple carry adder. Then 8×8 Vedic Multiplier is coded in VHDL, synthesized and simulated
using Xilinx ISE8.2 Software. Finally the objective of this paper lies in design of an efficient vedic multiplier
using Urdhva–Tiryakbhyam Sutra in VHDL Environment.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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VLSI ARCHITECTURE OF AN 8-BIT MULTIPLIER USING VEDIC MATHEMATICS IN 180NM TEC...P singh
A Multiplier is one of the key hardware blocks in most fast processing system which requires less power dissipation. A conventional multiplier consumes more power. This paper presents a low power 8 bit Vedic Multiplier (VM) based on Vertically & Crosswise method of Vedic mathematics, a general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. The implementation is done using cadence Virtuoso tool. The power dissipation of 8x8 bit Vedic multiplier obtained after synthesis is compared with conventional multipliers such as Wallace tree and array multipliers and found that the proposed Vedic multiplier circuit seems to have better performance in terms of power dissipation.
Binary Division Algorithms based on Vedic Mathematics: A ReviewIJEEE
With ever increasing demand of speed, accuracy and space we need better hardware and software. Software can be made better by making faster algorithms. As far as arithmetic algorithms are concerned in digital hardware, division is the least used one, computers experience performance degradation if division is ignored. There are various fields in digital world which demand excessive multiplication and division. For them algorithms based on Vedic Mathematics have proved to be much faster than other algorithms and there is further room for improvement also, which attracts further attention from researchers working on these algorithms.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High speed multiplier using vedic mathematicseSAT Journals
Abstract
The digital signal processing in today’s time need high speed computation. The basic building block of signal processing in
Communication, Biomedical signal processing, and Image processing remains Fast Fourier Transform (FFT). FFT computation
involves multiplications and additions. Speed of the DSP processor mainly depends on the speed of the multiplier. Time delay, power
dissipation and the silicon chip area. These are the most important parameters for the fast growing technology. The conventional
multiplication method requires more time and area and hence more power dissipation. In this paper an ancient Vedic multiplication
method called “Urdhva Triyakbhyam” is implemented. It is a method based on 16 sutras of Vedic mathematics. Vedic Mathematics
reduces the number of operations to be carried out compared to the conventional method. The code description is simulated and
synthesized using FPGA device Spartan XC3S400-PQ208.
Keywords— Vedic Multiplication, Urdhva Tiryakbhayam , FFT
FPGA Implementation of High Speed 8bit Vedic Multiplier using Barrel Shifterdbpublications
In today’s world Vedic mathematics has
proved to be the most robust technique for arithmetic
operations. In contrast, conventional techniques for
multiplication provide significant amount of delay in hardware
implementation of n-bit multiplier. Moreover, the
combinational delay of the design degrades the performance
of the multiplier. Hardware-based multiplication mainly
depends upon architecture selection in FPGA or ASIC.
A barrel shifter is a digital circuit that can shift a data word by
a specified number of bits in one clock cycle. It can be
implemented as a sequence of multiplexers (mux.), and in
such an implementation the output of one mux is connected to
the input of the next mux in a way that depends on the shift
distance.
Verilog Implementation of an Efficient Multiplier Using Vedic MathematicsIJERA Editor
In this paper, the design of a 16x16 Vedic multiplier has been proposed using the 16 bit Modified Carry Select Adder and 16 bit Kogge Stone Adder. The Modified Carry Select Adder incorporates the Binary to Excess -1 Converter (BEC) and is known to be the fastest adder as compared to all the conventional adders. The design is implemented using the Verilog Hardware Description Language and tested using the Modelsim simulator. The code is synthesized using the Virtex-7 family with the XC7VX330T device. The Vedic multiplier has applications in Digital Signal Processing, Microprocessors, FIR filters and communication systems. This paper presents a comparison of the results of 16x16 Vedic multiplier using Modified Carry Select Adder and 16x16 Vedic Multiplier using Kogge Stone Adder. The results show that 16x16 Vedic Multiplier using Modified Carry Select Adder is more efficient and has less time delay as compared to the 16x16 Vedic Multiplier using Kogge Stone Adder.
This paper presents different computational algorithms to implement single
precision floating point division on field programmable gate arrays (FPGA).
Fast division computation algorithms can apply to all division cases by
which an efficient result will be obtained in terms of delay time and power
consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra)
technique enhances the computational speed of the mantissa module and this
module is used to design a 32-bit floating point multiplier which is the
crucial feature of this proposed design, which yields a higher computational
speed and reduced delay time. The proposed design of floating-point divider
using fast computational algorithms synthesized using Verilog hardware
description language has a 32-bit floating point multiplier module unit and a
32-bit floating point subtractor module unit. Xilinx Spartan 6 SP605
evaluation platform is used to verify this proposed design on FPGA.
Synthesis results provide the device utilization and propagation delay
parameters for the proposed design and a comparative study is done with
previous work. Input to the divider is provided in IEEE 754 32-bit formats.
Design of Efficient 4×4 Quaternary Vedic Multiplier Using Current-Mode Multi-...idescitation
Vedic multiplier is based on ancient Indian Vedic mathematics that offers
simpler and hierarchical structure. Multi-valued logic results in the effective utilization of
interconnections, which reduces the chip size and delay. This paper proposes a new design
of 4×4 Vedic multiplier using quaternary current-mode multi-valued logic, equivalent to
iplier has
very low transistor-count and consumes very low power as compared to other multiplier
designs. Since the performance of a digital signal processor depends mainly on the
multipliers used, the proposed approach can greatly enhance the performance of a digital
signal processing system.
Design and Implentation of High Speed 16x16 CMOS Vedic MultiplierEECJOURNAL
In today scenario digital circuits are become more and more complex because of long arithmetic calculations but with the help of Vedic mathematics that calculations can become easy and fast. To make multiplier we have different techniques, in this paper we design 16x16 CMOS multiplier using Vedic mathematics technique.
RTL Verification and FPGA Implementation of 4x4 Vedic MultiplierMohd Esa
The objective of this paper is to study 4x4 Vedic multiplier.
Multiplication is an important fundamental function in arithmetic operations.
Vedic multiplier using Urdhva-Tiryagbyam sutra is predominant in
performance evaluation of parameters such as power, area & delay. This paper
presents design, verification and FPGA implementation of Vedic multiplier.
Verification is carried out in Questa Sim 10.4e using System Verilog HVL and
design is carried out in Xilinx ISE Design Suite 14.7 using Verilog HDL
environment
These days we have an increased number of heart diseases including increased risk of heart attacks. Our proposed system users sensors that allow to detect heart rate of a person using heartbeat sensing even if the person is at home. The sensor is then interfaced to a microcontroller that allows checking heart rate readings and transmitting them over internet. The user may set the high as well as low levels of heart beat limit. After setting these limits, the system starts monitoring and as soon as patient heart beat goes above a certain limit, the system sends an alert to the controller which then transmits this over the internet and alerts the doctors as well as concerned users. Also the system alerts for lower heartbeats. Whenever the user logs on for monitoring, the system also displays the live heart rate of the patient. Thus concerned ones may monitor heart rate as well get an alert of heart attack to the patient immediately from anywhere and the person can be saved on time.This value will continue to grow if no proper solution is found. Internet of Things (IoT) technology developments allows humans to control a variety of high-tech equipment in our daily lives. One of these is the ease of checking health using gadgets, either a phone, tablet or laptop. we mainly focused on the safety measures for both driver and vehicle by using three types of sensors: Heartbeat sensor, Traffic light sensor and Level sensor. Heartbeat sensor is used to monitor heartbeat rate of the driver constantly and prevents from the accidents by controlling through IOT.
ABSTRACT The success of the cloud computing paradigm is due to its on-demand, self-service, and pay-by-use nature. Public key encryption with keyword search applies only to the certain circumstances that keyword cipher text can only be retrieved by a specific user and only supports single-keyword matching. In the existing searchable encryption schemes, either the communication mode is one-to-one, or only single-keyword search is supported. This paper proposes a searchable encryption that is based on attributes and supports multi-keyword search. Searchable encryption is a primitive, which not only protects data privacy of data owners but also enables data users to search over the encrypted data. Most existing searchable encryption schemes are in the single-user setting. There are only few schemes in the multiple data users setting, i.e., encrypted data sharing. Among these schemes, most of the early techniques depend on a trusted third party with interactive search protocols or need cumbersome key management. To remedy the defects, the most recent approaches borrow ideas from attribute-based encryption to enable attribute-based keyword search (ABKS
Cloud computing is the one of the emerging techniques to process the big data. Large collection of set or large
volume of data is known as big data. Processing of big data (MRI images and DICOM images) normally takes
more time compare with other data. The main tasks such as handling big data can be solved by using the concepts
of hadoop. Enhancing the hadoop concept it will help the user to process the large set of images or data. The
Advanced Hadoop Distributed File System (AHDF) and MapReduce are the two default main functions which
are used to enhance hadoop. HDF method is a hadoop file storing system, which is used for storing and retrieving
the data. MapReduce is the combinations of two functions namely maps and reduce. Map is the process of
splitting the inputs and reduce is the process of integrating the output of map’s input. Recently, in medical fields
the experienced problems like machine failure and fault tolerance while processing the result for the scanned
data. A unique optimized time scheduling algorithm, called Advanced Dynamic Handover Reduce Function
(ADHRF) algorithm is introduced in the reduce function. Enhancement of hadoop and cloud introduction of
ADHRF helps to overcome the processing risks, to get optimized result with less waiting time and reduction in
error percentage of the output image
Text mining has turned out to be one of the in vogue handle that has been joined in a few research
fields, for example, computational etymology, Information Retrieval (IR) and data mining. Natural
Language Processing (NLP) methods were utilized to extricate learning from the textual text that is
composed by people. Text mining peruses an unstructured form of data to give important
information designs in a most brief day and age. Long range interpersonal communication locales
are an awesome wellspring of correspondence as the vast majority of the general population in this
day and age utilize these destinations in their everyday lives to keep associated with each other. It
turns into a typical practice to not compose a sentence with remedy punctuation and spelling. This
training may prompt various types of ambiguities like lexical, syntactic, and semantic and because of
this kind of indistinct data; it is elusive out the genuine data arrange. As needs be, we are directing
an examination with the point of searching for various text mining techniques to get different
textual requests via web-based networking media sites. This review expects to depict how
contemplates in online networking have utilized text investigation and text mining methods to
identify the key topics in the data. This study concentrated on examining the text mining
contemplates identified with Facebook and Twitter; the two prevailing web-based social networking
on the planet. Aftereffects of this overview can fill in as the baselines for future text mining research.
Colorectal cancer (CRC) has potential to spread within the peritoneal cavity, and this transcoelomic
dissemination is termed “peritoneal metastases” (PM).The aim of this article was to summarise the current
evidence regarding CRC patients at high risk of PM. Colorectal cancer is the second most common cause of cancer
death in the UK. Prompt investigation of suspicious symptoms is important, but there is increasing evidence that
screening for the disease can produce significant reductions in mortality.High quality surgery is of paramount
importance in achieving good outcomes, particularly in rectal cancer, but adjuvant radiotherapy and chemotherapy
have important parts to play. The treatment of advanced disease is still essentially palliative, although surgery for
limited hepatic metastases may be curative in a small proportion of patients.
Heat transfer in pipes is a distinctive kind of procedure employed in heat exchanger which transfers great
deal of heat because of the impact of capillary action and phase change heat transfer principle. Late improvement
in the heat pipe incorporates high thermal conductivity liquids like Nano liquids, fixed inside to extricate the most
extreme heat. This paper audits, impact of different factors, for example, thermal pipe tilt edge, charged measure
of working liquid, nano particles sort, size, and mass/volume part and its impact on the change of thermal
proficiency, thermal exchange limit and decrease in thermal protection. The Nano liquid arrangement and the
examination of its thermal attributes likewise have been investigated. The retained sun oriented vitality is
exchanged to the working liquid streaming in the pipe. The execution of the framework is affected by thermal
exchange from tube to working liquid, with least convective misfortunes, which must be considered as one of the
essential plan factor. In tube and channel streams, to improve the rate of heat exchange to the working liquid,
detached enlargement methods, for example, contorted tapes and swirl generators are employed from the fluid
flow path. The variation of heat transfer coefficient and pressure drop in the pipe flow for water and water based
Al2O3 Nano fluids at different volume concentrations and twisted tapes are studied.
Now-a-day’s pedal powered grinding machine is used only for grinding purpose. Also, it requires lots of efforts
and limited for single application use. Another problem in existing model is that it consumed more time and also has
lower efficiency. Our aim is to design a human powered grinding machine which can also be used for many purposes
like pumping, grinding, washing, cutting, etc. it can carry water to a height 8 meter and produces 4 ampere of electricity
in most effective way. The system is also useful for the health conscious work out purpose. The purpose of this technical
study is to increase the performance and output capacity of pedal powered grinding machine.
This project proposes a distributed control approach to coordinate multiple energy storage units
(ESUs) to avoid violation of voltage and network load constraints ESU as a buffer can be a promising
solution which can store surplus power during the peak generation periods and use it in peak load
periods.In ESU converters both active and reactive power are used to deal with the power quality
issues in distribution network ESU’s reactive power is proposed to be used for voltage support, while
the active power is to be utilized in managing network loading.
The steady increase in non-linear loads on the power supply network such as, AC variable speed drives,
DC variable Speed drives, UPS, Inverter and SMPS raises issues about power quality and reliability. In this
subject, attention has been focused on harmonics . Harmonics overload the power system network and cause
reliability problems on equipment and system and also waste energy. Passive and active harmonic filters are
used to mitigate harmonic problems. The use of both active and passive filter is justified to mitigate the
harmonics. The difficulty for practicing engineers is to select and deploy correct harmonic filters , This paper
explains which solutions are suitable when it comes to choosing active and passive harmonic filters and also
explains the mistakes need to be avoided.
This Paper is aimed at analyzing the few important Power System equipment failures generally
occurring in the Industrial Power Distribution system. Many such general problems if not resolved it may
lead to huge production stoppage and unforeseen equipment damages. We can improve the reliability of
Power system by simply applying the problem solving tool for every case study and finding out the root cause
of the problem, validation of root cause and elimination by corrective measures. This problem solving
approach to be practiced by every day to improve the power system reliability. This paper will throw the light
and will be a guide for the Practicing Electrical Engineers to find out the solution for every problem which
they come across in their day to day maintenance activity.
Today internet security is a serious problem. For every consumer and business that is on the Internet,
viruses, worms and crackers are a few security threats. There are the obvious tools that aid information security
professionals against these problems such as anti-virus software, firewalls and intrusion detection systems, but
these systems can only react to or prevent attacks-they cannot give us information about the attacker, the tools
used or even the methods employed. Given all of these security questions honeypots are a novel approach to
network security and security research alike. It is a resource, which is intended to be attacked and compromised to
gain more information about the attacker and the used tools. It can also be deployed to attract and divert an
attacker from their real targets. Honeypots is an additional layer of security. Honeypots have the big advantage that
they do not generate false alerts as each observed traffic is suspicious, because no productive components are
running on the system. The levels of interaction determines the amount of functionality a honeypots provides that
is low and high interactions.
More from IJET - International Journal of Engineering and Techniques (20)
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Vaccine management system project report documentation..pdfKamal Acharya
The Division of Vaccine and Immunization is facing increasing difficulty monitoring vaccines and other commodities distribution once they have been distributed from the national stores. With the introduction of new vaccines, more challenges have been anticipated with this additions posing serious threat to the already over strained vaccine supply chain system in Kenya.
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The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
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When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
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Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
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Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
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Ijet v5 i6p2
1. International Journal of Engineering and Techniques - Volume 5 Issue 6,November 2019
ISSN: 2395-1303 http://www.ijetjournal.org Page 1
VeMSC: Application of Vedic Mathematics for designing Multipliers,
Squarers and Cubers
Patil Siddhant Vitthal1
, Dr. Pravin Mane2
1,2
Department of Electrical and Electronics Engineering,
BITS Pilani - Goa Campus, India - 403726
Email:1
f20150475@goa.bits-pilani.ac.in, 2
pravinmane@goa.bits-pilani.ac.in
I. INTRODUCTION
A multiplier is the basic component of an
electronic system. It is at the heart of
Microprocessors, Digital Signal Processing Systems
[1] and Mobile Telecommunication Systems [2].
Multiplication is the basic computation required in
Convolution, Discrete Fourier Transform (DFT)
and Fast Fourier Transform (FFT). Multipliers also
have wide applications in the field of Image
Processing. Images are made up of pixels and the
RGB values of these pixels are structured in the
form of matrices. Image processing involves
calculations with the pixel values that require
matrix multiplication [3]. Therefore, the demand for
high speed, low power and area-efficient multipliers
is increasing day by day. The normal pen-paper
multiplication algorithm needs to be modified in a
way to reduce the number of calculation steps and
introduce parallelism into the process. The reduced
number of calculations help to reduce the required
resources for getting the final accurate result.
Reduction in the number of resources helps in
reducing the power dissipation and the length of the
critical path, which in turn reduces the delay time.
Another possible solution for getting better
performance would be using approximate
multipliers as described in [4]–[6]. This solution
would be application-specific. It would be effective
only in the case of error-resilient applications [7],
[8] because certain applications cannot tolerate the
erroneous results produced by approximate
calculations.
The paper considers the application of the
proposed methodology for both types, error-
resilient and non-error-resilient applications.
Therefore, it considers Vedic Mathematics as a
viable solution and focuses on its implementation.
The paper also elaborates on designing Squarer and
Cuber circuits due to their wide range of
applications in polynomial approximation [9], [10]
and robotics [11].
Vedic Mathematics is the ancient Indian
system of mathematics that was rediscovered in the
early twentieth century from the Vedas by Sri
Bharati Krishna Tirthaji Maharaj (1884-1960) [12].
It is used by people to tackle mathematical
problems mentally. Vedic Mathematics is classified
RESEARCH ARTICLE OPEN ACCESS
Abstract:
Multipliers are the indispensable part of an electronic system. Due to multipliers being at the heart of an electronic
system, it is necessary to optimize them in terms of path delay, power dissipation and area consumption. The optimization of
these parameters helps in improving the overall performance of the electronic system. The paper targets on the improvement
in the performance of the existing multiplier, squarer and cuber designs by using the different principles mentioned in Vedic
Mathematics. Simulation and synthesis is performed for designs using 2-bit, 4-bit, 8-bit and 16-bit operands using Cadence -
Simulation Analysis Environment SimVision (64)14.10-s007, Cadence - NCLaunch (64)14.10-s007 and Cadence Encounter
(R) RTL Compiler RC14.10. The most captivating observation from the results is that performing a cube of a 2-bit number
using principles of Vedic Mathematics requires 96.52×less time, 99.141×less power and 98.92×less area as compared to
performing cube of a 2-bit number using multiple stages of an array multiplier.
Keywords — Accurate Computation, Vedic Mathematics, Urdhva Triyak Technique, Multipliers, Dvanda, Square,
Cube
2. International Journal of Engineering and Techniques - Volume 5 Issue 6,November 2019
ISSN: 2395-1303 http://www.ijetjournal.org Page 2
into 16 sutras, out of which, only two i.e. Nikhilam
Sutra and Urdhva Triyak Technique are applicable
TABLE I
SIMULATION AND SYNTHESIS RESULTS OF ARRAY AND BOOTH'S MULTIPLIER
for multiplication. Nikhilam Sutra is a specific
technique that simplifies multiplication for integers
closer to the powers of 10 and the Urdhva Triyak
Technique is a general technique i.e. it has no
restrictions on the numeric value of the multiplier
and the multiplicand. Therefore, this paper explores
the Urdhva Triyak Technique for performing
multiplication. The implementation and analysis of
different Vedic Multipliers are carried out using
Cadence - Simulation Analysis Environment
SimVision (64)14.10-s007, Cadence - NCLaunch
(64) 14.10-s007 and Cadence Encounter (R) RTL
Compiler RC14.10.
Contributions: The major contributions of the
present work are:
Simulation and synthesis results of 2×2 bits,
4×4 bits, 8×8 bits, 16×16 bits Vedic multipliers
using Urdhva Triyak Technique and integrated
architecture approach
Design and implementation results of 2-bit, 4-
bit, 8-bit and 16-bit squarers using principles of
Vedic Mathematics and getting improved
performance as compared to performing the
same operation using array multipliers
A novel design for obtaining the cube of 2-bit,
4-bit, 8-bit and 16-bit number using principles
of Vedic Mathematics and getting improved
performance as compared to performing the
same operation using array multipliers
The paper is organized into 5 sections. Section II
provides the Simulation and Synthesis results of the
Array and Booth’s multiplier, which are the basis
for showing improvement in the designs proposed
in the later sections of this paper. Section II also
enlightens on the related work in the field of Vedic
Mathematics. Section III presents the methodology
of Vedic multiplication and gives a clear picture to
the reader about using Vedic Mathematics for
performing Square and Cube of a number.
Simulation and synthesis results of 2×2 bits, 4×4
bits, 8×8 bits and 16×16 bits Vedic Multipliers, 2-
bit, 4-bit, 8-bit and 16-bit squarer and 2-bit, 4-bit, 8-
bit and 16-bit cuber are described in Section IV.
Section V concludes the paper by pointing out
valuable observations and giving future directions.
II. BACKGROUND AND RELATED WORK
Background: The simulation and synthesis results
of 2×2 bits Array Multiplier (AM2×2), 4×4 bits
Array Multiplier (AM4×4), 8×8 bits Array
Multiplier (AM8×8), 16×16 bits Array Multiplier
(AM16×16), 2×2 bits Booth’s Multiplier (BM2×2),
4×4 bits Booth’s Multiplier (BM4×4), 8×8 bits
Booth’s Multiplier (BM8×8) and 16×16 bits
Booth’s Multiplier (BM16×16) are summarized in
Table I. These values form the basis for finding the
extent of improvement in proposed designs.
Related Work: Ranjan Kumar Barik et. al. (2016)
in ‘Time efficient signed vedic multiplier using
redundant binary representation’ [13] propose a
new method of signed multiplication. The design is
based on the Urdhva Triyak Sutra of Vedic
Mathematics. The performance of the proposed
multiplier is far better as compared to conventional
multipliers.
Ms. Gadakh et. al. (2016) in ‘FPGA
implementation of high speed vedic multiplier’ [14]
elaborate on the 16 Sutras of Vedic Mathematics.
The paper shows the implementation of 2×2 bits
Vedic Multiplier using the Urdhva Triyak
technique. It uses the 2×2 bits Vedic Multiplier as
the basic building block and constructs a 4×4 bits
Vedic Multiplier using these blocks. It also
discusses the FPGA implementation of the 8×8 bits
Vedic Multiplier using the newly constructed 4×4
bits Vedic Multiplier blocks.
Nagaraju N. et. al. (2015) in ‘FPGA
implementation of an efficient vedic multiplier’
[15] aim to implement an 8×8 bits Vedic Multiplier
using 4×4 bits Vedic Multiplier blocks. 3:2
compressors are used for reducing the number of
gates required for performing the addition of the
partial product terms. This method gives better
performance as compared to the designs proposed
3. International Journal of Engineering and Techniques - Volume 5 Issue 6,November 2019
ISSN: 2395-1303 http://www.ijetjournal.org Page 3
in [8] due to the reduction in the critical path length
as less number of gates are utilized.
Anannya Maiti et. al. (2016) in ‘Design and
implementation of 4 bit vedic multiplier’ [16]
implements a 4×4 bits Vedic Multiplier without
using a 2×2 bits Vedic Multiplier block. It uses
propagation delay as the parameter for merit. It
concludes that 4×4 bits Vedic Multipliers are better
in terms of performance than Array Multipliers.
Premananda B.S. et. al. (2013) in ‘Design
and implementation of 8-bit vedic multiplier’ [17]
implement 8×8 bits Vedic Multiplier using 4×4 bits
Vedic Multiplier blocks. It uses a modified ripple-
carry addition for shifting the carry generated by
the partial products.
Vengadapathiraj. M et. al. (2015) in ‘Design
of high speed 128×128 bit vedic multiplier using
high speed adder’ [18] uses 2×2 bits Vedic
Multiplier as the building block for implementing
128×128 bits Vedic Multiplication. It considers the
Combinational Path delay as the factor for deciding
a better multiplier. It shows the effect of
implementing addition using different adders like
Carry Save Adder (CSA), Carry Select Adder
(CLA) and Ripple Carry Adder (RCA) on the time
delay.
L. Srirman et. al. (2013) in ‘Design and
FPGA implementation of binary squarer using
vedic mathematics’ [19] proposes squarer based on
Ekadhikena Purvena Sutra. This squarer is useful
only for decimal numbers ending with ‘5’. It is a
specific squarer. The paper concludes that the
proposed squarer is better as compared to an array
squarer for squaring numbers ending with ‘5’.
The literature review shows that
multiplication performed using Vedic Mathematics
outperforms other techniques of multiplication. The
implementations of Vedic Multipliers use modular
architecture. No work can be found in the literature
that uses an integrated architecture approach for
designing Vedic multipliers having operand size
more than 4-bits.
Fig. 1 Multiplication of two 3-bit binary numbers using
Urdhva Triyak Technique
Fig. 2 Split version for calculation of partial product terms
Also, no designs have been proposed that
use Vedic Mathematics for designing Cubers
having operand size beyond 2-bits. No comparison
exists between the simulation and synthesis results
obtained on performing square and cube of a
number using multiple stages of array multipliers
and techniques prescribed in Vedic Mathematics.
Therefore, the paper focuses on designing Vedic
Multipliers, Squarers and Cubers as mentioned in
the Contributions.
III. METHODOLOGY
A. Urdhva Triyak Technique
‘Urdhva Triyak’ is a Sanskrit word. It
means Vertically and Crosswise. It is the most
powerful technique when it comes to Vedic
Multiplication as it is a General Technique. It is
also referred to as Urdhva Triyagbhyam sutra. The
multiplication methodology is explained with the
help of Fig. 1. It demonstrates the multiplication of
two 3-bit numbers. The first step involves
computation of the sum of partial products i.e. a0b0,
a1b0 + a0b1, a2b0 + a1b1 + a0b2, a2b1 + a1b2 and a2b2.
The second step is the transfer of carry from right to
left. It is to be noted that the terms pertaining to the
partial products are generated at the same time as
they are independent of each other. The
simultaneous generation of partial products helps in
the reduction of the computation time. Fig. 2 aims
to aid the visualization of the user for understanding
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the calculation of partial product terms. The
methodology shown in Fig. 2 can be extended to
‘n’× ‘n’ bits multiplication, where n ϵ Integer.
Fig. 3 shows the entire multiplication
process with the help of a numerical example using
a binary multiplicand and multiplier. It
demonstrates bit-wise multiplication of two 4-bit
numbers. As mentioned previously, in the first step,
all the partial product terms are calculated. The
horizontal arrows from right to left indicate the shift
of carry bits. Fig. 4 represents the Data Flow Graph
Fig. 3 Multiplication of two 4-bit numbers using Urdhva
Triyak Technique
for the same. The proposed design is unlike the
designs discussed in Section II. It uses the modular
multiplier concept. It does not use the 2×2 bits
Vedic Multiplier as a building block.
B. Square of a number
The square of a number is calculated by
using the basic block called Dvanda. Calculating
square of a number using Dvanda is known as
Dvanda Yoga. The definition of a Dvanda is as
follows:
D(a) = a2
(1)
D(bc) = 2 × b × c (2)
D(def) = 2 × d × f + e2
(3)
D(ghij) = g × j + h × i (4)
where ‘a’, ‘bc’, ‘def’, ‘ghij’ are 1-bit, 2-bit, 3-bit,
and 4-bit numbers respectively. The Dvanda Yoga
is further elaborated with the help of an example
using decimal operands as shown in Fig. 5. The
same method can be applied to binary numbers.
The first step is to calculate all the Dvandas.
This step is followed by shifting the carries from
right to left for arriving at the final result.
Fig. 4 Data Flow Graph for 4×4 bits Vedic Multiplication
Fig. 5 Numerical example for calculating the square of a 2
digit number using Vedic Mathematics
Fig. 6 shows the flowchart for finding the square of
a 4-bit number. The calculations of this method
seem to be similar to Urdhva Triyak Technique, but
they are different in a way that they require less
number of resources as compared to performing the
same operation using Vedic multipliers using
Urdhva Triyak Technique. Reduced number of
resources also help to reduce power and delay of
the circuit. This statement is supported by facts and
numerical figures in the results section.
C. Cube of a number
Vedic Mathematics explores the identity
mentioned in equation 5 for performing cube of a
number.
(a + b)3
= a3
+ 3 × a2
× b + 3 × a × b2
+ b3
(5)
The use of this identity is explained by
performing the calculations for finding the cube of
52 as shown in Fig. 7. In the example, 52 is split as
(50+2) i.e. 50 and 2. Therefore, ‘a’ in the identity is
replaced by 5 and ‘b’ is replaced by 2. Note that ‘a’
is 5 and not 50. This data computation concludes
towards giving correct results because the carry
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chain takes care of the place value of the number.
Therefore, this method requires the computation of
53
and not 503
. This methodology saves a lot of
Fig. 6 Flowchart for finding the square of a 4-bit number
Fig. 7 Numerical example for calculating the cube of a 2 digit
number using Vedic Mathematics
resources and reduces the path length and delay.
The positivity of this design is supported by facts
and figures in the results section. The partial
product terms are calculated and the carry is shifted
from right to left. In Fig. 7, the horizontal arrows
from right to left indicate the shift of carry. The
method shown works as long as the numbers are 2
digits wide. In the binary system, we can use the
abovementioned technique only for 2-bit operands.
In order to extend the application of Vedic
Mathematics for performing cube of 4-bit, 8-bit and
16-bit numbers the following method is proposed.
The method uses an indirect form of modular
approach and is explained with an example as
shown in Fig. 8. Consider the case where we intend
to calculate the cube of a 4 digit number. We split
the number into two parts: the lower two digits and
the upper two digits of significance. We use
equation 5, where ‘a’ is replaced by the upper two
digits and ‘b’ is replaced by the lower two digits of
the given number. We use the previously designed
Vedic Multiplier, Squarer and Cuber Circuits of
suitable port widths for the intermediate
computations. In each stage, 2 digits are retained
and the carry is shifted from right to left.
In general, if we have an ‘n’ bit number,
where ‘n’ is an even integer, we split the number
into two parts of n/2 bits each. We apply equation 5
and retain n/2 bits in each stage.
Fig. 8 Numerical example for calculating the cube of a 4 digit
number using Vedic Mathematics
IV. DESIGN AND IMPLEMENTATION RESULTS
The section is split into 3 parts, namely the
results of Vedic Multiplier, the results of Vedic
Squarer and the results of Vedic Cuber.
A. Results of Vedic Multiplier
Table II summarizes the result of Vedic Multipliers
for operands of varying bit-width.
TABLE II
SIMULATION AND SYNTHESIS RESULTS OF VEDIC MULTIPLIER
Comparing the results with Table I, an
observation can be made that Vedic Multipliers
always consume less amount of area as compared to
the Array Multipliers. Although the power
consumption of Vedic Multipliers is more than the
Array Multipliers of respective bit-widths, their
delay is considerably less. As two out of the three
design parameters are improving, we can say that
the Vedic Multipliers are better as compared to the
traditional Array Multipliers. Fig. 9 shows the gate
level representation of the 2×2 bits Vedic
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Multiplier. It uses 1 NOT gate, 6 AND gates and 1
XOR gate.
Fig. 9 Gate level representation for 2×2 bits Vedic Multiplier
B. Results of Vedic Squarer
The simulation and synthesis results of the
Vedic Squarer are summarized in Table III. The
Area, Power and Delay of Vedic Squarer is less in
all the cases when compared to performing the
same operation as compared to the Array
Multiplier. Area and Power savings of up to
63.63% and 74.47% respectively are achieved by
TABLE III
SIMULATION AND SYNTHESIS RESULTS OF VEDIC SQUARER
the Vedic Squarer when compared to the use of
Array Multipliers for performing the square
operation. Delay is reduced up to 72.036%.
Fig. 10 shows the gate level representation
of the circuit for performing the square of a 2-bit
number. It uses 1 NOT gate, 1 AND gate and 1
NOR gate. Comparing Fig. 9 and Fig. 10 it can be
seen that Fig. 10 uses less number of resources as
compared to Fig. 9. This is due to the simplification
of equations 1 and 2 to the following equations, the
reason being that we are dealing with binary
numbers.
D(a1) = a1
2
= a1 (6)
D(a1a0) = 2 × a1 × a0
= [10]2 × a1 × a0 (7)
D(a0) = a0
2
= a0 (8)
Equation 7 involves multiplication with
[10]2 = [2]10. Therefore, the bit s1 is permanently set
to 0. Thus, for performing square of a 2-bit number
it would be efficient to implement the method
described above, rather than using 2×2 bits Vedic
Multiplier.
Fig. 10 Gate level representation for the square of a 2-bit
number
C. Results of Vedic Cuber
Table IV summarizes the simulation and
synthesis results of the Vedic Cuber. Area savings
of up to 98.92%, a power reduction of up to 99.14%
and delay reduction of up to 96.529% are achieved
using the proposed designs when compared to using
TABLE IV
SIMULATION AND SYNTHESIS RESULTS OF VEDIC CUBER
an ‘n’בn’ Array Multiplier followed by ‘2n’ב2n’
Array Multiplier for performing cube of an ‘n’-bit
number.
Fig. 11 shows the gate level representation
of the Vedic 2-bit Cuber. The circuit uses only a
single AND gate. When compared to Fig. 9 and
Fig. 10, this design is the most efficient in terms of
performance parameters as it uses the least number
of resources. The reduction in the number of
resources can be explained by the simplification of
equation 5 for binary numbers as shown in
equations 9 and 10.
(a1a0)2
3
= a1
3
| 3 × a1
2
× a0 | 3 × a1 × a0
2
| a0
3
(9)
= a1 | 3 × a1 × a0 | 3 × a1 × a0 | a0 (10)
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The LSB bit of output is always set to a0 and
the method requires computation of one logical
operation a1 × a0 i.e. a1 AND a0.
Fig. 11 Gate level representation for the cube of a 2-bit
number
V. CONCLUSIONS
The literature survey shows that multipliers
implemented using Vedic Mathematics are faster as
compared to normal array multipliers. Also, the
previously proposed designs use a modular design
approach for designing higher bit multipliers. In
this paper, we use an integrated architecture
approach for implementation. The paper enlightens
on the use of principles mentioned in Vedic
Mathematics for performing square and cube of a
number. A novel technique for performing a cube
of a number exceeding 2-bits is proposed in this
paper.
The most captivating observation from the
results is that performing cube of a 2-bit number
using principles of Vedic Mathematics requires
96.52×less time, 99.141×less power and 98.92×less
area as compared to performing cube of a 2-bit
number using multiple stages of an array multiplier.
Similar values can be obtained for 4-bit, 8-bit and
16-bit cubers. Hence, the principles of Vedic
Mathematics leave a large scope for improving the
performance of current mathematical operations.
The designs discussed in the paper can be
used in circuits which involve a large number of
multiplications like the Digital Signal Processing
and Image Processing Circuits. Also, approximate
circuits can be designed using the circuits proposed
in the paper, by manipulating with the carry chains
or introducing truncation [6], [20], [21]. These
approximate circuits can then be applied to error-
resilient applications [22] for improving their
performance. Thus, Vedic Mathematics leaves a
large scope for exploration.
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